1 /**************************************************************************//**
2 * @file spi.h
3 * @version V3.00
4 * @brief M2L31 series SPI driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __SPI_H__
10 #define __SPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup SPI_Driver SPI Driver
23 @{
24 */
25
26 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
27 @{
28 */
29
30 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
31 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
32 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
33 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
34
35 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
36 #define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
37
38 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
39 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
40 #define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
41
42 /* SPI Interrupt Mask */
43 #define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
44 #define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
45 #define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
46 #define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
47 #define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
48 #define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
49 #define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
50 #define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
51 #define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
52 #define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
53
54 /* SPI Status Mask */
55 #define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
56 #define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
57 #define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
58 #define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
59 #define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
60 #define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
61 #define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */
62 #define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */
63
64
65 /* I2S Data Width */
66 #define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
67 #define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
68 #define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
69 #define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
70
71 /* I2S Audio Format */
72 #define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
73 #define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
74
75 /* I2S Data Format */
76 #define SPII2S_FORMAT_I2S (0U<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
77 #define SPII2S_FORMAT_MSB (1U<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
78 #define SPII2S_FORMAT_PCMA (2U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
79 #define SPII2S_FORMAT_PCMB (3U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
80
81 /* I2S Operation mode */
82 #define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
83 #define SPII2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */
84
85 /* I2S Record Channel */
86 #define SPII2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
87 #define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
88
89 /* I2S Channel */
90 #define SPII2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
91 #define SPII2S_LEFT (1U) /*!< Select left channel \hideinitializer */
92
93 /* I2S Interrupt Mask */
94 #define SPII2S_FIFO_TXTH_INT_MASK (0x01U) /*!< TX FIFO threshold interrupt mask \hideinitializer */
95 #define SPII2S_FIFO_RXTH_INT_MASK (0x02U) /*!< RX FIFO threshold interrupt mask \hideinitializer */
96 #define SPII2S_FIFO_RXOV_INT_MASK (0x04U) /*!< RX FIFO overrun interrupt mask \hideinitializer */
97 #define SPII2S_FIFO_RXTO_INT_MASK (0x08U) /*!< RX FIFO time-out interrupt mask \hideinitializer */
98 #define SPII2S_TXUF_INT_MASK (0x10U) /*!< TX FIFO underflow interrupt mask \hideinitializer */
99 #define SPII2S_RIGHT_ZC_INT_MASK (0x20U) /*!< Right channel zero cross interrupt mask \hideinitializer */
100 #define SPII2S_LEFT_ZC_INT_MASK (0x40U) /*!< Left channel zero cross interrupt mask \hideinitializer */
101
102 /*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
103
104
105 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
106 @{
107 */
108
109 /**
110 * @brief Clear the unit transfer interrupt flag.
111 * @param[in] spi The pointer of the specified SPI module.
112 * @return None.
113 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
114 * \hideinitializer
115 */
116 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
117
118 /**
119 * @brief Disable Slave 3-wire mode.
120 * @param[in] spi The pointer of the specified SPI module.
121 * @return None.
122 * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
123 * \hideinitializer
124 */
125 #define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
126
127 /**
128 * @brief Enable Slave 3-wire mode.
129 * @param[in] spi The pointer of the specified SPI module.
130 * @return None.
131 * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
132 * \hideinitializer
133 */
134 #define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
135
136 /**
137 * @brief Trigger RX PDMA function.
138 * @param[in] spi The pointer of the specified SPI module.
139 * @return None.
140 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
141 * \hideinitializer
142 */
143 #define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
144
145 /**
146 * @brief Trigger TX PDMA function.
147 * @param[in] spi The pointer of the specified SPI module.
148 * @return None.
149 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
150 * \hideinitializer
151 */
152 #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
153
154 /**
155 * @brief Trigger TX and RX PDMA function.
156 * @param[in] spi The pointer of the specified SPI module.
157 * @return None.
158 * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
159 * \hideinitializer
160 */
161 #define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
162
163 /**
164 * @brief Disable RX PDMA transfer.
165 * @param[in] spi The pointer of the specified SPI module.
166 * @return None.
167 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
168 * \hideinitializer
169 */
170 #define SPI_DISABLE_RX_PDMA(spi) ((spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk)
171
172 /**
173 * @brief Disable TX PDMA transfer.
174 * @param[in] spi The pointer of the specified SPI module.
175 * @return None.
176 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
177 * \hideinitializer
178 */
179 #define SPI_DISABLE_TX_PDMA(spi) ((spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk)
180
181 /**
182 * @brief Disable TX and RX PDMA transfer.
183 * @param[in] spi The pointer of the specified SPI module.
184 * @return None.
185 * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
186 * \hideinitializer
187 */
188 #define SPI_DISABLE_TX_RX_PDMA(spi) ((spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
189
190 /**
191 * @brief Get the count of available data in RX FIFO.
192 * @param[in] spi The pointer of the specified SPI module.
193 * @return The count of available data in RX FIFO.
194 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
195 * \hideinitializer
196 */
197 #define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
198
199 /**
200 * @brief Get the RX FIFO empty flag.
201 * @param[in] spi The pointer of the specified SPI module.
202 * @retval 0 RX FIFO is not empty.
203 * @retval 1 RX FIFO is empty.
204 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
205 * \hideinitializer
206 */
207 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
208
209 /**
210 * @brief Get the TX FIFO empty flag.
211 * @param[in] spi The pointer of the specified SPI module.
212 * @retval 0 TX FIFO is not empty.
213 * @retval 1 TX FIFO is empty.
214 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
215 * \hideinitializer
216 */
217 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
218
219 /**
220 * @brief Get the TX FIFO full flag.
221 * @param[in] spi The pointer of the specified SPI module.
222 * @retval 0 TX FIFO is not full.
223 * @retval 1 TX FIFO is full.
224 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
225 * \hideinitializer
226 */
227 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
228
229 /**
230 * @brief Get the datum read from RX register.
231 * @param[in] spi The pointer of the specified SPI module.
232 * @return Data in RX register.
233 * @details Read SPI_RX register to get the received datum.
234 * \hideinitializer
235 */
236 #define SPI_READ_RX(spi) ((spi)->RX)
237
238 /**
239 * @brief Write datum to TX register.
240 * @param[in] spi The pointer of the specified SPI module.
241 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
242 * @return None.
243 * @details Write u32TxData to SPI_TX register.
244 * \hideinitializer
245 */
246 #define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
247
248 /**
249 * @brief Set SPIx_SS pin to high state.
250 * @param[in] spi The pointer of the specified SPI module.
251 * @return None.
252 * @details Disable automatic slave selection function and set SPIx_SS pin to high state.
253 * \hideinitializer
254 */
255 #define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
256
257 /**
258 * @brief Set SPIx_SS pin to low state.
259 * @param[in] spi The pointer of the specified SPI module.
260 * @return None.
261 * @details Disable automatic slave selection function and set SPIx_SS pin to low state.
262 * \hideinitializer
263 */
264 #define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
265
266 /**
267 * @brief Enable Byte Reorder function.
268 * @param[in] spi The pointer of the specified SPI module.
269 * @return None.
270 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
271 * \hideinitializer
272 */
273 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
274
275 /**
276 * @brief Disable Byte Reorder function.
277 * @param[in] spi The pointer of the specified SPI module.
278 * @return None.
279 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
280 * \hideinitializer
281 */
282 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
283
284 /**
285 * @brief Set the length of suspend interval.
286 * @param[in] spi The pointer of the specified SPI module.
287 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
288 * @return None.
289 * @details Set the length of suspend interval according to u32SuspCycle.
290 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
291 * \hideinitializer
292 */
293 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
294
295 /**
296 * @brief Set the SPI transfer sequence with LSB first.
297 * @param[in] spi The pointer of the specified SPI module.
298 * @return None.
299 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
300 * \hideinitializer
301 */
302 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
303
304 /**
305 * @brief Set the SPI transfer sequence with MSB first.
306 * @param[in] spi The pointer of the specified SPI module.
307 * @return None.
308 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
309 * \hideinitializer
310 */
311 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
312
313 /**
314 * @brief Set the data width of a SPI transaction.
315 * @param[in] spi The pointer of the specified SPI module.
316 * @param[in] u32Width The bit width of one transaction.
317 * @return None.
318 * @details The data width can be 8 ~ 32 bits.
319 * \hideinitializer
320 */
321 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
322
323 /**
324 * @brief Get the SPI busy state.
325 * @param[in] spi The pointer of the specified SPI module.
326 * @retval 0 SPI controller is not busy.
327 * @retval 1 SPI controller is busy.
328 * @details This macro will return the busy state of SPI controller.
329 * \hideinitializer
330 */
331 #define SPI_IS_BUSY(spi) (((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos)
332
333 /**
334 * @brief Enable SPI controller.
335 * @param[in] spi The pointer of the specified SPI module.
336 * @return None.
337 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
338 * \hideinitializer
339 */
340 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
341
342 /**
343 * @brief Disable SPI controller.
344 * @param[in] spi The pointer of the specified SPI module.
345 * @return None.
346 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
347 * \hideinitializer
348 */
349 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
350
351 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
352 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
353 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
354 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
355
356 /**
357 * @brief Enable zero cross detection function.
358 * @param[in] i2s The pointer of the specified I2S module.
359 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
360 * - \ref SPII2S_RIGHT
361 * - \ref SPII2S_LEFT
362 * @return None
363 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
364 */
SPII2S_ENABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)365 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
366 {
367 if(u32ChMask == SPII2S_RIGHT)
368 {
369 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
370 }
371 else
372 {
373 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
374 }
375 }
376
377 /**
378 * @brief Disable zero cross detection function.
379 * @param[in] i2s The pointer of the specified I2S module.
380 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
381 * - \ref SPII2S_RIGHT
382 * - \ref SPII2S_LEFT
383 * @return None
384 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
385 */
SPII2S_DISABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)386 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
387 {
388 if(u32ChMask == SPII2S_RIGHT)
389 {
390 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
391 }
392 else
393 {
394 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
395 }
396 }
397
398 /**
399 * @brief Enable I2S TX DMA function.
400 * @param[in] i2s The pointer of the specified I2S module.
401 * @return None
402 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
403 * \hideinitializer
404 */
405 #define SPII2S_ENABLE_TXDMA(i2s) ((i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
406
407 /**
408 * @brief Disable I2S TX DMA function.
409 * @param[in] i2s The pointer of the specified I2S module.
410 * @return None
411 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
412 * \hideinitializer
413 */
414 #define SPII2S_DISABLE_TXDMA(i2s) ((i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk)
415
416 /**
417 * @brief Enable I2S RX DMA function.
418 * @param[in] i2s The pointer of the specified I2S module.
419 * @return None
420 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
421 * \hideinitializer
422 */
423 #define SPII2S_ENABLE_RXDMA(i2s) ((i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
424
425 /**
426 * @brief Disable I2S RX DMA function.
427 * @param[in] i2s The pointer of the specified I2S module.
428 * @return None
429 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
430 * \hideinitializer
431 */
432 #define SPII2S_DISABLE_RXDMA(i2s) ((i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk)
433
434 /**
435 * @brief Enable I2S TX function.
436 * @param[in] i2s The pointer of the specified I2S module.
437 * @return None
438 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
439 * \hideinitializer
440 */
441 #define SPII2S_ENABLE_TX(i2s) ((i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk)
442
443 /**
444 * @brief Disable I2S TX function.
445 * @param[in] i2s The pointer of the specified I2S module.
446 * @return None
447 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
448 * \hideinitializer
449 */
450 #define SPII2S_DISABLE_TX(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk)
451
452 /**
453 * @brief Enable I2S RX function.
454 * @param[in] i2s The pointer of the specified I2S module.
455 * @return None
456 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
457 * \hideinitializer
458 */
459 #define SPII2S_ENABLE_RX(i2s) ((i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk)
460
461 /**
462 * @brief Disable I2S RX function.
463 * @param[in] i2s The pointer of the specified I2S module.
464 * @return None
465 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
466 * \hideinitializer
467 */
468 #define SPII2S_DISABLE_RX(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk)
469
470 /**
471 * @brief Enable TX Mute function.
472 * @param[in] i2s The pointer of the specified I2S module.
473 * @return None
474 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
475 * \hideinitializer
476 */
477 #define SPII2S_ENABLE_TX_MUTE(i2s) ((i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk)
478
479 /**
480 * @brief Disable TX Mute function.
481 * @param[in] i2s The pointer of the specified I2S module.
482 * @return None
483 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
484 * \hideinitializer
485 */
486 #define SPII2S_DISABLE_TX_MUTE(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk)
487
488 /**
489 * @brief Clear TX FIFO.
490 * @param[in] i2s The pointer of the specified I2S module.
491 * @return None
492 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
493 * \hideinitializer
494 */
495 #define SPII2S_CLR_TX_FIFO(i2s) ((i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk)
496
497 /**
498 * @brief Clear RX FIFO.
499 * @param[in] i2s The pointer of the specified I2S module.
500 * @return None
501 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
502 * \hideinitializer
503 */
504 #define SPII2S_CLR_RX_FIFO(i2s) ((i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk)
505
506 /**
507 * @brief This function sets the recording source channel when mono mode is used.
508 * @param[in] i2s The pointer of the specified I2S module.
509 * @param[in] u32Ch left or right channel. Valid values are:
510 * - \ref SPII2S_MONO_LEFT
511 * - \ref SPII2S_MONO_RIGHT
512 * @return None
513 * @details This function selects the recording source channel of monaural mode.
514 * \hideinitializer
515 */
SPII2S_SET_MONO_RX_CHANNEL(SPI_T * i2s,uint32_t u32Ch)516 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
517 {
518 u32Ch == SPII2S_MONO_LEFT ?
519 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
520 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
521 }
522
523 /**
524 * @brief Write data to I2S TX FIFO.
525 * @param[in] i2s The pointer of the specified I2S module.
526 * @param[in] u32Data The value written to TX FIFO.
527 * @return None
528 * @details This macro will write a value to TX FIFO.
529 * \hideinitializer
530 */
531 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ((i2s)->TX = (u32Data))
532
533 /**
534 * @brief Read RX FIFO.
535 * @param[in] i2s The pointer of the specified I2S module.
536 * @return The value read from RX FIFO.
537 * @details This function will return a value read from RX FIFO.
538 * \hideinitializer
539 */
540 #define SPII2S_READ_RX_FIFO(i2s) ((i2s)->RX)
541
542 /**
543 * @brief Get the interrupt flag.
544 * @param[in] i2s The pointer of the specified I2S module.
545 * @param[in] u32Mask The mask value for all interrupt flags.
546 * @return The interrupt flags specified by the u32mask parameter.
547 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
548 * \hideinitializer
549 */
550 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ((i2s)->I2SSTS & (u32Mask))
551
552 /**
553 * @brief Clear the interrupt flag.
554 * @param[in] i2s The pointer of the specified I2S module.
555 * @param[in] u32Mask The mask value for all interrupt flags.
556 * @return None
557 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
558 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
559 * \hideinitializer
560 */
561 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ((i2s)->I2SSTS = (u32Mask))
562
563 /**
564 * @brief Get transmit FIFO level
565 * @param[in] i2s The pointer of the specified I2S module.
566 * @return TX FIFO level
567 * @details This macro will return the number of available words in TX FIFO.
568 * \hideinitializer
569 */
570 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) (((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos)
571
572 /**
573 * @brief Get receive FIFO level
574 * @param[in] i2s The pointer of the specified I2S module.
575 * @return RX FIFO level
576 * @details This macro will return the number of available words in RX FIFO.
577 * \hideinitializer
578 */
579 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) (((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos)
580
581 /* Function prototype declaration */
582 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
583 void SPI_Close(SPI_T *spi);
584 void SPI_ClearRxFIFO(SPI_T *spi);
585 void SPI_ClearTxFIFO(SPI_T *spi);
586 void SPI_DisableAutoSS(SPI_T *spi);
587 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
588 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
589 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
590 uint32_t SPI_GetBusClock(SPI_T *spi);
591 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
592 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
593 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
594 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
595 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
596
597 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
598 void SPII2S_Close(SPI_T *i2s);
599 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
600 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
601 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
602 void SPII2S_DisableMCLK(SPI_T *i2s);
603 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
604
605 /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
606
607 /*@}*/ /* end of group SPI_Driver */
608
609 /*@}*/ /* end of group Standard_Driver */
610
611 #ifdef __cplusplus
612 }
613 #endif
614
615 #endif
616
617 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
618
