1 /**************************************************************************//**
2 * @file spi.h
3 * @version V3.00
4 * @brief M460 series SPI driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __SPI_H__
10 #define __SPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup SPI_Driver SPI Driver
23 @{
24 */
25
26 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
27 @{
28 */
29
30 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
31 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
32 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
33 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
34
35 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
36 #define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
37
38 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
39 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
40 #define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
41
42 /* SPI Interrupt Mask */
43 #define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
44 #define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
45 #define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
46 #define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
47 #define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
48 #define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
49 #define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
50 #define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
51 #define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
52 #define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
53
54 /* SPI Status Mask */
55 #define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
56 #define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
57 #define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
58 #define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
59 #define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
60 #define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
61 #define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */
62 #define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */
63
64 /* SPI Status2 Mask */
65 #define SPI_SLVBENUM_MASK (0x01U) /*!< Effective bit number of uncompleted RX data status mask \hideinitializer */
66
67
68 /* I2S Data Width */
69 #define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
70 #define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
71 #define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
72 #define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
73
74 /* I2S Audio Format */
75 #define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
76 #define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
77
78 /* I2S Data Format */
79 #define SPII2S_FORMAT_I2S (0U<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
80 #define SPII2S_FORMAT_MSB (1U<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
81 #define SPII2S_FORMAT_PCMA (2U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
82 #define SPII2S_FORMAT_PCMB (3U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
83
84 /* I2S Operation mode */
85 #define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
86 #define SPII2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */
87
88 /* I2S Record Channel */
89 #define SPII2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
90 #define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
91
92 /* I2S Channel */
93 #define SPII2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
94 #define SPII2S_LEFT (1U) /*!< Select left channel \hideinitializer */
95
96 /* I2S Interrupt Mask */
97 #define SPII2S_FIFO_TXTH_INT_MASK (0x01U) /*!< TX FIFO threshold interrupt mask \hideinitializer */
98 #define SPII2S_FIFO_RXTH_INT_MASK (0x02U) /*!< RX FIFO threshold interrupt mask \hideinitializer */
99 #define SPII2S_FIFO_RXOV_INT_MASK (0x04U) /*!< RX FIFO overrun interrupt mask \hideinitializer */
100 #define SPII2S_FIFO_RXTO_INT_MASK (0x08U) /*!< RX FIFO time-out interrupt mask \hideinitializer */
101 #define SPII2S_TXUF_INT_MASK (0x10U) /*!< TX FIFO underflow interrupt mask \hideinitializer */
102 #define SPII2S_RIGHT_ZC_INT_MASK (0x20U) /*!< Right channel zero cross interrupt mask \hideinitializer */
103 #define SPII2S_LEFT_ZC_INT_MASK (0x40U) /*!< Left channel zero cross interrupt mask \hideinitializer */
104 #define SPII2S_SLAVE_ERR_INT_MASK (0x80U) /*!< Bit clock loss interrupt mask \hideinitializer */
105
106 /*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
107
108 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
109 @{
110 */
111
112 /**
113 * @brief Clear the unit transfer interrupt flag.
114 * @param[in] spi The pointer of the specified SPI module.
115 * @return None.
116 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
117 * \hideinitializer
118 */
119 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
120
121 /**
122 * @brief Disable Slave 3-wire mode.
123 * @param[in] spi The pointer of the specified SPI module.
124 * @return None.
125 * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
126 * \hideinitializer
127 */
128 #define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk )
129
130 /**
131 * @brief Enable Slave 3-wire mode.
132 * @param[in] spi The pointer of the specified SPI module.
133 * @return None.
134 * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
135 * \hideinitializer
136 */
137 #define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk )
138
139 /**
140 * @brief Trigger RX PDMA function.
141 * @param[in] spi The pointer of the specified SPI module.
142 * @return None.
143 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
144 * \hideinitializer
145 */
146 #define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
147
148 /**
149 * @brief Trigger TX PDMA function.
150 * @param[in] spi The pointer of the specified SPI module.
151 * @return None.
152 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
153 * \hideinitializer
154 */
155 #define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
156
157 /**
158 * @brief Trigger TX and RX PDMA function.
159 * @param[in] spi The pointer of the specified SPI module.
160 * @return None.
161 * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
162 * \hideinitializer
163 */
164 #define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
165
166 /**
167 * @brief Disable RX PDMA transfer.
168 * @param[in] spi The pointer of the specified SPI module.
169 * @return None.
170 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
171 * \hideinitializer
172 */
173 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
174
175 /**
176 * @brief Disable TX PDMA transfer.
177 * @param[in] spi The pointer of the specified SPI module.
178 * @return None.
179 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
180 * \hideinitializer
181 */
182 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
183
184 /**
185 * @brief Disable TX and RX PDMA transfer.
186 * @param[in] spi The pointer of the specified SPI module.
187 * @return None.
188 * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
189 * \hideinitializer
190 */
191 #define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
192
193 /**
194 * @brief Get the count of available data in RX FIFO.
195 * @param[in] spi The pointer of the specified SPI module.
196 * @return The count of available data in RX FIFO.
197 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
198 * \hideinitializer
199 */
200 #define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos )
201
202 /**
203 * @brief Get the RX FIFO empty flag.
204 * @param[in] spi The pointer of the specified SPI module.
205 * @retval 0 RX FIFO is not empty.
206 * @retval 1 RX FIFO is empty.
207 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
208 * \hideinitializer
209 */
210 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos )
211
212 /**
213 * @brief Get the TX FIFO empty flag.
214 * @param[in] spi The pointer of the specified SPI module.
215 * @retval 0 TX FIFO is not empty.
216 * @retval 1 TX FIFO is empty.
217 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
218 * \hideinitializer
219 */
220 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos )
221
222 /**
223 * @brief Get the TX FIFO full flag.
224 * @param[in] spi The pointer of the specified SPI module.
225 * @retval 0 TX FIFO is not full.
226 * @retval 1 TX FIFO is full.
227 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
228 * \hideinitializer
229 */
230 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos )
231
232 /**
233 * @brief Get the datum read from RX register.
234 * @param[in] spi The pointer of the specified SPI module.
235 * @return Data in RX register.
236 * @details Read SPI_RX register to get the received datum.
237 * \hideinitializer
238 */
239 #define SPI_READ_RX(spi) ( (spi)->RX )
240
241 /**
242 * @brief Write datum to TX register.
243 * @param[in] spi The pointer of the specified SPI module.
244 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
245 * @return None.
246 * @details Write u32TxData to SPI_TX register.
247 * \hideinitializer
248 */
249 #define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) )
250
251 /**
252 * @brief Set SPIx_SS pin to high state.
253 * @param[in] spi The pointer of the specified SPI module.
254 * @return None.
255 * @details Disable automatic slave selection function and set SPIx_SS pin to high state.
256 * \hideinitializer
257 */
258 #define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) )
259
260 /**
261 * @brief Set SPIx_SS pin to low state.
262 * @param[in] spi The pointer of the specified SPI module.
263 * @return None.
264 * @details Disable automatic slave selection function and set SPIx_SS pin to low state.
265 * \hideinitializer
266 */
267 #define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk )
268
269 /**
270 * @brief Enable Byte Reorder function.
271 * @param[in] spi The pointer of the specified SPI module.
272 * @return None.
273 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
274 * \hideinitializer
275 */
276 #define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
277
278 /**
279 * @brief Disable Byte Reorder function.
280 * @param[in] spi The pointer of the specified SPI module.
281 * @return None.
282 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
283 * \hideinitializer
284 */
285 #define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
286
287 /**
288 * @brief Set the length of suspend interval.
289 * @param[in] spi The pointer of the specified SPI module.
290 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
291 * @return None.
292 * @details Set the length of suspend interval according to u32SuspCycle.
293 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
294 * \hideinitializer
295 */
296 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) )
297
298 /**
299 * @brief Set the SPI transfer sequence with LSB first.
300 * @param[in] spi The pointer of the specified SPI module.
301 * @return None.
302 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
303 * \hideinitializer
304 */
305 #define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
306
307 /**
308 * @brief Set the SPI transfer sequence with MSB first.
309 * @param[in] spi The pointer of the specified SPI module.
310 * @return None.
311 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
312 * \hideinitializer
313 */
314 #define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
315
316 /**
317 * @brief Set the data width of a SPI transaction.
318 * @param[in] spi The pointer of the specified SPI module.
319 * @param[in] u32Width The bit width of one transaction.
320 * @return None.
321 * @details The data width can be 4 ~ 32 bits.
322 * \hideinitializer
323 */
324 #define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) )
325
326 /**
327 * @brief Get the SPI busy state.
328 * @param[in] spi The pointer of the specified SPI module.
329 * @retval 0 SPI controller is not busy.
330 * @retval 1 SPI controller is busy.
331 * @details This macro will return the busy state of SPI controller.
332 * \hideinitializer
333 */
334 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos )
335
336 /**
337 * @brief Enable SPI controller.
338 * @param[in] spi The pointer of the specified SPI module.
339 * @return None.
340 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
341 * \hideinitializer
342 */
343 #define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
344
345 /**
346 * @brief Disable SPI controller.
347 * @param[in] spi The pointer of the specified SPI module.
348 * @return None.
349 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
350 * \hideinitializer
351 */
352 #define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
353
354 /**
355 * @brief Enable zero cross detection function.
356 * @param[in] i2s The pointer of the specified I2S module.
357 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
358 * - \ref SPII2S_RIGHT
359 * - \ref SPII2S_LEFT
360 * @return None
361 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
362 */
SPII2S_ENABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)363 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
364 {
365 if(u32ChMask == SPII2S_RIGHT)
366 {
367 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
368 }
369 else
370 {
371 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
372 }
373 }
374
375 /**
376 * @brief Disable zero cross detection function.
377 * @param[in] i2s The pointer of the specified I2S module.
378 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
379 * - \ref SPII2S_RIGHT
380 * - \ref SPII2S_LEFT
381 * @return None
382 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
383 */
SPII2S_DISABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)384 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
385 {
386 if(u32ChMask == SPII2S_RIGHT)
387 {
388 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
389 }
390 else
391 {
392 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
393 }
394 }
395
396 /**
397 * @brief Enable I2S TX DMA function.
398 * @param[in] i2s The pointer of the specified I2S module.
399 * @return None
400 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
401 * \hideinitializer
402 */
403 #define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
404
405 /**
406 * @brief Disable I2S TX DMA function.
407 * @param[in] i2s The pointer of the specified I2S module.
408 * @return None
409 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
410 * \hideinitializer
411 */
412 #define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
413
414 /**
415 * @brief Enable I2S RX DMA function.
416 * @param[in] i2s The pointer of the specified I2S module.
417 * @return None
418 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
419 * \hideinitializer
420 */
421 #define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
422
423 /**
424 * @brief Disable I2S RX DMA function.
425 * @param[in] i2s The pointer of the specified I2S module.
426 * @return None
427 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
428 * \hideinitializer
429 */
430 #define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
431
432 /**
433 * @brief Enable I2S TX function.
434 * @param[in] i2s The pointer of the specified I2S module.
435 * @return None
436 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
437 * \hideinitializer
438 */
439 #define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
440
441 /**
442 * @brief Disable I2S TX function.
443 * @param[in] i2s The pointer of the specified I2S module.
444 * @return None
445 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
446 * \hideinitializer
447 */
448 #define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
449
450 /**
451 * @brief Enable I2S RX function.
452 * @param[in] i2s The pointer of the specified I2S module.
453 * @return None
454 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
455 * \hideinitializer
456 */
457 #define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
458
459 /**
460 * @brief Disable I2S RX function.
461 * @param[in] i2s The pointer of the specified I2S module.
462 * @return None
463 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
464 * \hideinitializer
465 */
466 #define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
467
468 /**
469 * @brief Enable TX Mute function.
470 * @param[in] i2s The pointer of the specified I2S module.
471 * @return None
472 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
473 * \hideinitializer
474 */
475 #define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
476
477 /**
478 * @brief Disable TX Mute function.
479 * @param[in] i2s The pointer of the specified I2S module.
480 * @return None
481 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
482 * \hideinitializer
483 */
484 #define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
485
486 /**
487 * @brief Clear TX FIFO.
488 * @param[in] i2s The pointer of the specified I2S module.
489 * @return None
490 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
491 * \hideinitializer
492 */
493 #define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
494
495 /**
496 * @brief Clear RX FIFO.
497 * @param[in] i2s The pointer of the specified I2S module.
498 * @return None
499 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
500 * \hideinitializer
501 */
502 #define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
503
504 /**
505 * @brief This function sets the recording source channel when mono mode is used.
506 * @param[in] i2s The pointer of the specified I2S module.
507 * @param[in] u32Ch left or right channel. Valid values are:
508 * - \ref SPII2S_MONO_LEFT
509 * - \ref SPII2S_MONO_RIGHT
510 * @return None
511 * @details This function selects the recording source channel of monaural mode.
512 * \hideinitializer
513 */
SPII2S_SET_MONO_RX_CHANNEL(SPI_T * i2s,uint32_t u32Ch)514 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
515 {
516 u32Ch == SPII2S_MONO_LEFT ?
517 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
518 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
519 }
520
521 /**
522 * @brief Write data to I2S TX FIFO.
523 * @param[in] i2s The pointer of the specified I2S module.
524 * @param[in] u32Data The value written to TX FIFO.
525 * @return None
526 * @details This macro will write a value to TX FIFO.
527 * \hideinitializer
528 */
529 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
530
531 /**
532 * @brief Read RX FIFO.
533 * @param[in] i2s The pointer of the specified I2S module.
534 * @return The value read from RX FIFO.
535 * @details This function will return a value read from RX FIFO.
536 * \hideinitializer
537 */
538 #define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
539
540 /**
541 * @brief Get the interrupt flag.
542 * @param[in] i2s The pointer of the specified I2S module.
543 * @param[in] u32Mask The mask value for all interrupt flags.
544 * @return The interrupt flags specified by the u32mask parameter.
545 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
546 * \hideinitializer
547 */
548 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
549
550 /**
551 * @brief Clear the interrupt flag.
552 * @param[in] i2s The pointer of the specified I2S module.
553 * @param[in] u32Mask The mask value for all interrupt flags.
554 * @return None
555 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
556 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
557 * \hideinitializer
558 */
559 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
560
561 /**
562 * @brief Get transmit FIFO level
563 * @param[in] i2s The pointer of the specified I2S module.
564 * @return TX FIFO level
565 * @details This macro will return the number of available words in TX FIFO.
566 * \hideinitializer
567 */
568 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
569
570 /**
571 * @brief Get receive FIFO level
572 * @param[in] i2s The pointer of the specified I2S module.
573 * @return RX FIFO level
574 * @details This macro will return the number of available words in RX FIFO.
575 * \hideinitializer
576 */
577 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
578
579
580
581 /* Function prototype declaration */
582 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
583 void SPI_Close(SPI_T *spi);
584 void SPI_ClearRxFIFO(SPI_T *spi);
585 void SPI_ClearTxFIFO(SPI_T *spi);
586 void SPI_DisableAutoSS(SPI_T *spi);
587 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
588 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
589 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
590 uint32_t SPI_GetBusClock(SPI_T *spi);
591 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
592 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
593 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
594 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
595 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
596 uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask);
597
598 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
599 void SPII2S_Close(SPI_T *i2s);
600 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
601 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
602 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
603 void SPII2S_DisableMCLK(SPI_T *i2s);
604 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
605
606
607 /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
608
609 /*@}*/ /* end of group SPI_Driver */
610
611 /*@}*/ /* end of group Standard_Driver */
612
613 #ifdef __cplusplus
614 }
615 #endif
616
617 #endif /* __SPI_H__ */
618
