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Searched refs:cfg (Results 1 – 25 of 26) sorted by relevance

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/hal_microchip-latest/mec5/drivers/
Dmec_espi.c175 static uint8_t fc_sharing_hw(uint32_t cfg) in fc_sharing_hw() argument
179 if (cfg & MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS)) { in fc_sharing_hw()
180 if (cfg & MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_CAF_POS)) { in fc_sharing_hw()
194 uint32_t cfg = 0; in fc_sharing_get() local
198 cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS); in fc_sharing_get()
200 cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_CAF_POS); in fc_sharing_get()
202 cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS); in fc_sharing_get()
206 return cfg; in fc_sharing_get()
324 int mec_hal_espi_init(struct mec_espi_config *cfg) in mec_hal_espi_init() argument
326 if (!cfg) { in mec_hal_espi_init()
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Dmec_dmac.c608 int mec_hal_dma_chan_cfg(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg) in mec_hal_dma_chan_cfg() argument
614 if (!cfg || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_cfg()
620 if ((cfg->unitsz == 4u) || (cfg->unitsz == 2u)) { in mec_hal_dma_chan_cfg()
621 usz = cfg->unitsz; in mec_hal_dma_chan_cfg()
627 if (cfg->dir == MEC_DMAC_DIR_MEM_TO_DEV) { in mec_hal_dma_chan_cfg()
629 regs->MSTART = cfg->src_addr; in mec_hal_dma_chan_cfg()
630 regs->MEND = cfg->src_addr + cfg->nbytes; in mec_hal_dma_chan_cfg()
631 regs->DSTART = cfg->dst_addr; in mec_hal_dma_chan_cfg()
632 if (cfg->flags & MEC_DMA_CFG_FLAG_INCR_SRC_ADDR) { in mec_hal_dma_chan_cfg()
635 if (cfg->flags & MEC_DMA_CFG_FLAG_INCR_DST_ADDR) { in mec_hal_dma_chan_cfg()
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Dmec_wktimer.c79 int mec_hal_wktimer_init(struct mec_wktmr_regs *regs, struct mec_wktmr_config *cfg) in mec_hal_wktimer_init() argument
89 if (!cfg) { in mec_hal_wktimer_init()
96 if (cfg->cfg_flags & MEC_BIT(MEC_WKTMR_CFG_SYS_PWR_PRES_EN_POS)) { in mec_hal_wktimer_init()
100 if (cfg->cfg_flags & MEC_BIT(MEC_WKTMR_CFG_SUBWK_RELOAD_POS)) { in mec_hal_wktimer_init()
104 if (cfg->cfg_flags & MEC_BIT(MEC_WKTMR_CFG_VCI_PWR_UP_EV_EN_POS)) { in mec_hal_wktimer_init()
108 if (cfg->cfg_flags & MEC_BIT(MEC_WKTMR_CFG_ENABLE_POS)) { in mec_hal_wktimer_init()
112 regs->COUNT = cfg->one_sec_count; in mec_hal_wktimer_init()
113 regs->COMP = cfg->one_sec_alarm_count; in mec_hal_wktimer_init()
115 | (cfg->sub_week_reload & MEC_WKTMR_SWAC_SUB_LOAD_Msk); in mec_hal_wktimer_init()
Dmec_peci.c59 int mec_hal_peci_init(struct mec_peci_regs *regs, struct mec_peci_config *cfg, uint32_t flags) in mec_hal_peci_init() argument
67 if (!cfg) { in mec_hal_peci_init()
82 regs->BAUD_CTRL = cfg->clock_div; in mec_hal_peci_init()
86 regs->OPTBTM_LO = (uint8_t)(cfg->optimal_bit_time); in mec_hal_peci_init()
87 regs->OPTBTM_HI = (uint8_t)(cfg->optimal_bit_time >> 8); in mec_hal_peci_init()
91 regs->REQ_TIMER_LSB = (uint8_t)(cfg->request_timer); in mec_hal_peci_init()
92 regs->REQ_TIMER_MSB = (uint8_t)(cfg->request_timer >> 8); in mec_hal_peci_init()
102 peci_intr_en(regs, cfg->intr_enables); in mec_hal_peci_init()
Dmec_adc.c39 int mec_hal_adc_init(struct mec_adc_regs *regs, struct mec_adc_config *cfg) in mec_hal_adc_init() argument
55 if (cfg) { in mec_hal_adc_init()
56 flags = cfg->flags; in mec_hal_adc_init()
75 temp = (((uint32_t)cfg->sample_clk_hi_time << MEC_ADC_CONFIG_CHTM_Pos) in mec_hal_adc_init()
77 temp |= (((uint32_t)cfg->sample_clk_lo_time << MEC_ADC_CONFIG_CLTM_Pos) in mec_hal_adc_init()
86 | (((uint32_t)cfg->warm_up_delay << MEC_ADC_SAR_CTRL_WARMUPDLY_Pos) in mec_hal_adc_init()
93 temp |= (((uint32_t)cfg->rpt_start_delay << MEC_ADC_DELAY_RSTART_DLY_Pos) in mec_hal_adc_init()
95 temp |= (((uint32_t)cfg->rpt_cycle_delay << MEC_ADC_DELAY_RPT_DLY_Pos) in mec_hal_adc_init()
101 regs->SAR_CFG = cfg->sar_config; in mec_hal_adc_init()
Dmec_pwm.c151 uint32_t perc, pulc, ps1, cnt_on, cnt_off, cfg, fin, fpwm, flags; in prog_pwm_fd() local
185 cfg = regs->CONFIG & (uint32_t)~(MEC_PWM_CONFIG_CLKDIV_Msk | MEC_PWM_CONFIG_CLK_SRC_SLOW_Msk); in prog_pwm_fd()
186 cfg |= ((ps1 << MEC_PWM_CONFIG_CLKDIV_Pos) & MEC_PWM_CONFIG_CLKDIV_Msk); in prog_pwm_fd()
188 cfg |= MEC_BIT(MEC_PWM_CONFIG_CLK_SRC_SLOW_Pos); in prog_pwm_fd()
192 regs->CONFIG = cfg; in prog_pwm_fd()
Dmec_espi_core.h267 int mec_hal_espi_init(struct mec_espi_config *cfg);
270 enum mec_espi_global_cap cap, uint32_t cfg);
273 enum mec_espi_global_cap cap, uint32_t *cfg);
275 int mec_hal_espi_cap_set(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id, uint32_t cfg);
Dmec_espi_vw.c450 struct mec_espi_vw_config *cfg, uint32_t flags) in mec_hal_espi_vwg_ct_config() argument
465 r[0] |= (((uint32_t)cfg->host_idx << MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Pos) in mec_hal_espi_vwg_ct_config()
471 r[0] |= (((uint32_t)cfg->reset_src << MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_Pos) in mec_hal_espi_vwg_ct_config()
477 if (cfg->reset_val_bm & MEC_BIT(i)) { in mec_hal_espi_vwg_ct_config()
484 uint8_t j = cfg->src_irq_sel[i]; in mec_hal_espi_vwg_ct_config()
491 if (cfg->src_val_bm & MEC_BIT(i)) { in mec_hal_espi_vwg_ct_config()
739 struct mec_espi_vw_config *cfg, uint32_t flags) in mec_hal_espi_vwg_tc_config() argument
749 r[0] |= (((uint32_t)cfg->host_idx << MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX_Pos) in mec_hal_espi_vwg_tc_config()
755 r[0] |= (((uint32_t)cfg->reset_src << MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_Pos) in mec_hal_espi_vwg_tc_config()
761 if (cfg->reset_val_bm & MEC_BIT(i)) { in mec_hal_espi_vwg_tc_config()
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Dmec_i2c.c539 uint32_t cfg = 0; in mec_hal_i2c_smb_intr_ctrl() local
559 cfg |= MEC_BIT(MEC_I2C_SMB_CONFIG_ENI_IDLE_Pos); in mec_hal_i2c_smb_intr_ctrl()
562 cfg |= MEC_BIT(MEC_I2C_SMB_CONFIG_ENMI_Pos); in mec_hal_i2c_smb_intr_ctrl()
565 cfg |= MEC_BIT(MEC_I2C_SMB_CONFIG_ENSI_Pos); in mec_hal_i2c_smb_intr_ctrl()
568 cfg |= MEC_BIT(MEC_I2C_SMB_CONFIG_ENI_AAT_Pos); in mec_hal_i2c_smb_intr_ctrl()
572 regs->CONFIG |= cfg; in mec_hal_i2c_smb_intr_ctrl()
574 regs->CONFIG &= (uint32_t)~cfg; in mec_hal_i2c_smb_intr_ctrl()
654 uint32_t cfg = base->CONFIG & MEC_BIT(MEC_I2C_SMB_CONFIG_ENI_IDLE_Pos); in mec_hal_i2c_smb_is_idle_intr() local
657 if (cfg && compl) { in mec_hal_i2c_smb_is_idle_intr()
677 uint32_t cfg = base->CONFIG & MEC_BIT(MEC_I2C_SMB_CONFIG_ENI_AAT_Pos); in mec_hal_i2c_smb_is_aat_ien() local
[all …]
Dmec_dmac_api.h156 int mec_hal_dma_chan_cfg(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg);
158 int mec_hal_dma_chan_cfg_get(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg);
Dmec_wktimer_api.h78 int mec_hal_wktimer_init(struct mec_wktmr_regs *regs, struct mec_wktmr_config *cfg);
Dmec_adc_api.h86 int mec_hal_adc_init(struct mec_adc_regs *regs, struct mec_adc_config *cfg);
Dmec_pcr.c595 struct mec_pcr_clkmon_cfg *cfg, in mec_hal_pcr_clk32k_init() argument
602 if (!cfg) { in mec_hal_pcr_clk32k_init()
648 ret = check_crystal(cfg); in mec_hal_pcr_clk32k_init()
Dmec_peci_api.h75 int mec_hal_peci_init(struct mec_peci_regs *regs, struct mec_peci_config *cfg, uint32_t flags);
Dmec_gpio.c383 int mec_hal_gpio_set_config(uint32_t pin, uint32_t cfg) in mec_hal_gpio_set_config() argument
391 MEC_MMCR16_WR(&MEC_GPIO->CTRL[pin], cfg & 0xffffu); in mec_hal_gpio_set_config()
396 int mec_hal_gpio_set_config_mask(uint32_t pin, uint32_t cfg, uint32_t mask) in mec_hal_gpio_set_config_mask() argument
406 pin_cfg |= (uint16_t)(cfg & mask); in mec_hal_gpio_set_config_mask()
Dmec_pcr_api.h233 struct mec_pcr_clkmon_cfg *cfg,
Dmec_espi_vw.h222 struct mec_espi_vw_config *cfg, uint32_t flags);
/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dmss_ethernet_mac.c147 static void config_mac_hw(mss_mac_instance_t *this_mac, const mss_mac_cfg_t * cfg);
156 static void instances_init(mss_mac_instance_t *this_mac, mss_mac_cfg_t *cfg);
173 mss_mac_cfg_t *cfg in MSS_MAC_init() argument
177 ASSERT(cfg != NULL_POINTER); in MSS_MAC_init()
181 instances_init(this_mac, cfg); in MSS_MAC_init()
183 if((cfg != NULL_POINTER) && (this_mac == &g_mac0)) in MSS_MAC_init()
187 instances_init(this_mac, cfg); in MSS_MAC_init()
257 this_mac->mac_base->USER_IO = cfg->tsu_clock_select & 1U; in MSS_MAC_init()
260 …if((cfg != NULL_POINTER) && ((this_mac == &g_mac0) || (this_mac == &g_mac1) || (this_mac == &g_ema… in MSS_MAC_init()
263 this_mac->phy_addr = cfg->phy_addr; in MSS_MAC_init()
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Dmss_ethernet_mac.h587 mss_mac_cfg_t * cfg
646 mss_mac_cfg_t * cfg
708 const mss_mac_cfg_t * cfg
Dvsc8575_phy.c264 g_phy_conf_1g.master.cfg = TRUE; /* 1=Enabled */ in MSS_MAC_VSC8575_phy_init()
472 phy_config.conf_1g.master.cfg = 0U; /* Manual Master/Slave config to Force Master cfg */ in MSS_MAC_VSC8575_phy_init()
/hal_microchip-latest/mpfs/drivers/mss/pf_pcie/
Dpf_pcie.c845 pf_pcie_master_atr_cfg_t * cfg, in PF_PCIE_master_atr_table_init() argument
863 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
878 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
901 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
902 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
904 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
920 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
921 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
923 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
937 phy_reg = (uint32_t)(cfg->src_addr & ATR_ADDR_MASK); in PF_PCIE_master_atr_table_init()
[all …]
Dpf_pcie.h630 pf_pcie_master_atr_cfg_t * cfg,
694 pf_pcie_slave_atr_cfg_t * cfg,
/hal_microchip-latest/mpfs/drivers/mss/mss_mmc/
Dmss_mmc.c198 static mss_mmc_status_t mmccard_oper_config(const mss_mmc_cfg_t * cfg);
199 static mss_mmc_status_t sdcard_oper_config(const mss_mmc_cfg_t * cfg);
200 static mss_mmc_status_t sdio_oper_config(const mss_mmc_cfg_t * cfg);
211 const mss_mmc_cfg_t * cfg
213 static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg);
222 static mss_mmc_status_t set_sd_host_device_bus_mode(const mss_mmc_cfg_t * cfg);
248 static mss_mmc_status_t change_sdio_device_bus_mode(const mss_mmc_cfg_t * cfg);
295 const mss_mmc_cfg_t * cfg in MSS_MMC_init() argument
336 if (MSS_MMC_CARD_TYPE_MMC == cfg->card_type) in MSS_MMC_init()
382 if (MSS_MMC_CARD_TYPE_SD == cfg->card_type) in MSS_MMC_init()
[all …]
Dmss_mmc.h418 const mss_mmc_cfg_t * cfg
/hal_microchip-latest/mpfs/drivers/mss/mss_can/
Dmss_can.c138 uint32_t cfg in MSS_CAN_set_config_reg() argument
154 this_can->hw_reg->Config.L = cfg; in MSS_CAN_set_config_reg()

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