1 /*******************************************************************************
2  * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * PolarFire SoC MSS eMMC SD bare metal driver implementation.
7  *
8  */
9 #include "mpfs_hal/mss_hal.h"
10 #include "mss_mmc_if.h"
11 #include "mss_mmc_regs.h"
12 #include "mss_mmc_types.h"
13 #include "mss_mmc.h"
14 #ifdef MSS_MMC_INTERNAL_APIS
15 #include "mss_mmc_internal_api.h"
16 #endif
17 
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21 
22 /***************************************************************************//**
23  * Macros
24  */
25 #define WORD_SIZE                       4u
26 #define BYTE_MASK                       0xFFu
27 #define BLK_SIZE                        512u
28 #define BLOCK_COUNT_ENABLE_SHIFT        16u
29 #define BUFF_EMPTY                      0u
30 #define RCA_VALUE                       0x0001u
31 #define STUFF_BITS                      0x0u
32 #define BUSY_BIT_MASK                   0x80000000u
33 #define SECT_SIZE_CSD_MASK              0x03C000u
34 #define SECT_SIZE_CSD_SHIFT             14u
35 #define SECTOR_ACCESS_MODE_MASK         0x60000000u
36 #define SECTOR_SHIFT                    29u
37 #define RESET_ARG                       0x00000000u
38 #define MMC_DW_CSD                      0x03B70000u
39 #define MMC_LEGACY_MODE                 0x03B90000u
40 #define MMC_HS_MODE                     0x03B90100u
41 #define MMC_HS200_MODE                  0x03B90200u
42 #define MMC_HS400_MODE                  0x03B90300u
43 #define MMC_HS_MODE_DEFAULT             0x03B90000u
44 #define MMC_HPI_ENABLE                  0x03A10100u
45 
46 #define MMC_CQ_ENABLE                   0x030F0100u
47 #define CQ_IDLE_TIME                    0x1000u
48 
49 #define MMC_DEVICE_LOW_POWER            0x80u
50 #define MMC_DEVICE_LOW_VOLT_SET         0x40000080u
51 #define MMC_DEVICE_3_3V_VOLT_SET        0x40300000u
52 
53 #define MMC_CLEAR                       0x0u
54 #define MMC_SET                         0x1u
55 #define MMC_STATUS_CLEAR                0xFFFFFFFFu
56 #define MMC_64BIT_UPPER_ADDR_SHIFT      32u
57 #define MMC_SRS03_COMMAND_SHIFT         24u
58 #define DELAY_COUNT                     0xFFFFu
59 #define DATA_TIMEOUT_VALUE              500000u
60 #define HRS0_SOFTWARE_RESET             0x00000001u
61 #define MMC_SOFTWARE_RESET_SHIFT        0x3u
62 #define DEBOUNCING_TIME                 0x300000u
63 #define MMC_RESET_DATA_CMD_LINE         0x06000000u
64 /* SDMA boundary is 512k */
65 #define SIZE_32MB                       0x02000000u
66 #define SIZE_64KB                       0x00010000u
67 #define SIZE_1GB                        0x40000000u
68 
69 #define EXT_CSD_SECTOR_COUNT_OFFSET     212u
70 #define EXT_CSD_CARD_TYPE_OFFSET        196u
71 #define EXT_CSD_REVISION_OFFSET         192u
72 #define EXT_CSD_HS_TIMING_OFFSET        185u
73 #define EXT_CSD_ES_SUPPORT_OFFSET       184u
74 #define EXT_CSD_CQ_SUPPORT_OFFSET       308u
75 /* CMD Queuing Depth */
76 #define EXT_CSD_CQ_DEPTH_OFFSET         307u
77 #define EXT_CSD_CQ_MODE_EN_OFFSET       15u
78 
79 #define READ_SEND_SCR                   0xFFFFFFFEu
80 #define SCR_REG_DATA_SIZE               8u
81 
82 #define IF_COND_27V_33V                 (1u << 8u)
83 
84 #define RCA_SHIFT_BIT                   16u
85 #define SIZE_4KB                        4096u
86 #define COMMANDS_TIMEOUT                3000u
87 /* HS200/400 1.8v support */
88 #define DEVICE_SUPPORT_HS400            0x40u
89 #define DEVICE_SUPPORT_HS200            0x10u
90 
91 #define DEVICE_SUPPORT_DDR              0x04u
92 #define DEVICE_SUPPORT_SDR              0x03u
93 #define DEVICE_SUPPORT_SDR_50MHZ        0x02u
94 #define DEVICE_SUPPORT_SDR_25MHZ        0x01u
95 #define DEVICE_SUPPORT_LEGACY           0x00u
96 
97 #define DEVICE_STATE_MASK               0xF00u
98 #define DEVICE_STATE_TRANS              0x900u
99 
100 #define MMC_ES_DUAL_DATA_WIDTH_8BIT     0x86u
101 #define MMC_DUAL_DATA_WIDTH_8BIT        0x6u
102 #define MMC_DUAL_DATA_WIDTH_4BIT        0x5u
103 
104 #define MAX_CURRENT_MA                  150u
105 
106 #define SHIFT_2BIT                      0x2u
107 #define SHIFT_4BIT                      0x4u
108 #define SHIFT_8BIT                      0x8u
109 #define SHIFT_9BIT                      9u
110 #define SHIFT_16BIT                     16u
111 #define SHIFT_24BIT                     24u
112 #define SHIFT_27BIT                     27u
113 #define SHIFT_28BIT                     28u
114 #define SHIFT_30BIT                     30u
115 #define SHIFT_31BIT                     31u
116 #define SHIFT_32BIT                     32u
117 
118 #define MASK_32BIT                      0xFFFFFFFFu
119 #define MASK_24BIT                      0xFFFFFFu
120 #define MASK_16BIT                      0xFFFFu
121 #define MASK_12BIT                      0xFFFu
122 #define MASK_8BIT                       0xFFu
123 #define MASK_4BIT                       0xFu
124 
125 #define BYTES_128                       128u
126 #define BYTES_64                        64u
127 #define BYTES_40                        40u
128 #define BYTES_20                        20u
129 #define BYTES_7                         7u
130 #define BYTES_6                         6u
131 #define BYTES_5                         5u
132 #define BYTES_4                         4u
133 #define BYTES_3                         3u
134 #define BYTES_2                         2u
135 #define BYTES_1                         1u
136 
137 #define BYTE_3_MASK                     0xFF0000u
138 #define CQ_TDLBA_ALIGN_MASK            ((1u << 10u) - 1u)
139 
140 #define CARD_INT_STATUS_MASK            0xFEu
141 #define SDCARD_BUSWIDTH_MASK            0xFCu
142 
143 #define DEVICE_HPI_SUPPORT              0x01u
144 #define HPI_WITH_CMD12_SUPPORT          0x02u
145 /* Number outside of normal range- used to tell read
146  block routine to read extended CSD register */
147 #define READ_SEND_EXT_CSD               0xFFFFFFFFu
148 
149 /* Number of temporary sub-buffers, used by to split data
150  bigger than 64KB for smaller parts. Split is made by ADMA module. */
151 #define SDIO_CFG_SDIO_BUFFERS_COUNT     0x4000u
152 
153 #define SDIO_OPCODE_INC                 0x04000000
154 #define SDIO_WRITE                      0x80000000
155 #define SDIO_CSA_REG_ADDR               0x10Fu
156 #define SDIO_CSA_SUPPORT                0x40u
157 #define SDIO_CSA_ENABLE                 0x80u
158 #define SDIO_FBR_BASE_ADDR              0x100u
159 
160 #define NULL_POINTER                    ((void *)0u)
161 /*******************************************************************************
162  * Global variable file scope
163  */
164 /* Relative card address (eMMC/SD) */
165 static uint32_t sdcard_RCA;
166 /* ADMA descriptor table */
167 static uint32_t adma_descriptor_table[SIZE_64KB];
168 static uint8_t *g_desc_addr = NULL_POINTER;
169 static uint8_t g_mmc_init_complete;
170 static uint8_t g_mmc_cq_init_complete;
171 static uint8_t g_mmc_is_multi_blk = MMC_CLEAR;
172 static uint8_t g_sdio_fun_num;
173 static uint8_t g_device_hpi_suport;
174 
175 #ifdef MSS_MMC_INTERNAL_APIS
176 static uint8_t g_device_hpi_set = MMC_CLEAR;
177 static uint32_t g_trans_remain_size = MMC_CLEAR;
178 static uint8_t * g_trans_src_addr = MMC_CLEAR;
179 static uint32_t g_trans_dest_addr = MMC_CLEAR;
180 #endif /* MSS_MMC_INTERNAL_APIS */
181 
182 static uint8_t g_cq_task_id = MMC_CLEAR;
183 /******************************************************************************/
184 struct mmc_trans
185 {
186     volatile mss_mmc_status_t state;
187 };
188 static struct mmc_trans g_mmc_trs_status;
189 /******************************************************************************/
190 struct phydelayaddresses
191 {
192     uint8_t address;
193     MSS_MMC_phydelay phydelaytype;
194 };
195 /*******************************************************************************
196  * Private functions
197  */
198 static mss_mmc_status_t mmccard_oper_config(const mss_mmc_cfg_t * cfg);
199 static mss_mmc_status_t sdcard_oper_config(const mss_mmc_cfg_t * cfg);
200 static mss_mmc_status_t sdio_oper_config(const mss_mmc_cfg_t * cfg);
201 
202 static uint8_t set_host_sdclk(uint32_t frequencyKHz);
203 static mss_mmc_status_t set_data_timeout(uint32_t timeout_val_us);
204 static mss_mmc_status_t  set_sdhost_power(uint32_t voltage);
205 static void get_phy_addr(MSS_MMC_phydelay phydelaytype, uint8_t *phySetAddr);
206 static mss_mmc_status_t phy_training_mmc(uint8_t delay_type, uint32_t clk_rate);
207 static void phy_write_set(uint8_t delay_type, uint8_t delay_value);
208 static mss_mmc_status_t device_set_hs_timing
209 (
210     uint32_t hs_mode,
211     const mss_mmc_cfg_t * cfg
212 );
213 static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg);
214 static void mmc_delay(uint32_t value);
215 static uint8_t is_uhsi_supported(void);
216 static mss_mmc_status_t cmd6_single_block_read
217 (
218     uint32_t src_addr,
219     uint32_t * dst_addr,
220     uint32_t size
221 );
222 static mss_mmc_status_t set_sd_host_device_bus_mode(const mss_mmc_cfg_t * cfg);
223 static mss_mmc_status_t set_host_uhsi_mode
224 (
225     uint8_t access_mode,
226     uint8_t driver_strengh
227 );
228 
229 static mss_mmc_status_t sd_host_process_switch_function
230 (
231     uint8_t function_num,
232     uint8_t group_num
233 );
234 static mss_mmc_status_t sd_host_exec_cmd6_command
235 (
236     uint32_t argument,
237     uint8_t *buffer,
238     uint8_t function_num,
239     uint8_t group_num
240 );
241 static mss_mmc_status_t sd_card_uhsi_supported(void);
242 static mss_mmc_status_t adma2_create_descriptor_table
243 (
244     const uint8_t *data_src,
245     uint32_t data_sz
246 );
247 
248 static mss_mmc_status_t change_sdio_device_bus_mode(const mss_mmc_cfg_t * cfg);
249 static void sdio_host_access_cccr
250 (
251     uint8_t transfer_direction,
252     void *data,
253     uint8_t data_size,
254     uint8_t register_address,
255     uint8_t raw
256 );
257 static void sdio_host_access_fbr
258 (
259     uint8_t transfer_direction,
260     void *data,
261     uint8_t data_size,
262     uint32_t register_address,
263     uint8_t fun_num,
264     uint8_t raw
265 );
266 static void sdio_host_get_tuple_from_cis
267 (
268     uint32_t tuple_address,
269     uint8_t tuple_code,
270     uint8_t *buffer,
271     uint8_t buffer_size
272 );
273 static const uint32_t* calc_write_pattern(const uint8_t bus_width);
274 static void host_mmc_tune(uint8_t value);
275 static mss_mmc_status_t sd_tuning(void);
276 static uint8_t calc_longest_valid_delay_chain_val(const uint8_t* pattern_ok);
277 static mss_mmc_status_t read_tune_block
278 (
279     uint32_t *read_data,
280     uint32_t size,
281     uint8_t cmd
282 );
283 static mss_mmc_status_t execute_tunning_mmc(uint8_t data_width);
284 static cif_response_t check_device_status(cif_response_t rsp_status);
285 
286 static mss_mmc_handler_t g_transfer_complete_handler_t;
287 /*****************************************************************************/
288 
289 /*-------------------------------------------------------------------------*//**
290  * See "mss_mmc.h" for details of how to use this function.
291  */
292 mss_mmc_status_t
MSS_MMC_init(const mss_mmc_cfg_t * cfg)293 MSS_MMC_init
294 (
295     const mss_mmc_cfg_t * cfg
296 )
297 {
298     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
299     cif_response_t response_status;
300     uint32_t reg, cap, srs10, hrs6;
301     uint32_t csd_reg[BLK_SIZE/WORD_SIZE];
302     uint8_t *pcsd_reg = NULL_POINTER;
303 
304     uint32_t hw_sec_count;
305     uint8_t hw_ext_csd_rev;
306     uint8_t hw_device_type;
307     uint8_t hw_strobe_suport;
308     uint8_t hw_hs_timing;
309 
310     /* Reset MMC */
311     SYSREG->SOFT_RESET_CR &= ~(MMC_SET << MMC_SOFTWARE_RESET_SHIFT);
312     /* Disable MMC interrupt */
313     PLIC_DisableIRQ(MMC_main_PLIC);
314 
315     g_transfer_complete_handler_t = NULL_POINTER;
316     g_mmc_init_complete = MMC_CLEAR;
317     g_sdio_fun_num = MMC_CLEAR;
318     g_mmc_trs_status.state = MSS_MMC_NOT_INITIALISED;
319     /* Set RCA default value */
320     sdcard_RCA = RCA_VALUE;
321     /* Reset host controller*/
322     MMC->HRS00 |= HRS0_SOFTWARE_RESET;
323     mmc_delay(DELAY_COUNT);
324 
325     do
326     {
327        reg = MMC->HRS00;
328     }while ((reg & HRS0_SOFTWARE_RESET) != MMC_CLEAR);
329 
330     /* Set de-bounce time */
331     MMC->HRS01 = DEBOUNCING_TIME;
332     /* eMMC Mode select in Host controller */
333     hrs6 = MMC->HRS06;
334     hrs6 &= ~MSS_MMC_MODE_MASK;
335     /* Check card type SD or MMC */
336     if (MSS_MMC_CARD_TYPE_MMC == cfg->card_type)
337     {
338         hrs6 |= MSS_MMC_MODE_LEGACY;
339     }
340     else
341     {
342         hrs6 |= MSS_MMC_MODE_SDCARD;
343     }
344     MMC->HRS06 = hrs6;
345     /* Clear error/interrupt status */
346     MMC->SRS12 = MMC_STATUS_CLEAR;
347 
348     reg = MMC->SRS15;
349     cap = MMC->SRS16;
350     /* Check DMA 64 bit support */
351     if ((cap & SRS16_64BIT_SUPPORT) != MMC_CLEAR)
352     {
353         reg |= SRS15_64_BIT_ADDRESSING;
354         reg |= SRS15_HOST_4_ENABLE;
355         MMC->SRS15 = reg;
356     }
357     /* Enable error/interrupt status */
358     MMC->SRS13 = SRS13_STATUS_EN;
359     /* Disable error/interrupt */
360     MMC->SRS14 = MMC_CLEAR;
361     /* Set 500ms data timeout */
362     ret_status = set_data_timeout(DATA_TIMEOUT_VALUE);
363     if (MSS_MMC_NO_ERROR != ret_status)
364     {
365         ret_status = MSS_MMC_NOT_INITIALISED;
366     }
367     /* Turn-off Host Controller Power */
368     ret_status = set_sdhost_power(MMC_CLEAR);
369     if (MSS_MMC_NO_ERROR != ret_status)
370     {
371         ret_status = MSS_MMC_NOT_INITIALISED;
372     }
373 
374     reg = MMC->SRS09;
375     /* If card stable is not set it means that something is wrong */
376     if (((reg & SRS9_CARD_STATE_STABLE) == MMC_CLEAR) &&
377                                     (MSS_MMC_NO_ERROR == ret_status))
378     {
379         ret_status = MSS_MMC_CARD_STATE_STABLE_ERR;
380     }
381     /* If card is not inserted to SD socked */
382     if (MSS_MMC_CARD_TYPE_SD == cfg->card_type)
383     {
384         if (((reg & SRS9_CARD_INSERTED) == MMC_CLEAR) &&
385                                     (MSS_MMC_NO_ERROR == ret_status))
386         {
387             ret_status = MSS_MMC_CARD_INSERTED_ERR;
388         }
389     }
390     /* Set 1-bit bus mode */
391     srs10 = MMC->SRS10;
392     srs10 &= ~SRS10_DATA_WIDTH_4BIT;
393     srs10 &= ~SRS10_EXTENDED_DATA_TRANSFER_WIDTH;
394     MMC->SRS10 = srs10;
395 
396     if ((MSS_MMC_CARD_TYPE_MMC == cfg->card_type) && (MSS_MMC_NO_ERROR == ret_status))
397     {
398         switch (cfg->bus_voltage)
399         {
400             case MSS_MMC_1_8V_BUS_VOLTAGE:
401                 /* Set Host Controller power to 1.8v */
402                 ret_status = set_sdhost_power(SRS10_SET_1_8V_BUS_VOLTAGE);
403                 if (ret_status != MSS_MMC_NO_ERROR)
404                 {
405                     ret_status = MSS_MMC_NOT_INITIALISED;
406                 }
407                 break;
408 
409             case MSS_MMC_3_3V_BUS_VOLTAGE:
410                 if (((MSS_MMC_MODE_HS200 == cfg->bus_speed_mode) ||
411                     (MSS_MMC_MODE_HS400_ES == cfg->bus_speed_mode) ||
412                     (MSS_MMC_MODE_HS400 == cfg->bus_speed_mode)))
413                 {
414                     ret_status = MSS_MMC_NOT_INITIALISED;
415                 }
416                 else
417                 {
418                     /* Set Host Controller power to 3.3v */
419                     ret_status = set_sdhost_power(SRS10_SET_3_3V_BUS_VOLTAGE);
420                     if (ret_status != MSS_MMC_NO_ERROR)
421                     {
422                         ret_status = MSS_MMC_NOT_INITIALISED;
423                     }
424                 }
425                 break;
426 
427             default:
428                 ret_status = MSS_MMC_NOT_INITIALISED;
429         }
430     }
431     else
432     {
433         if (MSS_MMC_NO_ERROR == ret_status)
434         {
435             /* Set Host Controller power to 3.3v */
436             ret_status = set_sdhost_power(SRS10_SET_3_3V_BUS_VOLTAGE);
437             if (ret_status != MSS_MMC_NO_ERROR)
438             {
439                 ret_status = MSS_MMC_NOT_INITIALISED;
440             }
441         }
442     }
443 
444     if (MSS_MMC_NO_ERROR == ret_status)
445     {
446         /* Set 400khz clock */
447         set_host_sdclk(MSS_MMC_CLOCK_400KHZ);
448     }
449     mmc_delay(DELAY_COUNT);
450     /* MMC memory */
451     if ((MSS_MMC_CARD_TYPE_MMC == cfg->card_type) && (MSS_MMC_NO_ERROR == ret_status))
452     {
453         response_status = cif_send_cmd(RESET_ARG, MMC_CMD_0_GO_IDLE_STATE,
454                                                     MSS_MMC_RESPONSE_NO_RESP);
455         mmc_delay(DELAY_COUNT);
456         /* Reset CMD is success */
457         if (TRANSFER_IF_SUCCESS == response_status)
458         {
459             ret_status = mmccard_oper_config(cfg);
460             if (MSS_MMC_CARD_SELECT_SUCCESS == ret_status)
461             {
462                  /* mmc init success */
463                 g_mmc_init_complete = MMC_SET;
464                 /* Set Block length in device */
465                 response_status = cif_send_cmd(BLK_SIZE, SD_CMD_16,
466                                                         MSS_MMC_RESPONSE_R1);
467                 if (TRANSFER_IF_SUCCESS == response_status)
468                 {
469                     /* Read EXT_CSD */
470                     ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
471                     if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
472                     {
473                         pcsd_reg = ((uint8_t *)csd_reg);
474                         hw_device_type   =  pcsd_reg[EXT_CSD_CARD_TYPE_OFFSET];
475                         hw_hs_timing   = pcsd_reg[EXT_CSD_HS_TIMING_OFFSET];
476                         hw_strobe_suport = pcsd_reg [EXT_CSD_ES_SUPPORT_OFFSET];
477                         g_device_hpi_suport = pcsd_reg[EXT_CSD_ES_SUPPORT_OFFSET];
478 
479                         if ((g_device_hpi_suport & DEVICE_HPI_SUPPORT) == DEVICE_HPI_SUPPORT)
480                         {
481                             /* Enable HPI in device */
482                             response_status = cif_send_cmd(MMC_HPI_ENABLE,
483                                                             MMC_CMD_6_SWITCH,
484                                                             MSS_MMC_RESPONSE_R1B);
485                             if (TRANSFER_IF_FAIL != response_status)
486                             {
487                                 response_status = check_device_status(response_status);
488                             }
489                         }
490                         switch (cfg->bus_speed_mode)
491                         {
492                             case MSS_MMC_MODE_HS400_ES:
493 
494                                 if (((hw_device_type & DEVICE_SUPPORT_HS400) == DEVICE_SUPPORT_HS400)
495                                                 && (hw_strobe_suport == MMC_SET))
496                                 {
497                                     ret_status =  set_device_hs400_mode(cfg);
498                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
499                                     {
500                                         ret_status = MSS_MMC_HS400_MODE_SETUP_FAILURE;
501                                     }
502                                 }
503                                 else
504                                 {
505                                     ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_HS400;
506                                 }
507                                 break;
508 
509                             case MSS_MMC_MODE_HS400:
510 
511                                 if ((hw_device_type & DEVICE_SUPPORT_HS400) == DEVICE_SUPPORT_HS400)
512                                 {
513                                     ret_status =  set_device_hs400_mode(cfg);
514                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
515                                     {
516                                         ret_status = MSS_MMC_HS400_MODE_SETUP_FAILURE;
517                                     }
518                                 }
519                                 else
520                                 {
521                                     ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_HS400;
522                                 }
523                                 break;
524 
525                             case MSS_MMC_MODE_HS200:
526 
527                                 if ((hw_device_type & DEVICE_SUPPORT_HS200) == DEVICE_SUPPORT_HS200)
528                                 {
529                                     ret_status = device_set_hs_timing(DEVICE_SUPPORT_HS200, cfg);
530                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
531                                     {
532                                         ret_status = MSS_MMC_MODE_NOT_SUPPORT_DATAWIDTH;
533                                     }
534                                     else
535                                     {
536                                         ret_status = execute_tunning_mmc(cfg->data_bus_width);
537                                         if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
538                                         {
539                                             ret_status = MSS_MMC_TRANSFER_FAIL;
540                                         }
541                                     }
542                                 }
543                                 else
544                                 {
545                                     ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_HS200;
546                                 }
547                                 break;
548 
549                             case MSS_MMC_MODE_DDR:
550 
551                                 if ((hw_device_type & DEVICE_SUPPORT_DDR) == DEVICE_SUPPORT_DDR)
552                                 {
553                                     ret_status = device_set_hs_timing(DEVICE_SUPPORT_DDR, cfg);
554                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
555                                     {
556                                         ret_status = MSS_MMC_MODE_NOT_SUPPORT_DATAWIDTH;
557                                     }
558                                     /* Enable Host High Speed */
559                                     MMC->SRS10 |= (MMC_SET << SHIFT_2BIT);
560                                 }
561                                 else
562                                 {
563                                     ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_DDR;
564                                 }
565                                 break;
566 
567                             case MSS_MMC_MODE_SDR:
568 
569                                 if ((hw_device_type & DEVICE_SUPPORT_SDR_50MHZ) == DEVICE_SUPPORT_SDR_50MHZ)
570                                 {
571                                     ret_status = device_set_hs_timing(DEVICE_SUPPORT_SDR, cfg);
572                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
573                                     {
574                                         ret_status = MSS_MMC_DWIDTH_ERR;
575                                     }
576                                     /* Enable Host High Speed */
577                                     MMC->SRS10 |= (MMC_SET << SHIFT_2BIT);
578                                 }
579                                 else if ((hw_device_type & DEVICE_SUPPORT_SDR_25MHZ) == DEVICE_SUPPORT_SDR_25MHZ)
580                                 {
581                                     ret_status = device_set_hs_timing(DEVICE_SUPPORT_SDR, cfg);
582                                     if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
583                                     {
584                                         ret_status = MSS_MMC_DWIDTH_ERR;
585                                     }
586                                 }
587                                 else
588                                 {
589                                     ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_SDR;
590                                 }
591                                 break;
592 
593                             case MSS_MMC_MODE_LEGACY:
594 
595                                 ret_status = device_set_hs_timing(DEVICE_SUPPORT_LEGACY, cfg);
596                                 if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
597                                 {
598                                     ret_status = MSS_MMC_CLK_DIV_ERR;
599                                 }
600                                 break;
601 
602                             default:
603 
604                                 ret_status = MSS_MMC_INIT_FAILURE;
605                                 break;
606                         }
607 
608                         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
609                         {
610                             ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
611                             if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
612                             {
613                                 pcsd_reg = (uint8_t *)csd_reg;
614                                 /* Offsets defined in JESD84-B51 extended CSD */
615                                 hw_sec_count   = csd_reg[EXT_CSD_SECTOR_COUNT_OFFSET/WORD_SIZE];
616                                 hw_ext_csd_rev = pcsd_reg[EXT_CSD_REVISION_OFFSET] & BYTE_MASK;
617                                 hw_hs_timing   = pcsd_reg[EXT_CSD_HS_TIMING_OFFSET];
618 
619                                 if ((MMC_CLEAR == hw_hs_timing) &&
620                                     (cfg->bus_speed_mode != MSS_MMC_MODE_LEGACY))
621                                 {
622                                     ret_status = MSS_MMC_CLK_DIV_ERR;
623                                 }
624                             }
625                         }
626 
627                         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
628                         {
629                             ret_status = MSS_MMC_INIT_SUCCESS;
630                             g_mmc_trs_status.state = MSS_MMC_INIT_SUCCESS;
631                         }
632                         else
633                         {
634                             g_mmc_init_complete = MMC_CLEAR;
635                             ret_status = MSS_MMC_INIT_FAILURE;
636                             g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
637                         }
638                     }
639                     else
640                     {
641                         g_mmc_init_complete = MMC_CLEAR;
642                         ret_status = MSS_MMC_INIT_FAILURE;
643                         g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
644                     }
645                 }
646                 else
647                 {
648                     g_mmc_init_complete = MMC_CLEAR;
649                     ret_status = MSS_MMC_INIT_FAILURE;
650                     g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
651                 }
652             }
653         }
654         else
655         {
656             ret_status = MSS_MMC_RESET_ERR;
657         }
658     }
659     /* SD Memory card */
660     else if ((MSS_MMC_CARD_TYPE_SD == cfg->card_type) && (MSS_MMC_NO_ERROR == ret_status))
661     {
662         response_status = cif_send_cmd(RESET_ARG, MMC_CMD_0_GO_IDLE_STATE,
663                                                     MSS_MMC_RESPONSE_NO_RESP);
664         mmc_delay(DELAY_COUNT);
665 
666         if (TRANSFER_IF_SUCCESS == response_status)
667         {
668             /* Specify the operating conditions to the device */
669             ret_status = sdcard_oper_config(cfg);
670 
671             if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
672             {
673                 ret_status = MSS_MMC_INIT_SUCCESS;
674                 g_mmc_trs_status.state = MSS_MMC_INIT_SUCCESS;
675             }
676             else
677             {
678                 g_mmc_init_complete = MMC_CLEAR;
679                 ret_status = MSS_MMC_INIT_FAILURE;
680                 g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
681             }
682         }
683         else
684         {
685             g_mmc_init_complete = MMC_CLEAR;
686             ret_status = MSS_MMC_INIT_FAILURE;
687             g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
688         }
689     }
690     /* SDIO card */
691     else if ((MSS_MMC_CARD_TYPE_SDIO == cfg->card_type) && (MSS_MMC_NO_ERROR == ret_status))
692     {
693         ret_status = sdio_oper_config(cfg);
694 
695         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
696         {
697             ret_status = MSS_MMC_INIT_SUCCESS;
698             g_mmc_trs_status.state = MSS_MMC_INIT_SUCCESS;
699         }
700         else
701         {
702             g_mmc_init_complete = MMC_CLEAR;
703             ret_status = MSS_MMC_INIT_FAILURE;
704             g_mmc_trs_status.state = MSS_MMC_INIT_FAILURE;
705         }
706     }
707     else
708     {
709         ret_status = MSS_MMC_NOT_INITIALISED;
710         g_mmc_init_complete = MMC_CLEAR;
711         g_mmc_trs_status.state = MSS_MMC_NOT_INITIALISED;
712     }
713     /* Clear interrupts */
714     MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
715                             | SRS12_CARD_INTERRUPT
716                             | SRS12_CARD_REMOVAL
717                             | SRS12_CARD_INSERTION);
718     return(ret_status);
719 }
720 
721 /*******************************************************************************
722 *************************** READ APIs *****************************************
723 *******************************************************************************/
724 /*-------------------------------------------------------------------------*//**
725  * See "mss_mmc.h" for details of how to use this function.
726  */
727 mss_mmc_status_t
MSS_MMC_single_block_read(uint32_t src_addr,uint32_t * dst_addr)728 MSS_MMC_single_block_read
729 (
730     uint32_t src_addr,
731     uint32_t * dst_addr
732 )
733 {
734     uint32_t isr_errors;
735     uint32_t blk_read, srs03_data, srs9;
736     uint16_t word_cnt = (BLK_SIZE/WORD_SIZE);
737     uint32_t idx_cnt;
738     cif_response_t response_status;
739     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
740 
741     if (g_mmc_init_complete == MMC_SET)
742     {
743         /* Check eMMC/SD device is busy */
744         do
745         {
746             response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
747                                         MMC_CMD_13_SEND_STATUS,
748                                         MSS_MMC_RESPONSE_R1);
749         } while (DEVICE_BUSY == response_status);
750         /* Device is ready */
751         if (TRANSFER_IF_SUCCESS == response_status)
752         {
753             /* Reset Data and cmd line */
754             MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
755             mmc_delay(MASK_8BIT);
756             /* Block length and count*/
757             MMC->SRS01 = (BLK_SIZE | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
758 
759             /* DPS, Data transfer direction - read */
760             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ
761                         |SRS3_BLOCK_COUNT_ENABLE | SRS3_RESP_ERR_CHECK_EN
762                         | SRS3_RESP_INTER_DISABLE | SRS3_RESPONSE_CHECK_TYPE_R1
763                         | SRS3_RESP_LENGTH_48 | SRS3_CRC_CHECK_EN
764                         | SRS3_INDEX_CHECK_EN);
765             /* Check cmd and data line busy */
766             do
767             {
768                 srs9 = MMC->SRS09;
769             }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
770 
771             /* eMMC EXT_CSD read */
772             if (READ_SEND_EXT_CSD == src_addr)
773             {
774                     /* Command argument */
775                     MMC->SRS02 = MMC_CLEAR;
776                     /* execute command */
777                     MMC->SRS03 = (uint32_t)((MMC_CMD_8_SEND_EXT_CSD << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
778             }/* SD card ACMD51 read */
779             else if (READ_SEND_SCR == src_addr)
780             {
781                 MMC->SRS01 = (SCR_REG_DATA_SIZE | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
782                 word_cnt = SHIFT_2BIT;
783                 response_status = cif_send_cmd(SCR_REG_DATA_SIZE,
784                                             SD_CMD_16,
785                                             MSS_MMC_RESPONSE_R1);
786 
787                 response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
788                                             SD_CMD_55,
789                                             MSS_MMC_RESPONSE_R1);
790                 /* Command argument */
791                 MMC->SRS02 = MMC_CLEAR;
792                 /* execute command */
793                 MMC->SRS03 = (uint32_t)((SD_ACMD_51 << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
794             }
795             else
796             {
797                 /* Command argument */
798                 MMC->SRS02 = src_addr;
799                 /* Execute command */
800                 MMC->SRS03 = (uint32_t)((MMC_CMD_17_READ_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
801             }
802 
803             idx_cnt = MMC_CLEAR;
804 
805             do
806             {
807                 blk_read = MMC->SRS12;
808             } while (MMC_CLEAR == (blk_read & (SRS12_BUFFER_READ_READY | SRS12_ERROR_INTERRUPT)));
809             /* Read in the contents of the Buffer */
810             if ((blk_read & SRS12_BUFFER_READ_READY) != MMC_CLEAR)
811             {
812                 while (word_cnt > (BUFF_EMPTY))
813                 {
814                     dst_addr[idx_cnt] = MMC->SRS08;
815                     ++idx_cnt;
816                     --word_cnt;
817                 }
818             }
819 
820             isr_errors = MMC->SRS12;
821             /* Abort if any errors*/
822             if ((SRS12_ERROR_STATUS_MASK & isr_errors) == MMC_CLEAR)
823             {
824                 /*
825                  * Ensure no error fields in Card Status register are set and
826                  * that the device is idle before this function returns.
827                  */
828                 do
829                 {
830                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
831                                                 MMC_CMD_13_SEND_STATUS,
832                                                 MSS_MMC_RESPONSE_R1);
833                 } while (DEVICE_BUSY == response_status);
834 
835                 if (TRANSFER_IF_SUCCESS == response_status)
836                 {
837                     ret_status = MSS_MMC_TRANSFER_SUCCESS;
838                 }
839                 else
840                 {
841                     ret_status = MSS_MMC_DEVICE_ERROR;
842                 }
843             }
844             else
845             {
846                 ret_status = MSS_MMC_ERR_INTERRUPT;
847             }
848             /* Clear all status interrupts except:
849              * current limit error, card interrupt, card removal,
850              * card insertion
851              */
852             MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
853                                 | SRS12_CARD_INTERRUPT
854                                 | SRS12_CARD_REMOVAL
855                                 | SRS12_CARD_INSERTION);
856         }
857         else
858         {
859             ret_status = MSS_MMC_DEVICE_ERROR;
860         }
861     }
862     else
863     {
864         ret_status = MSS_MMC_NOT_INITIALISED;
865     }
866     return ret_status;
867 }
868 /*-------------------------------------------------------------------------*//**
869  * See "mss_mmc.h" for details of how to use this function.
870  */
871 mss_mmc_status_t
MSS_MMC_sdma_read(uint32_t src,uint8_t * dest,uint32_t size)872 MSS_MMC_sdma_read
873 (
874     uint32_t src,
875     uint8_t *dest,
876     uint32_t size
877 )
878 {
879     uint32_t blockcount;
880     uint32_t argument;
881     uint32_t blocklen;
882     uint32_t tmp, srs03_data, srs9;
883     cif_response_t response_status;
884     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
885 
886     blocklen = BLK_SIZE;
887     argument = src;
888 
889     if (g_mmc_init_complete == MMC_SET)
890     {
891         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
892         {
893             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
894         }
895         else
896         {
897             /* Size should be divided by 512, not greater than (32MB - 512) */
898             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
899                     || (size == MMC_CLEAR) || (dest == NULL_POINTER))
900             {
901                 ret_status = MSS_MMC_INVALID_PARAMETER;
902                 g_mmc_trs_status.state = MSS_MMC_INVALID_PARAMETER;
903             }
904             else
905             {
906                 /* Disable PLIC interrupt for MMC */
907                 PLIC_DisableIRQ(MMC_main_PLIC);
908                 /* Disable error/interrupt */
909                 MMC->SRS14 = MMC_CLEAR;
910                 /* Check eMMC/SD device is busy */
911                 do
912                 {
913                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
914                                                     MMC_CMD_13_SEND_STATUS,
915                                                     MSS_MMC_RESPONSE_R1);
916                 } while (DEVICE_BUSY == response_status);
917 
918                 if (TRANSFER_IF_SUCCESS == response_status)
919                 {
920                     /* Reset Data and cmd line */
921                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
922                     mmc_delay(MASK_8BIT);
923                     /* Calculate block count */
924                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
925                     /* Select SDMA */
926                     tmp = MMC->SRS10;
927                     tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
928                     MMC->SRS10 = (tmp | SRS10_DMA_SELECT_SDMA);
929                     /* SDMA setup */
930                     MMC->SRS22 = ((uint32_t)((uintptr_t)dest));
931                     MMC->SRS23 = ((uint32_t)(((uint64_t)((uintptr_t)dest)) >> MMC_64BIT_UPPER_ADDR_SHIFT));
932                     /* Block length and count SDMA buffer boundary */
933                     MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT)
934                                             |  SRS1_DMA_BUFF_SIZE_512KB);
935 
936                     /* Enable interrupts */
937                     MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN |
938                                 SRS14_TRANSFER_COMPLETE_SIG_EN |
939                                 SRS14_DMA_INTERRUPT_SIG_EN |
940                                 SRS14_DATA_TIMEOUT_ERR_SIG_EN);
941 
942                     PLIC_EnableIRQ(MMC_main_PLIC);
943 
944                     /* Check cmd and data line busy */
945                     do
946                     {
947                         srs9 = MMC->SRS09;
948                     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
949 
950                     /* Multi Block read */
951                     if (blockcount > MMC_SET)
952                     {
953                         /* DPS, Data transfer direction - read */
954                         srs03_data = ((uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ
955                                             | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
956                                             | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
957                                             | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
958                                             | SRS3_DMA_ENABLE));
959 
960                         /* Multi block transfer */
961                         g_mmc_is_multi_blk = MMC_SET;
962                         /* Command argument */
963                         MMC->SRS02 = argument;
964                         /* execute command */
965                         MMC->SRS03 = ((uint32_t)((MMC_CMD_18_READ_MULTIPLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data));
966                     }
967                     else /* Single block read */
968                     {
969                         /* DPS, Data transfer direction - read */
970                         srs03_data = ((uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ
971                                                 | SRS3_BLOCK_COUNT_ENABLE
972                                                 | SRS3_RESPONSE_CHECK_TYPE_R1
973                                                 | SRS3_RESP_LENGTH_48
974                                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
975                                                 | SRS3_DMA_ENABLE));
976                         /* Single block transfer */
977                         g_mmc_is_multi_blk = MMC_CLEAR;
978                         /* Command argument */
979                         MMC->SRS02 = argument;
980                         /* Execute command */
981                         MMC->SRS03 = ((uint32_t)((MMC_CMD_17_READ_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data));
982                     }
983                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
984                     ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
985                 }
986                 else
987                 {
988                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
989                     ret_status = MSS_MMC_DEVICE_ERROR;
990                 }
991             }
992         }
993     }
994     else
995     {
996         ret_status = MSS_MMC_NOT_INITIALISED;
997     }
998     return ret_status;
999 }
1000 /*-------------------------------------------------------------------------*//**
1001  * See "mss_mmc.h" for details of how to use this function.
1002  */
1003 mss_mmc_status_t
MSS_MMC_adma2_read(uint32_t src,uint8_t * dest,uint32_t size)1004 MSS_MMC_adma2_read
1005 (
1006     uint32_t src,
1007     uint8_t *dest,
1008     uint32_t size
1009 )
1010 {
1011     uint32_t blockcount;
1012     uint32_t argument;
1013     uint32_t blocklen;
1014     uint32_t tmp, srs03_data, srs9;
1015     cif_response_t response_status;
1016     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1017 
1018     blocklen = BLK_SIZE;
1019     argument = src;
1020 
1021     if (g_mmc_init_complete == MMC_SET)
1022     {
1023         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
1024         {
1025             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1026         }
1027         else
1028         {
1029             /* Size should be divided by 512, not greater than (32MB - 512) */
1030             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
1031                     || (size == MMC_CLEAR) || (dest == NULL_POINTER))
1032             {
1033                 ret_status = MSS_MMC_INVALID_PARAMETER;
1034             }
1035             else
1036             {
1037                 /* Disable PLIC interrupt for MMC */
1038                 PLIC_DisableIRQ(MMC_main_PLIC);
1039                 /* Disable error/interrupt */
1040                 MMC->SRS14 = MMC_CLEAR;
1041                 /* Check eMMC/SD device is busy */
1042                 do
1043                 {
1044                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
1045                                                 MMC_CMD_13_SEND_STATUS,
1046                                                 MSS_MMC_RESPONSE_R1);
1047                 } while (DEVICE_BUSY == response_status);
1048 
1049                 if (TRANSFER_IF_SUCCESS == response_status)
1050                 {
1051                     /* Reset Data and cmd line */
1052                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1053                     mmc_delay(MASK_8BIT);
1054                     /* Calculate block count */
1055                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
1056                     /* Create ADMA2 descriptor table */
1057                     ret_status = adma2_create_descriptor_table(dest, size);
1058                     if (ret_status != MSS_MMC_INVALID_PARAMETER)
1059                     {
1060                         /* ADMA setup */
1061                         MMC->SRS22 = (uint32_t)(uintptr_t)adma_descriptor_table;
1062                         MMC->SRS23 = (uint32_t)(((uint64_t)(uintptr_t)adma_descriptor_table) >> MMC_64BIT_UPPER_ADDR_SHIFT);
1063                         /* Select ADMA2 */
1064                         tmp = MMC->SRS10;
1065                         tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
1066                         MMC->SRS10 = (tmp | SRS10_DMA_SELECT_ADMA2);
1067                         /* Block length and count */
1068                         MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT));
1069                         /* Enable interrupts */
1070                         MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN |
1071                                         SRS14_TRANSFER_COMPLETE_SIG_EN  |
1072                                         SRS14_DATA_TIMEOUT_ERR_SIG_EN |
1073                                         SRS14_ADMA_ERROR_SIG_EN);
1074                         PLIC_EnableIRQ(MMC_main_PLIC);
1075                         /* Check cmd and data line busy */
1076                         do
1077                         {
1078                             srs9 = MMC->SRS09;
1079                         }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1080                         /* Multi Block read */
1081                         if (blockcount > MMC_SET)
1082                         {
1083                             /* DPS, Data transfer direction - read */
1084                             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ
1085                                                 | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
1086                                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1087                                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
1088                                                 | SRS3_DMA_ENABLE);
1089                             /* Multi block transfer */
1090                             g_mmc_is_multi_blk = MMC_SET;
1091                             /* Command argument */
1092                             MMC->SRS02 = argument;
1093                             /* Execute command */
1094                             MMC->SRS03 = (uint32_t)((MMC_CMD_18_READ_MULTIPLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1095                         }
1096                         else /* Single block read */
1097                         {
1098                             /* DPS, Data transfer direction - read */
1099                             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ | SRS3_BLOCK_COUNT_ENABLE
1100                                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1101                                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
1102                                                 | SRS3_DMA_ENABLE);
1103                             /* Single block transfer */
1104                             g_mmc_is_multi_blk = MMC_CLEAR;
1105                             /* Command argument */
1106                             MMC->SRS02 = argument;
1107                             /* Execute command */
1108                             MMC->SRS03 = (uint32_t)((MMC_CMD_17_READ_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1109                         }
1110                         g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
1111                         ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1112                     }
1113                 }
1114                 else
1115                 {
1116                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
1117                     ret_status = MSS_MMC_DEVICE_ERROR;
1118                 }
1119             }
1120         }
1121     }
1122     else
1123     {
1124         ret_status = MSS_MMC_NOT_INITIALISED;
1125     }
1126     return ret_status;
1127 }
1128 /*-------------------------------------------------------------------------*//**
1129  * See "mss_mmc.h" for details of how to use this function.
1130  */
1131 mss_mmc_status_t
MSS_MMC_sdio_single_block_read(uint32_t src_addr,uint32_t * dst_addr,uint16_t data_size)1132 MSS_MMC_sdio_single_block_read
1133 (
1134     uint32_t src_addr,
1135     uint32_t *dst_addr,
1136     uint16_t data_size
1137 )
1138 {
1139     uint32_t isr_errors;
1140     uint32_t blk_read, srs03_data, srs9;
1141     uint16_t word_cnt = (data_size/WORD_SIZE);
1142     uint32_t arguement;
1143     uint32_t idx_cnt;
1144     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1145 
1146     if (g_mmc_init_complete == MMC_SET)
1147     {
1148         if ((data_size != MMC_CLEAR) && (data_size <= BLK_SIZE)
1149             && (dst_addr != NULL_POINTER))
1150         {
1151             sdio_host_access_fbr(SDIOHOST_CCCR_WRITE, &src_addr, BYTES_3,
1152                                 MSS_MMC_FBR_ADDR_CSA, MMC_SET, MMC_CLEAR);
1153             /* Reset Data and cmd line */
1154             MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1155             mmc_delay(MASK_8BIT);
1156             /* Block length and count*/
1157             MMC->SRS01 = (data_size | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
1158 
1159             /* DPS, Data transfer direction - read */
1160             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ |SRS3_BLOCK_COUNT_ENABLE
1161                                 | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
1162                                 | SRS3_RESPONSE_CHECK_TYPE_R5 | SRS3_RESP_LENGTH_48
1163                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
1164             /* Check cmd and data line busy */
1165             do
1166             {
1167                 srs9 = MMC->SRS09;
1168             }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1169 
1170             if(data_size == BLK_SIZE)
1171             {
1172                 data_size = MMC_CLEAR;
1173             }
1174             arguement = (SDIO_CSA_REG_ADDR << SHIFT_9BIT) | SDIO_OPCODE_INC | data_size;
1175                 /* Command argument */
1176             MMC->SRS02 = arguement;
1177                 /* Execute command */
1178             MMC->SRS03 = (uint32_t)((SDIO_CMD_53_IO_RW_EXTENDED << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1179 
1180             idx_cnt = MMC_CLEAR;
1181 
1182             do
1183             {
1184                 blk_read = MMC->SRS12;
1185             } while (MMC_CLEAR == (blk_read & (SRS12_BUFFER_READ_READY | SRS12_ERROR_INTERRUPT)));
1186                     /* Read in the contents of the Buffer */
1187             if ((blk_read & SRS12_BUFFER_READ_READY) != MMC_CLEAR)
1188             {
1189                 while (word_cnt > (BUFF_EMPTY))
1190                 {
1191                     dst_addr[idx_cnt] = MMC->SRS08;
1192                     ++idx_cnt;
1193                     --word_cnt;
1194                 }
1195             }
1196             isr_errors = MMC->SRS12;
1197             /* Abort if any errors*/
1198             if ((SRS12_ERROR_STATUS_MASK & isr_errors) == MMC_CLEAR)
1199             {
1200                 if ((SRS12_TRANSFER_COMPLETE & isr_errors) == SRS12_TRANSFER_COMPLETE)
1201                 {
1202                 ret_status = MSS_MMC_TRANSFER_SUCCESS;
1203                 }
1204                 else
1205                 {
1206                     ret_status = MSS_MMC_TRANSFER_FAIL;
1207                 }
1208             }
1209             else
1210             {
1211                 ret_status = MSS_MMC_ERR_INTERRUPT;
1212             }
1213             /* Clear all status interrupts except:
1214             *  current limit error, card interrupt, card removal, card insertion */
1215             MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
1216                                     | SRS12_CARD_INTERRUPT
1217                                     | SRS12_CARD_REMOVAL
1218                                     | SRS12_CARD_INSERTION);
1219         }
1220         else
1221         {
1222             ret_status = MSS_MMC_INVALID_PARAMETER;
1223         }
1224     }
1225     else
1226     {
1227         ret_status = MSS_MMC_NOT_INITIALISED;
1228     }
1229     return (ret_status);
1230 }
1231 /*******************************************************************************
1232 *************************** WRITE APIs *****************************************
1233 *******************************************************************************/
1234 /*-------------------------------------------------------------------------*//**
1235  * See "mss_mmc.h" for details of how to use this function.
1236  */
1237 mss_mmc_status_t
MSS_MMC_single_block_write(const uint32_t * src_addr,uint32_t dst_addr)1238 MSS_MMC_single_block_write
1239 (
1240     const uint32_t * src_addr,
1241     uint32_t dst_addr
1242 )
1243 {
1244     cif_response_t response_status;
1245     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1246     uint16_t word_cnt = MMC_CLEAR;
1247     uint8_t blk_tran_err;
1248     uint8_t blk_write;
1249     uint32_t srs03_data, srs9;
1250 
1251     if (g_mmc_init_complete == MMC_SET)
1252     {
1253         /* Check eMMC/SD device is busy */
1254         do
1255         {
1256             response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
1257                                             MMC_CMD_13_SEND_STATUS,
1258                                             MSS_MMC_RESPONSE_R1);
1259         } while (DEVICE_BUSY == response_status);
1260         /* Device ready */
1261         if (TRANSFER_IF_SUCCESS == response_status)
1262         {
1263             /* Reset Data and cmd line */
1264             MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1265             mmc_delay(MASK_8BIT);
1266             /* Block length and count*/
1267             MMC->SRS01 = (BLK_SIZE | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
1268             /* DPS, Data transfer direction - read */
1269             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE |SRS3_BLOCK_COUNT_ENABLE
1270                                 | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
1271                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1272                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
1273             /* Check cmd and data line busy */
1274             do
1275             {
1276                 srs9 = MMC->SRS09;
1277             }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1278             /* Command argument */
1279             MMC->SRS02 = dst_addr;
1280             /* Execute command */
1281             MMC->SRS03 = (uint32_t)((MMC_CMD_24_WRITE_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1282 
1283             do
1284             {
1285                 blk_write = MMC->SRS12;
1286             } while (MMC_CLEAR == (blk_write & (SRS12_BUFFER_WRITE_READY | SRS12_ERROR_INTERRUPT)));
1287             /*
1288             * Load the block of data into the
1289             * buffer, four bytes at a time through the Buffer Data Register.
1290             */
1291             if((blk_write & SRS12_BUFFER_WRITE_READY) != MMC_CLEAR)
1292             {
1293                 while((BLK_SIZE/WORD_SIZE) > word_cnt)
1294                 {
1295                     MMC->SRS08 = src_addr[word_cnt];
1296                     ++word_cnt;
1297                 }
1298 
1299                 /* Check is block write complete */
1300                 do
1301                 {
1302                     blk_write = MMC->SRS12;
1303                 } while (MMC_CLEAR == (blk_write & SRS12_TRANSFER_COMPLETE));
1304             }
1305 
1306             blk_tran_err = MMC->SRS12;
1307             /* Abort if any errors*/
1308             if ((SRS12_ERROR_STATUS_MASK & blk_tran_err) == MMC_CLEAR)
1309             {
1310                 /*
1311                 * Ensure no error fields in Card Status register are set and that
1312                 * the device is idle before this function returns.
1313                 */
1314                 do
1315                 {
1316                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
1317                                                 MMC_CMD_13_SEND_STATUS,
1318                                                 MSS_MMC_RESPONSE_R1);
1319                 } while (DEVICE_BUSY == response_status);
1320 
1321                 if (TRANSFER_IF_SUCCESS == response_status)
1322                 {
1323                     ret_status = MSS_MMC_TRANSFER_SUCCESS;
1324                 }
1325                 else
1326                 {
1327                     ret_status = MSS_MMC_DEVICE_ERROR;
1328                 }
1329             }
1330             else
1331             {
1332                 ret_status = MSS_MMC_ERR_INTERRUPT;
1333             }
1334             /* Clear all status interrupts except:
1335             *  current limit error, card interrupt, card removal, card insertion */
1336             MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
1337                                 | SRS12_CARD_INTERRUPT
1338                                 | SRS12_CARD_REMOVAL
1339                                 | SRS12_CARD_INSERTION);
1340         }
1341         else
1342         {
1343             ret_status = MSS_MMC_DEVICE_ERROR;
1344         }
1345     }
1346     else
1347     {
1348         ret_status = MSS_MMC_NOT_INITIALISED;
1349     }
1350     return (ret_status);
1351 }
1352 /*-------------------------------------------------------------------------*//**
1353  * See "mss_mmc.h" for details of how to use this function.
1354  */
1355 mss_mmc_status_t
MSS_MMC_sdma_write(const uint8_t * src,uint32_t dest,uint32_t size)1356 MSS_MMC_sdma_write
1357 (
1358     const uint8_t *src,
1359     uint32_t dest,
1360     uint32_t size
1361 )
1362 {
1363     uint32_t blockcount;
1364     uint32_t argument;
1365     uint32_t blocklen;
1366     uint32_t tmp, srs03_data, srs9;
1367     cif_response_t response_status;
1368     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1369 
1370     blocklen = BLK_SIZE;
1371     argument = dest;
1372 
1373     if (g_mmc_init_complete == MMC_SET)
1374     {
1375         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
1376         {
1377             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1378         }
1379         else
1380         {
1381             /* Size should be divided by 512, not greater than (32MB - 512) */
1382             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
1383                     || (size == MMC_CLEAR) || (src == NULL_POINTER))
1384             {
1385                 ret_status = MSS_MMC_INVALID_PARAMETER;
1386             }
1387             else
1388             {
1389                 /* Disable PLIC interrupt for MMC */
1390                 PLIC_DisableIRQ(MMC_main_PLIC);
1391                 /* Disable error/interrupt */
1392                 MMC->SRS14 = MMC_CLEAR;
1393                 /* Check eMMC/SD device is busy */
1394                 do
1395                 {
1396 
1397                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
1398                                                         MMC_CMD_13_SEND_STATUS,
1399                                                         MSS_MMC_RESPONSE_R1);
1400                 } while (DEVICE_BUSY == response_status);
1401 
1402                 if (TRANSFER_IF_SUCCESS == response_status)
1403                 {
1404                     /* Reset Data and cmd line */
1405                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1406                     mmc_delay(MASK_8BIT);
1407                     /* Calculate block count */
1408                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
1409                     /* Enable SDMA */
1410                     tmp = MMC->SRS10;
1411                     tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
1412                     MMC->SRS10 = (tmp | SRS10_DMA_SELECT_SDMA);
1413                     /* SDMA setup */
1414                     MMC->SRS22 = (uint32_t)(uintptr_t)src;
1415                     MMC->SRS23 = (uint32_t)(((uint64_t)(uintptr_t)src) >> MMC_64BIT_UPPER_ADDR_SHIFT);
1416                     /* Block length and count SDMA buffer boundary */
1417                     MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT) | SRS1_DMA_BUFF_SIZE_512KB);
1418                     /* Enable interrupts */
1419                     MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN |
1420                                     SRS14_TRANSFER_COMPLETE_SIG_EN |
1421                                     SRS14_DMA_INTERRUPT_SIG_EN |
1422                                     SRS14_DATA_TIMEOUT_ERR_SIG_EN);
1423                     /* Enable PLIC MMC interrupt */
1424                     PLIC_EnableIRQ(MMC_main_PLIC);
1425                     /* check data line busy */
1426                     do
1427                     {
1428                         srs9 = MMC->SRS09;
1429                     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1430                     /* Multi Block write */
1431                     if (blockcount > MMC_SET)
1432                     {
1433                         /* DPS, Data transfer direction - write */
1434                         srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE
1435                                                 | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
1436                                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1437                                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
1438                                                 | SRS3_DMA_ENABLE);
1439                         /* Multi block transfer */
1440                         g_mmc_is_multi_blk = MMC_SET;
1441 
1442                         MMC->SRS02 = argument;
1443                         /* Execute command */
1444                         MMC->SRS03 = (uint32_t)((MMC_CMD_25_WRITE_MULTI_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1445                     }
1446                     else /* Single block write */
1447                     {
1448                         /* DPS, Data transfer direction - write */
1449                         srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE
1450                                                 | SRS3_BLOCK_COUNT_ENABLE
1451                                                 | SRS3_RESPONSE_CHECK_TYPE_R1
1452                                                 | SRS3_RESP_LENGTH_48
1453                                                 | SRS3_CRC_CHECK_EN
1454                                                 | SRS3_INDEX_CHECK_EN
1455                                                 | SRS3_DMA_ENABLE);
1456                         /* Single block transfer */
1457                         g_mmc_is_multi_blk = MMC_CLEAR;
1458                         /* Execute command */
1459                         MMC->SRS02 = argument;
1460                         MMC->SRS03 = (uint32_t)((MMC_CMD_24_WRITE_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1461                     }
1462                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
1463                     ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1464                 }
1465                 else
1466                 {
1467                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
1468                     ret_status = MSS_MMC_DEVICE_ERROR;
1469                 }
1470             }
1471         }
1472     }
1473     else
1474     {
1475         ret_status = MSS_MMC_NOT_INITIALISED;
1476     }
1477     return ret_status;
1478 
1479 }
1480 /*-------------------------------------------------------------------------*//**
1481  * See "mss_mmc.h" for details of how to use this function.
1482  */
1483 mss_mmc_status_t
MSS_MMC_adma2_write(const uint8_t * src,uint32_t dest,uint32_t size)1484 MSS_MMC_adma2_write
1485 (
1486     const uint8_t *src,
1487     uint32_t dest,
1488     uint32_t size
1489 )
1490 {
1491     uint32_t blockcount;
1492     uint32_t argument;
1493     uint32_t blocklen;
1494     uint32_t tmp, srs03_data, srs9;
1495     cif_response_t response_status;
1496     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1497 
1498     blocklen = BLK_SIZE;
1499     argument = dest;
1500 
1501     if (g_mmc_init_complete == MMC_SET)
1502     {
1503         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
1504         {
1505             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1506         }
1507         else
1508         {
1509             /* Size should be divided by 512, not greater than (32MB - 512) */
1510             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
1511                     || (size == MMC_CLEAR) || (src == NULL_POINTER))
1512             {
1513                 ret_status = MSS_MMC_INVALID_PARAMETER;
1514             }
1515             else
1516             {
1517                 /* Disable PCLI interrupt for MMC */
1518                 PLIC_DisableIRQ(MMC_main_PLIC);
1519                 /* Disable error/interrupt */
1520                 MMC->SRS14 = MMC_CLEAR;
1521                 /* Check eMMC/SD device is busy */
1522                 do
1523                 {
1524                     response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
1525                                                 MMC_CMD_13_SEND_STATUS,
1526                                                 MSS_MMC_RESPONSE_R1);
1527                 } while (DEVICE_BUSY == response_status);
1528 
1529                 if (TRANSFER_IF_SUCCESS == response_status)
1530                 {
1531                     /* Reset Data and cmd line */
1532                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1533                     mmc_delay(MASK_8BIT);
1534                     /* Calculate block count */
1535                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
1536                     /* ADMA2 table create */
1537                     ret_status = adma2_create_descriptor_table(src, size);
1538                     if (ret_status != MSS_MMC_INVALID_PARAMETER)
1539                     {
1540                         /* ADMA setup */
1541                         MMC->SRS22 = (uint32_t)(uintptr_t)adma_descriptor_table;
1542                         MMC->SRS23 = (uint32_t)(((uint64_t)(uintptr_t)adma_descriptor_table) >> MMC_64BIT_UPPER_ADDR_SHIFT);
1543                         tmp = MMC->SRS10;
1544                         tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
1545                         MMC->SRS10 = (tmp | SRS10_DMA_SELECT_ADMA2);
1546                         /* Block length and count */
1547                         MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT));
1548                         /* enable interrupts */
1549                         MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN | SRS14_TRANSFER_COMPLETE_SIG_EN
1550                                             | SRS14_DATA_TIMEOUT_ERR_SIG_EN | SRS14_ADMA_ERROR_SIG_EN);
1551                         PLIC_EnableIRQ(MMC_main_PLIC);
1552                         /* Check data line busy */
1553                         do
1554                         {
1555                             srs9 = MMC->SRS09;
1556                         }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1557                         /* Multi Block write */
1558                         if (blockcount > MMC_SET)
1559                         {
1560                             /* DPS, Data transfer direction - write */
1561                             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE
1562                                                 | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
1563                                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1564                                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
1565                                                 | SRS3_DMA_ENABLE);
1566                             /* Multi block transfer */
1567                             g_mmc_is_multi_blk = MMC_SET;
1568                             MMC->SRS02 = argument;
1569                             /* Execute command */
1570                             MMC->SRS03 = (uint32_t)((MMC_CMD_25_WRITE_MULTI_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1571                         }
1572                         else /* Single block write */
1573                         {
1574                             /* DPS, Data transfer direction - write */
1575                             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE | SRS3_BLOCK_COUNT_ENABLE
1576                                                 | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
1577                                                 | SRS3_CRC_CHECK_EN| SRS3_INDEX_CHECK_EN
1578                                                 | SRS3_DMA_ENABLE);
1579                             /* Single block transfer */
1580                             g_mmc_is_multi_blk = MMC_CLEAR;
1581                             /* Execute command */
1582                             MMC->SRS02 = argument;
1583                             MMC->SRS03 = (uint32_t)((MMC_CMD_24_WRITE_SINGLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1584                         }
1585                         g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
1586                         ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1587                     }
1588                 }
1589                 else
1590                 {
1591                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
1592                     ret_status = MSS_MMC_DEVICE_ERROR;
1593                 }
1594             }
1595         }
1596     }
1597     else
1598     {
1599         ret_status = MSS_MMC_NOT_INITIALISED;
1600     }
1601     return ret_status;
1602 }
1603 /*-------------------------------------------------------------------------*//**
1604  * See "mss_mmc.h" for details of how to use this function.
1605  */
MSS_MMC_sdio_single_block_write(const uint32_t * src_addr,uint32_t dst_addr,uint16_t data_size)1606 mss_mmc_status_t MSS_MMC_sdio_single_block_write
1607 (
1608     const uint32_t * src_addr,
1609     uint32_t dst_addr,
1610     uint16_t data_size
1611 )
1612 {
1613     uint16_t word_cnt = MMC_CLEAR;
1614     uint8_t blk_tran_err;
1615     uint8_t blk_write;
1616     uint16_t blk_size = (data_size/WORD_SIZE);
1617     uint32_t srs03_data, srs9;
1618     uint32_t arguement;
1619     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1620 
1621     if (g_mmc_init_complete == MMC_SET)
1622     {
1623         if ((data_size != MMC_CLEAR) && (data_size <= BLK_SIZE)
1624             && (src_addr != NULL_POINTER))
1625         {
1626             sdio_host_access_fbr(SDIOHOST_CCCR_WRITE, &dst_addr, BYTES_3,
1627                                         MSS_MMC_FBR_ADDR_CSA, MMC_SET, MMC_CLEAR);
1628             /* Reset Data and cmd line */
1629             MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
1630             mmc_delay(MASK_8BIT);
1631             /* Block length and count*/
1632             MMC->SRS01 = (data_size | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
1633 
1634             /* DPS, Data transfer direction - read */
1635             srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE |SRS3_BLOCK_COUNT_ENABLE
1636                             | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
1637                             | SRS3_RESPONSE_CHECK_TYPE_R5 | SRS3_RESP_LENGTH_48
1638                             | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
1639             /* Check cmd and data line busy */
1640             do
1641             {
1642                 srs9 = MMC->SRS09;
1643             }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
1644 
1645             if (data_size == BLK_SIZE)
1646             {
1647                 data_size = MMC_CLEAR;
1648             }
1649 
1650             arguement = SDIO_WRITE | (SDIO_CSA_REG_ADDR << SHIFT_9BIT)
1651                                             | SDIO_OPCODE_INC | data_size;
1652             /* Command argument */
1653             MMC->SRS02 = arguement;
1654             /* Execute command */
1655             MMC->SRS03 = (uint32_t)((SDIO_CMD_53_IO_RW_EXTENDED << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
1656 
1657             do
1658             {
1659                 blk_write = MMC->SRS12;
1660             }while (MMC_CLEAR == (blk_write & (SRS12_BUFFER_WRITE_READY | SRS12_ERROR_INTERRUPT)));
1661             /*
1662             * Load the block of data into the
1663             * buffer, four bytes at a time through the Buffer Data Register.
1664             */
1665             if ((blk_write & SRS12_BUFFER_WRITE_READY) != MMC_CLEAR)
1666             {
1667                 while (blk_size > word_cnt)
1668                 {
1669                     MMC->SRS08 = src_addr[word_cnt];
1670                     ++word_cnt;
1671                 }
1672                 /* Check is block write complete */
1673                 do
1674                 {
1675                     blk_write = MMC->SRS12;
1676                 }while (MMC_CLEAR == (blk_write & SRS12_TRANSFER_COMPLETE));
1677             }
1678             blk_tran_err = MMC->SRS12;
1679             /* Abort if any errors*/
1680             if ((SRS12_ERROR_STATUS_MASK & blk_tran_err) == MMC_CLEAR)
1681             {
1682                 ret_status = MSS_MMC_TRANSFER_SUCCESS;
1683             }
1684             else
1685             {
1686                 ret_status = MSS_MMC_ERR_INTERRUPT;
1687             }
1688             MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
1689                                 | SRS12_CARD_INTERRUPT
1690                                 | SRS12_CARD_REMOVAL
1691                                 | SRS12_CARD_INSERTION);
1692         }
1693         else
1694         {
1695             ret_status = MSS_MMC_INVALID_PARAMETER;
1696         }
1697     }
1698     else
1699     {
1700         ret_status = MSS_MMC_NOT_INITIALISED;
1701     }
1702     return (ret_status);
1703 }
1704 
1705 /*-------------------------------------------------------------------------*//**
1706  * See "mss_mmc.h" for details of how to use this function.
1707  */
MSS_MMC_get_transfer_status(void)1708 mss_mmc_status_t MSS_MMC_get_transfer_status(void)
1709 {
1710     return g_mmc_trs_status.state;
1711 }
1712 /*-------------------------------------------------------------------------*//**
1713  * See "mss_mmc.h" for details of how to use this function.
1714  */
MSS_MMC_set_handler(mss_mmc_handler_t handler)1715 void MSS_MMC_set_handler( mss_mmc_handler_t handler)
1716 {
1717     g_transfer_complete_handler_t = handler;
1718 }
1719 /*-------------------------------------------------------------------------*//**
1720  * See "mss_mmc.h" for details of how to use this function.
1721  */
MSS_MMC_cq_init(void)1722 mss_mmc_status_t MSS_MMC_cq_init(void)
1723 {
1724     uint32_t csd_reg[BLK_SIZE/WORD_SIZE];
1725     uint8_t  *pcsd_reg;
1726     uint64_t desc_addr64;
1727     uint32_t reg;
1728     uint8_t  hw_cq_mode_en;
1729     uint8_t  hw_cq_depth;
1730     uint8_t  hw_cq_support;
1731     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1732     cif_response_t response_status;
1733     static uint8_t g_cq_task_desc[SIZE_4KB];
1734 
1735     g_mmc_cq_init_complete = MMC_CLEAR;
1736 
1737     if (g_mmc_init_complete == MMC_SET)
1738     {
1739         /* Task descriptor size configuration */
1740         reg = MMC->CQRS02;
1741         reg &= ~(uint32_t)CQRS02_TASK_DESCRIPTOR_SIZE_MASK;
1742         reg |= (uint32_t)CQRS02_TASK_DESCRIPTOR_SIZE_128;
1743         MMC->CQRS02 = reg;
1744 
1745         g_desc_addr = (uint8_t *)g_cq_task_desc;
1746 
1747         if (((uintptr_t)g_desc_addr & CQ_TDLBA_ALIGN_MASK) != MMC_CLEAR)
1748         {
1749             g_desc_addr += (CQ_TDLBA_ALIGN_MASK + MMC_SET) - ((uintptr_t)g_desc_addr & CQ_TDLBA_ALIGN_MASK);
1750         }
1751         /* Task Descriptor List address configuration */
1752         desc_addr64 = (uintptr_t)g_desc_addr;
1753         MMC->CQRS08 = (uint32_t)(desc_addr64 & MASK_32BIT);
1754         MMC->CQRS09 = (uint32_t)((desc_addr64 >> SHIFT_32BIT) & MASK_32BIT);
1755 
1756         ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
1757         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
1758         {
1759             pcsd_reg = (uint8_t *)csd_reg;
1760             /* Offsets defined in JESD84-B51 extended CSD */
1761             hw_cq_mode_en = pcsd_reg[EXT_CSD_CQ_MODE_EN_OFFSET];
1762             hw_cq_depth = pcsd_reg[EXT_CSD_CQ_DEPTH_OFFSET] + MMC_SET;
1763             hw_cq_support = pcsd_reg[EXT_CSD_CQ_SUPPORT_OFFSET];
1764 
1765             if (hw_cq_support == MMC_SET)
1766             {
1767                 /* Enable CQ mode in the device */
1768                 response_status = cif_send_cmd(MMC_CQ_ENABLE,
1769                                             MMC_CMD_6_SWITCH,
1770                                             MSS_MMC_RESPONSE_R1B);
1771 
1772                 if (TRANSFER_IF_FAIL != response_status)
1773                 {
1774                     response_status = check_device_status(response_status);
1775                 }
1776 
1777                 if (TRANSFER_IF_SUCCESS == response_status)
1778                 {
1779                     /* Check device is enabled with CQ or not */
1780                     ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
1781                     if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
1782                     {
1783                         pcsd_reg = (uint8_t *)csd_reg;
1784                         hw_cq_mode_en = pcsd_reg[EXT_CSD_CQ_MODE_EN_OFFSET];
1785                         if (MMC_SET == hw_cq_mode_en)
1786                         {
1787                             /* Enable CQ in Host controller */
1788                             /* Set blk count and idle timer */
1789                             MMC->CQRS16 = (MMC_SET << SHIFT_16BIT) |(CQ_IDLE_TIME);
1790                             /* enable signaling command queuing interrupts */
1791                             reg = (uint32_t)(CQRS05_TASK_CLEARED_STAT_EN
1792                                                     | CQRS05_RESP_ERR_STAT_EN
1793                                                     | CQRS05_TASK_COMPLETE_STAT_EN);
1794                             MMC->CQRS05 = reg;
1795                             /* Clear all interrupts */
1796                             MMC->CQRS04 = MASK_32BIT;
1797                             /* Set 16-bit RCA value which is send as an argument in SEND_QUEUE_STATUS */
1798                             MMC->CQRS17 = sdcard_RCA;
1799                             /* Enable command queuing engine in SD host controller */
1800                             reg = MMC->CQRS02;
1801                             reg |= (uint32_t)CQRS02_COMMAND_QUEUING_ENABLE;
1802                             MMC->CQRS02 = reg;
1803                             /* Enable task complete interrupt */
1804                             reg = (uint32_t)(CQRS06_TASK_COMPLETE_INT_SIG_EN | CQRS06_RESP_ERR_INT_SIG_EN);
1805                             MMC->CQRS06 = reg;
1806                             /* Check device CQ status */
1807                             do
1808                             {
1809                                 response_status = cif_send_cq_direct_command(g_desc_addr,
1810                                                                 sdcard_RCA,
1811                                                             MMC_CMD_13_SEND_STATUS,
1812                                                             MSS_MMC_RESPONSE_R1,
1813                                                             CQ_DCMD_TASK_ID);
1814                             }while (DEVICE_BUSY == response_status);
1815 
1816                             if (TRANSFER_IF_SUCCESS == response_status)
1817                             {
1818                                 g_mmc_cq_init_complete = MMC_SET;
1819                                 ret_status = MSS_MMC_INIT_SUCCESS;
1820                             }
1821                             else
1822                             {
1823                                 g_mmc_cq_init_complete = MMC_CLEAR;
1824                                 ret_status = MSS_MMC_CQ_INIT_FAILURE;
1825                             }
1826                         }
1827                         else
1828                         {
1829                             ret_status = MSS_MMC_CQ_INIT_FAILURE;
1830                         }
1831                     }
1832                 }
1833                 else
1834                 {
1835                     ret_status = MSS_MMC_CQ_INIT_FAILURE;
1836                 }
1837             }
1838             else
1839             {
1840                 ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_CQ;
1841             }
1842         }
1843         else
1844         {
1845             ret_status = MSS_MMC_CQ_INIT_FAILURE;
1846         }
1847     }
1848     else
1849     {
1850         ret_status = MSS_MMC_CQ_INIT_FAILURE;
1851     }
1852     return ret_status;
1853 }
1854 /*-------------------------------------------------------------------------*//**
1855  * See "mss_mmc.h" for details of how to use this function.
1856  */
1857 mss_mmc_status_t
MSS_MMC_cq_write(const uint8_t * src,uint32_t dest,uint32_t size)1858 MSS_MMC_cq_write
1859 (
1860     const uint8_t *src,
1861     uint32_t dest,
1862     uint32_t size
1863 )
1864 {
1865     uint32_t reg;
1866     uint32_t *dcmdTaskDesc = NULL_POINTER;
1867     uint32_t flags;
1868     uint32_t desc_offset;
1869     uint32_t cmd_response;
1870     uint32_t blockcount;
1871     uint32_t argument;
1872     uint32_t blocklen;
1873     uint32_t blk_cnt;
1874     uint8_t task_id;
1875     uint32_t trans_size;
1876     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
1877     cif_response_t response_status;
1878 
1879     blocklen = BLK_SIZE;
1880     argument = dest;
1881     trans_size = size;
1882 
1883     if (g_mmc_cq_init_complete == MMC_SET)
1884     {
1885         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
1886         {
1887             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1888         }
1889         else
1890         {
1891             /* Size should be divided by 512, not greater than (1GB - 16KB) */
1892             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_1GB - (CQ_HOST_NUMBER_OF_TASKS * BLK_SIZE)))
1893                     || (size == MMC_CLEAR) || (src == NULL_POINTER))
1894             {
1895                 ret_status = MSS_MMC_INVALID_PARAMETER;
1896             }
1897             else
1898             {
1899                 /* Disable PCLI interrupt for MMC */
1900                 PLIC_DisableIRQ(MMC_main_PLIC);
1901                 /* Disable error/interrupt */
1902                 MMC->SRS14 = MMC_CLEAR;
1903                 /* Check MMC device is busy */
1904                 do
1905                 {
1906                     response_status = cif_send_cq_direct_command(g_desc_addr,
1907                                                     sdcard_RCA,
1908                                                     MMC_CMD_13_SEND_STATUS,
1909                                                     MSS_MMC_RESPONSE_R1,
1910                                                     CQ_DCMD_TASK_ID);
1911                 } while (DEVICE_BUSY == response_status);
1912 
1913                 if (TRANSFER_IF_SUCCESS == response_status)
1914                 {
1915                     /* Calculate block count */
1916                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
1917                     reg = MMC_CLEAR;
1918                     for(task_id = MMC_CLEAR; ((task_id < CQ_HOST_NUMBER_OF_TASKS) && (blockcount != MMC_CLEAR)); ++task_id)
1919                     {
1920                         desc_offset = CQ_HOST_NUMBER_OF_TASKS * task_id;
1921                         dcmdTaskDesc = (uint32_t *)(g_desc_addr + desc_offset);
1922 
1923                         flags = (uint32_t)(CQ_DESC_VALID |  CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT);
1924                         flags |= CQ_DESC_SET_CONTEXT_ID(MMC_SET) | CQ_DESC_DATA_DIR_WRITE;
1925 
1926                         if (blockcount > MASK_16BIT)
1927                         {
1928                             blk_cnt = MASK_16BIT;
1929                             blockcount = blockcount - MASK_16BIT;
1930                         }
1931                         else
1932                         {
1933                             blk_cnt = blockcount;
1934                             blockcount = MMC_CLEAR;
1935                         }
1936 
1937                         dcmdTaskDesc[MMC_CLEAR] = flags | (blk_cnt << SHIFT_16BIT);
1938                         dcmdTaskDesc[BYTES_1] = argument;
1939                         dcmdTaskDesc[BYTES_2] = MMC_CLEAR;
1940                         dcmdTaskDesc[BYTES_3] = MMC_CLEAR;
1941 
1942                         if (trans_size > MASK_16BIT)
1943                         {
1944                             /* Data buffer size is 64KB */
1945                             size = MMC_CLEAR;
1946                         }
1947                         else
1948                         {
1949                             size = trans_size;
1950                         }
1951                         /* Supports only 64KB */
1952                         dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN |  CQ_DESC_END) | (size << SHIFT_16BIT));
1953                         /* Data buffer address in host memory, lower part */
1954                         dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)src;
1955                         /* Data buffer address in host memory, higher part */
1956                         dcmdTaskDesc[BYTES_6] = (uint32_t)(((uint64_t)(uintptr_t)src) >> MMC_64BIT_UPPER_ADDR_SHIFT);
1957                         dcmdTaskDesc[BYTES_7] = MMC_CLEAR;
1958 
1959                         if (trans_size > (SIZE_32MB - BLK_SIZE))
1960                         {
1961                             trans_size = trans_size - (SIZE_32MB - BLK_SIZE);
1962                             src = src + (SIZE_32MB - - BLK_SIZE);
1963                             argument = argument + blockcount;
1964                         }
1965                         reg |= (MMC_SET << task_id);
1966                     }
1967 
1968                     g_cq_task_id = task_id;
1969                     /* Enable interrupts */
1970                     MMC->SRS14 = (SRS14_CMD_QUEUING_SIG_EN | SRS14_COMMAND_TIMEOUT_ERR_SIG_EN
1971                                         | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
1972                     PLIC_EnableIRQ(MMC_main_PLIC);
1973                     /* Set doorbell to start processing descriptors by controller */
1974                     MMC->CQRS10 = reg;
1975 
1976                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
1977                     ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
1978                 }
1979                 else
1980                 {
1981                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
1982                     ret_status = MSS_MMC_DEVICE_ERROR;
1983                 }
1984             }
1985         }
1986     }
1987     else
1988     {
1989         ret_status = MSS_MMC_CQ_NOT_INITIALISED;
1990     }
1991     return ret_status;
1992 }
1993 /*-------------------------------------------------------------------------*//**
1994  * See "mss_mmc.h" for details of how to use this function.
1995  */
1996 mss_mmc_status_t
MSS_MMC_cq_read(uint32_t src,uint8_t * dest,uint32_t size)1997 MSS_MMC_cq_read
1998 (
1999     uint32_t src,
2000     uint8_t *dest,
2001     uint32_t size
2002 )
2003 {
2004     uint32_t reg;
2005     uint32_t *dcmdTaskDesc = NULL_POINTER;
2006     uint32_t flags;
2007     uint32_t desc_offset;
2008     uint32_t cmd_response;
2009     uint32_t blockcount;
2010     uint32_t argument;
2011     uint32_t blocklen;
2012     uint32_t blk_cnt;
2013     uint8_t task_id;
2014     uint32_t trans_size;
2015     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2016     cif_response_t response_status;
2017 
2018     blocklen = BLK_SIZE;
2019     argument = src;
2020     trans_size = size;
2021 
2022     if (g_mmc_cq_init_complete == MMC_SET)
2023     {
2024        if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2025        {
2026            ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2027        }
2028        else
2029        {
2030             /* Size should be divided by 512, not greater than (1GB - 16KB) */
2031             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_1GB - (CQ_HOST_NUMBER_OF_TASKS * BLK_SIZE)))
2032                     || (size == MMC_CLEAR) || (dest == NULL_POINTER))
2033             {
2034                 ret_status = MSS_MMC_INVALID_PARAMETER;
2035             }
2036             else
2037             {
2038                 /* Disable PCLI interrupt for MMC */
2039                 PLIC_DisableIRQ(MMC_main_PLIC);
2040                 /* Disable error/interrupt */
2041                 MMC->SRS14 = MMC_CLEAR;
2042                 /* Check MMC device is busy */
2043                 do
2044                 {
2045                    response_status = cif_send_cq_direct_command(g_desc_addr,
2046                                                        sdcard_RCA,
2047                                                        MMC_CMD_13_SEND_STATUS,
2048                                                        MSS_MMC_RESPONSE_R1,
2049                                                        CQ_DCMD_TASK_ID);
2050                 } while (DEVICE_BUSY == response_status);
2051 
2052                 if (TRANSFER_IF_SUCCESS == response_status)
2053                 {
2054                     reg = MMC_CLEAR;
2055                     /* Calculate block count */
2056                     blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
2057                     for(task_id = MMC_CLEAR; ((task_id < CQ_HOST_NUMBER_OF_TASKS) && (blockcount != MMC_CLEAR)); ++task_id)
2058                     {
2059                         desc_offset = CQ_HOST_NUMBER_OF_TASKS * task_id;
2060                         dcmdTaskDesc = (uint32_t *)(g_desc_addr + desc_offset);
2061 
2062                         flags = (uint32_t)(CQ_DESC_VALID |  CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT);
2063                         flags |= CQ_DESC_SET_CONTEXT_ID(MMC_CLEAR) | CQ_DESC_DATA_DIR_READ;
2064 
2065                         if (blockcount > MASK_16BIT)
2066                         {
2067                             blk_cnt = MASK_16BIT;
2068                             blockcount = blockcount - MASK_16BIT;
2069                         }
2070                         else
2071                         {
2072                             blk_cnt = blockcount;
2073                             blockcount = MMC_CLEAR;
2074                         }
2075                         dcmdTaskDesc[MMC_CLEAR] = flags | (blk_cnt << SHIFT_16BIT);
2076                         dcmdTaskDesc[BYTES_1] = argument;
2077                         dcmdTaskDesc[BYTES_2] = MMC_CLEAR;
2078                         dcmdTaskDesc[BYTES_3] = MMC_CLEAR;
2079 
2080                         if (trans_size > MASK_16BIT)
2081                         {
2082                             /* Data buffer size is 64KB */
2083                             size = MMC_CLEAR;
2084                         }
2085                         else
2086                         {
2087                             size = trans_size;
2088                         }
2089                         /* Supports only 64KB */
2090                         dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN |  CQ_DESC_END) | (size << SHIFT_16BIT));
2091                         /* Data buffer address in host memory, lower part */
2092                         dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)dest;
2093                         /* Data buffer address in host memory, higher part */
2094                         dcmdTaskDesc[BYTES_6] = (uint32_t)(((uint64_t)(uintptr_t)dest) >> MMC_64BIT_UPPER_ADDR_SHIFT);
2095                         dcmdTaskDesc[BYTES_7] = MMC_CLEAR;
2096 
2097                         if (trans_size > (SIZE_32MB - BLK_SIZE))
2098                         {
2099                             trans_size = trans_size - (SIZE_32MB - BLK_SIZE);
2100                             src = src + (SIZE_32MB - - BLK_SIZE);
2101                             argument = argument + blockcount;
2102                         }
2103                         reg |= (MMC_SET << task_id);
2104                     }
2105 
2106                     g_cq_task_id = task_id;
2107                     /* Enable interrupts */
2108                     MMC->SRS14 = (SRS14_CMD_QUEUING_SIG_EN | SRS14_COMMAND_TIMEOUT_ERR_SIG_EN
2109                                         | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
2110                     PLIC_EnableIRQ(MMC_main_PLIC);
2111                     /* Set doorbell to start processing descriptors by controller */
2112                     MMC->CQRS10 = reg;
2113 
2114                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
2115                     ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2116                 }
2117                 else
2118                 {
2119                     g_mmc_trs_status.state = MSS_MMC_DEVICE_ERROR;
2120                     ret_status = MSS_MMC_DEVICE_ERROR;
2121                 }
2122             }
2123         }
2124     }
2125     else
2126     {
2127         ret_status = MSS_MMC_CQ_NOT_INITIALISED;
2128     }
2129     return ret_status;
2130 }
2131 
2132 /******************************************************************************
2133   MMC ISR
2134 *******************************************************************************/
mmc_main_plic_IRQHandler(void)2135 uint8_t  mmc_main_plic_IRQHandler(void)
2136 {
2137     uint32_t trans_status_isr;
2138     uint32_t response_reg, inttoclear;
2139     uintptr_t address;
2140     uintptr_t highaddr;
2141     uint64_t address64;
2142     static uint8_t transfer_complete  = MMC_CLEAR;
2143 
2144     trans_status_isr = MMC->SRS12;
2145 
2146     /* Error interrupt */
2147     if ((trans_status_isr & SRS12_ERROR_INTERRUPT) != MMC_CLEAR)
2148     {
2149         MMC->SRS12 = trans_status_isr;
2150         MMC->SRS14 = MMC_CLEAR;
2151         g_mmc_trs_status.state = MSS_MMC_TRANSFER_FAIL;
2152         if (g_transfer_complete_handler_t != NULL_POINTER)
2153         {
2154             g_transfer_complete_handler_t(trans_status_isr);
2155         }
2156     }
2157     /* Command completion */
2158     else if ((trans_status_isr & SRS12_COMMAND_COMPLETE) != MMC_CLEAR)
2159     {
2160         MMC->SRS12 = SRS12_COMMAND_COMPLETE;
2161         response_reg = MMC->SRS04;
2162         if ((response_reg & CARD_STATUS_ALL_ERRORS_MASK) != MMC_CLEAR)
2163         {
2164             /* Disable interrupts */
2165             MMC->SRS14 = MMC_CLEAR;
2166             g_mmc_trs_status.state = MSS_MMC_RESPONSE_ERROR;
2167         }
2168         /* Stop command success */
2169         if (transfer_complete == MMC_SET)
2170         {
2171             /* Disable interrupts */
2172             MMC->SRS14 = MMC_CLEAR;
2173             g_mmc_trs_status.state = MSS_MMC_TRANSFER_SUCCESS;
2174             transfer_complete = MMC_CLEAR;
2175 
2176             if (g_transfer_complete_handler_t != NULL_POINTER)
2177             {
2178                 g_transfer_complete_handler_t(trans_status_isr);
2179             }
2180         }
2181     }
2182     /* Transfer Completion */
2183     else if ((trans_status_isr & SRS12_TRANSFER_COMPLETE) != MMC_CLEAR)
2184     {
2185         MMC->SRS12 = trans_status_isr;
2186 
2187         if (g_mmc_is_multi_blk == MMC_CLEAR)
2188         {
2189             /* Disable interrupts */
2190             MMC->SRS14 = MMC_CLEAR;
2191             g_mmc_trs_status.state = MSS_MMC_TRANSFER_SUCCESS;
2192             transfer_complete = MMC_CLEAR;
2193             if (g_transfer_complete_handler_t != NULL_POINTER)
2194             {
2195                 g_transfer_complete_handler_t(trans_status_isr);
2196             }
2197         }
2198         else
2199         {
2200             /* Multi block transfer */
2201             transfer_complete = MMC_SET;
2202             send_mmc_cmd(sdcard_RCA << SHIFT_16BIT, MMC_CMD_12_STOP_TRANSMISSION,
2203                                     MSS_MMC_RESPONSE_R1, CHECK_IF_CMD_SENT_INT);
2204         }
2205     }
2206     /* DMA interrupt */
2207     else if ((trans_status_isr & SRS12_DMA_INTERRUPT) != MMC_CLEAR)
2208     {
2209         address = MMC->SRS22;
2210         highaddr = MMC->SRS23;
2211 
2212         address64 = address | ((uint64_t)highaddr << MMC_64BIT_UPPER_ADDR_SHIFT);
2213         /* Increase address(512kb) and re-write new address in DMA buffer */
2214         address = (uint32_t)address64;
2215         highaddr = (uint32_t)(address64 >> MMC_64BIT_UPPER_ADDR_SHIFT);
2216 
2217         MMC->SRS22 = address;
2218         MMC->SRS23 = highaddr;
2219         MMC->SRS12 = SRS12_DMA_INTERRUPT;
2220     }
2221     else if ((trans_status_isr & SRS12_CMD_QUEUING_INT) != MMC_CLEAR)
2222     {
2223         MMC->SRS12 = trans_status_isr;
2224         inttoclear = MMC->CQRS04;
2225         MMC->CQRS04 = inttoclear;
2226 
2227         if ((inttoclear & CQRS04_RESP_ERR_INT) != MMC_CLEAR)
2228         {
2229             /* Disable interrupts */
2230             MMC->SRS14 = MMC_CLEAR;
2231            g_mmc_trs_status.state = MSS_MMC_TRANSFER_FAIL;
2232         }
2233 
2234         if ((inttoclear & CQRS04_TASK_COMPLETE_INT) != MMC_CLEAR)
2235         {
2236             inttoclear = MMC->CQRS11;
2237             /* Clear all caught notifications */
2238             MMC->CQRS11 = inttoclear;
2239             --g_cq_task_id;
2240             if (g_cq_task_id == MMC_CLEAR)
2241             {
2242                 /* Disable interrupts */
2243                 MMC->SRS14 = MMC_CLEAR;
2244                 g_mmc_trs_status.state = MSS_MMC_TRANSFER_SUCCESS;
2245                 if (g_transfer_complete_handler_t != NULL_POINTER)
2246                 {
2247                     g_transfer_complete_handler_t(trans_status_isr);
2248                 }
2249             }
2250         }
2251     }
2252     else
2253     {
2254         MMC->SRS12 = trans_status_isr;
2255         /* Disable interrupts */
2256         MMC->SRS14 = MMC_CLEAR;
2257     }
2258     return MMC_CLEAR;
2259 }
2260 
2261 #ifdef MSS_MMC_INTERNAL_APIS
2262 /*-------------------------------------------------------------------------*//**
2263  * See "mss_mmc_internal_test.h" for details of how to use this function.
2264  */
2265 mss_mmc_status_t
MSS_MMC_pause_sdma_write_hpi(const uint8_t * src,uint32_t dest,uint32_t size)2266 MSS_MMC_pause_sdma_write_hpi
2267 (
2268     const uint8_t *src,
2269     uint32_t dest,
2270     uint32_t size
2271 )
2272 {
2273     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2274     cif_response_t response_status;
2275     uint32_t command_information;
2276     uint32_t trans_status_isr, response;
2277     uint32_t total_sectors = size/BLK_SIZE;
2278     uint32_t remaining_sectors;
2279     uint32_t csd_reg[BLK_SIZE/WORD_SIZE];
2280     uint8_t  *pcsd_reg;
2281     uint32_t prog_sector_num = MMC_CLEAR;
2282 
2283     g_device_hpi_set = MMC_CLEAR;
2284 
2285     if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2286     {
2287         if ((g_device_hpi_suport & DEVICE_HPI_SUPPORT) == DEVICE_HPI_SUPPORT)
2288         {
2289             /* Disable PLIC interrupt for MMC */
2290             PLIC_DisableIRQ(MMC_main_PLIC);
2291             MMC->SRS14 = MMC_CLEAR;
2292             if ((g_device_hpi_suport & HPI_WITH_CMD12_SUPPORT) != MMC_CLEAR)
2293             {
2294 
2295                 response_status = cif_send_cmd((uint32_t)((sdcard_RCA << RCA_SHIFT_BIT) | DEVICE_HPI_SUPPORT),
2296                                         MMC_CMD_12_STOP_TRANSMISSION,
2297                                         MSS_MMC_RESPONSE_R1B);
2298             }
2299             else
2300             {
2301                 response_status = cif_send_cmd((uint32_t)((sdcard_RCA << RCA_SHIFT_BIT) | DEVICE_HPI_SUPPORT),
2302                                         MMC_CMD_13_SEND_STATUS,
2303                                         MSS_MMC_RESPONSE_R1);
2304                 do
2305                 {
2306                     response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
2307                                             MMC_CMD_13_SEND_STATUS,
2308                                             MSS_MMC_RESPONSE_R1);
2309                 }while (DEVICE_BUSY == response_status);
2310 
2311                 response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
2312                                         MMC_CMD_12_STOP_TRANSMISSION,
2313                                         MSS_MMC_RESPONSE_R1B);
2314             }
2315 
2316             if (TRANSFER_IF_FAIL != response_status)
2317             {
2318                 response_status = check_device_status(response_status);
2319             }
2320 
2321             if (TRANSFER_IF_SUCCESS == response_status)
2322             {
2323                 do
2324                 {
2325                     command_information = (uint32_t)(SRS3_ABORT_CMD | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
2326                                 | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
2327                     MMC->SRS02 = (sdcard_RCA << RCA_SHIFT_BIT) | DEVICE_HPI_SUPPORT;
2328                     MMC->SRS03 = (uint32_t)((MMC_CMD_13_SEND_STATUS << CMD_SHIFT) | command_information);
2329 
2330                     do
2331                     {
2332                         trans_status_isr = MMC->SRS12;
2333                     }while (((SRS12_COMMAND_COMPLETE | SRS12_ERROR_INTERRUPT) & trans_status_isr) == MMC_CLEAR);
2334 
2335                     if (SRS12_COMMAND_COMPLETE == (trans_status_isr & SRS12_COMMAND_COMPLETE))
2336                     {
2337                         /* If the response is an R1/B response */
2338                         response = MMC->SRS04;
2339                         if ((CARD_STATUS_ALL_ERRORS_MASK & response) == MMC_CLEAR) /* no error */
2340                         {
2341                             if ((CARD_STATUS_READY_FOR_DATA & response) != MMC_CLEAR)
2342                             {
2343                                 response_status = TRANSFER_IF_SUCCESS;
2344                             }
2345                             else
2346                             {
2347                                 response_status = DEVICE_BUSY;
2348                             }
2349                         }
2350                         else if (SRS12_ERROR_INTERRUPT == (SRS12_ERROR_INTERRUPT & trans_status_isr))
2351                         {
2352                             response_status = TRANSFER_IF_FAIL;
2353                         }
2354                         else
2355                         {
2356                             response_status = TRANSFER_IF_FAIL;
2357                         }
2358                     }
2359                 }while (response_status == DEVICE_BUSY);
2360 
2361                 if (TRANSFER_IF_SUCCESS == response_status)
2362                 {
2363                     ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
2364                     if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
2365                     {
2366                         pcsd_reg = (uint8_t *)csd_reg;
2367                         prog_sector_num = (uint32_t)(pcsd_reg[245] << SHIFT_24BIT);
2368                         prog_sector_num |= (uint32_t)(pcsd_reg[244] << SHIFT_16BIT);
2369                         prog_sector_num |= (uint32_t)(pcsd_reg[243] << SHIFT_8BIT);
2370                         prog_sector_num |= (uint32_t)pcsd_reg[242];
2371 
2372                         remaining_sectors = total_sectors - prog_sector_num;
2373 
2374                         g_trans_remain_size = remaining_sectors * BLK_SIZE;
2375                         g_trans_dest_addr = (dest + total_sectors) - remaining_sectors;
2376                         g_trans_src_addr = (uint8_t *)(src + (prog_sector_num * BLK_SIZE));
2377 
2378                         g_device_hpi_set = MMC_SET;
2379                     }
2380                     else
2381                     {
2382                         ret_status = MSS_MMC_TRANSFER_FAIL;
2383                     }
2384                 }
2385                 else
2386                 {
2387                     ret_status = MSS_MMC_TRANSFER_FAIL;
2388                 }
2389             }
2390             else
2391             {
2392                 ret_status = MSS_MMC_TRANSFER_FAIL;
2393             }
2394         }
2395         else
2396         {
2397             ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_HPI;
2398         }
2399     }
2400     else
2401     {
2402         ret_status = g_mmc_trs_status.state;
2403     }
2404     return (ret_status);
2405 }
2406 /*-------------------------------------------------------------------------*//**
2407  * See "mss_mmc_internal_test.h" for details of how to use this function.
2408  */
MSS_MMC_resume_sdma_write_hpi(void)2409 mss_mmc_status_t MSS_MMC_resume_sdma_write_hpi(void)
2410 {
2411     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2412 
2413     if (g_device_hpi_set == MMC_SET)
2414     {
2415         g_device_hpi_set = MMC_CLEAR;
2416         if (g_trans_remain_size != MMC_CLEAR)
2417         {
2418             g_mmc_trs_status.state = MSS_MMC_INIT_SUCCESS;
2419             ret_status = MSS_MMC_sdma_write(g_trans_src_addr, g_trans_dest_addr, g_trans_remain_size);
2420         }
2421         else
2422         {
2423             ret_status = MSS_MMC_TRANSFER_SUCCESS;
2424         }
2425     }
2426     else
2427     {
2428         ret_status = MSS_MMC_DEVICE_IS_NOT_IN_HPI_MODE;
2429     }
2430     return ret_status;
2431 }
2432 /*-------------------------------------------------------------------------*//**
2433  * See "mss_mmc_internal_test.h" for details of how to use this function.
2434  */
2435 mss_mmc_status_t
MSS_MMC_packed_write(const uint8_t * src,uint32_t dest,uint32_t size)2436 MSS_MMC_packed_write
2437 (
2438     const uint8_t *src,
2439     uint32_t dest,
2440     uint32_t size
2441 )
2442 {
2443     uint32_t blockcount;
2444     uint32_t argument;
2445     uint32_t blocklen;
2446     uint32_t tmp, srs03_data, srs9;
2447     cif_response_t response_status;
2448     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2449 
2450     blocklen = BLK_SIZE;
2451     argument = dest;
2452 
2453     if (g_mmc_init_complete == MMC_SET)
2454     {
2455         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2456         {
2457             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2458         }
2459         else
2460         {
2461             /* Size should be divided by 512, not greater than (32MB - 512) */
2462             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
2463                     || (size == MMC_CLEAR) || (src == NULL_POINTER))
2464             {
2465                 ret_status = MSS_MMC_INVALID_PARAMETER;
2466             }
2467             else
2468             {
2469                 /* Disable PCLI interrupt for MMC */
2470                 PLIC_DisableIRQ(MMC_main_PLIC);
2471                 MMC->SRS14 = MMC_CLEAR;
2472                 /* Calculate block count */
2473                 blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
2474                 /* Multi Block write */
2475                 if (blockcount > MMC_SET)
2476                 {
2477                     tmp = MMC->SRS10;
2478                     tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
2479                     MMC->SRS10 = (tmp | SRS10_DMA_SELECT_SDMA);
2480 
2481                     /* SDMA setup */
2482                     MMC->SRS22 = (uint32_t)(uintptr_t)src;
2483                     MMC->SRS23 = (uint32_t)(((uint64_t)(uintptr_t)src) >> MMC_64BIT_UPPER_ADDR_SHIFT);
2484 
2485                     /* DPS, Data transfer direction - write */
2486                     srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE
2487                                         | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
2488                                         | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
2489                                         | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
2490                                         | SRS3_DMA_ENABLE);
2491                     /* Block length and count SDMA buffer boundary */
2492                     MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT) | SRS1_DMA_BUFF_SIZE_512KB);
2493                     /* Multi block transfer */
2494                     g_mmc_is_multi_blk = MMC_CLEAR;
2495                     /* Set Block count and packed command in device using CMD23 */
2496                     response_status = cif_send_cmd(blockcount | (MMC_SET << SHIFT_30BIT),
2497                                                 MMC_CMD_23_SET_BLOCK_COUNT,
2498                                                 MSS_MMC_RESPONSE_R1);
2499                     /* Enable interrupts */
2500                     MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN | SRS14_TRANSFER_COMPLETE_SIG_EN
2501                                     | SRS14_DMA_INTERRUPT_SIG_EN | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
2502                     PLIC_EnableIRQ(MMC_main_PLIC);
2503 
2504                     /* Check data line busy */
2505                     do
2506                     {
2507                         srs9 = MMC->SRS09;
2508                     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
2509 
2510                     MMC->SRS02 = argument;
2511                     /* Execute command */
2512                     MMC->SRS03 = (uint32_t)((MMC_CMD_25_WRITE_MULTI_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
2513                 }
2514                 else
2515                 {
2516                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_FAIL;
2517                     ret_status = MSS_MMC_DATA_SIZE_IS_NOT_MULTI_BLOCK;
2518                 }
2519 
2520             }
2521             g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
2522             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2523         }
2524     }
2525     else
2526     {
2527         ret_status = MSS_MMC_NOT_INITIALISED;
2528     }
2529     return ret_status;
2530 }
2531 /*-------------------------------------------------------------------------*//**
2532  * See "mss_mmc_internal_test.h" for details of how to use this function.
2533  */
2534 mss_mmc_status_t
MSS_MMC_packed_read(uint32_t src,uint8_t * dest,uint32_t * packed_header,uint32_t size)2535 MSS_MMC_packed_read
2536 (
2537     uint32_t src,
2538     uint8_t *dest,
2539     uint32_t *packed_header,
2540     uint32_t size
2541 )
2542 {
2543     uint32_t blockcount;
2544     uint32_t argument;
2545     uint32_t blocklen;
2546     uint32_t tmp, srs03_data, srs9;
2547     cif_response_t response_status;
2548     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2549     uint16_t word_cnt = MMC_CLEAR;
2550     uint8_t blk_tran_err;
2551     uint8_t blk_write;
2552 
2553     blocklen = BLK_SIZE;
2554     argument = src;
2555 
2556     if (g_mmc_init_complete == MMC_SET)
2557     {
2558         if (MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2559         {
2560             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2561         }
2562         else
2563         {
2564             /* Size should be divided by 512, not greater than (32MB - 512) */
2565             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
2566                     || (size == MMC_CLEAR) || (dest == NULL_POINTER)
2567                     || (packed_header == NULL_POINTER))
2568             {
2569                 ret_status = MSS_MMC_INVALID_PARAMETER;
2570             }
2571             else
2572             {
2573                 /* Disable PCLI interrupt for MMC */
2574                 PLIC_DisableIRQ(MMC_main_PLIC);
2575                 MMC->SRS14 = MMC_CLEAR;
2576                 /* Calculate block count */
2577                 blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
2578 
2579                 if (blockcount > MMC_SET)
2580                 {
2581                     /* Block length and count*/
2582                     MMC->SRS01 = (BLK_SIZE | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
2583 
2584                     /* DPS, Data transfer direction - read */
2585                     srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_WRITE |SRS3_BLOCK_COUNT_ENABLE
2586                                         | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
2587                                         | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
2588                                         | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
2589 
2590                     /* Set Block count with packed in device using CMD23 */
2591                     response_status = cif_send_cmd(MMC_SET | (MMC_SET << SHIFT_30BIT),
2592                                                 MMC_CMD_23_SET_BLOCK_COUNT,
2593                                                 MSS_MMC_RESPONSE_R1);
2594 
2595                     /* Check cmd and data line busy */
2596                     do
2597                     {
2598                         srs9 = MMC->SRS09;
2599                     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
2600 
2601                     /* Command argument */
2602                     MMC->SRS02 = argument;
2603                     /* Execute command */
2604                     MMC->SRS03 = (uint32_t)((MMC_CMD_25_WRITE_MULTI_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
2605 
2606                     do
2607                     {
2608                         blk_write = MMC->SRS12;
2609                     }while (MMC_CLEAR == (blk_write & SRS12_BUFFER_WRITE_READY));
2610                     /* Load the block of data into the
2611                     * buffer, one byte at a time through the Buffer Data Register.
2612                     */
2613                     while ((BLK_SIZE/WORD_SIZE) > word_cnt)
2614                     {
2615                         MMC->SRS08 = packed_header[word_cnt];
2616                         ++word_cnt;
2617                     }
2618                     /* Check is block write complete */
2619                     do
2620                     {
2621                         blk_write = MMC->SRS12;
2622                     }while (MMC_CLEAR == (blk_write & SRS12_TRANSFER_COMPLETE));
2623 
2624                     blk_tran_err = MMC->SRS12;
2625                     /* Abort if any errors*/
2626                     if ((SRS12_ERROR_STATUS_MASK & blk_tran_err) == MMC_CLEAR)
2627                     {
2628                         ret_status = MSS_MMC_TRANSFER_SUCCESS;
2629                     }
2630                     else
2631                     {
2632                         ret_status = MSS_MMC_ERR_INTERRUPT;
2633                     }
2634                     MMC->SRS12 = blk_tran_err;
2635 
2636                     if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
2637                     {
2638                         tmp = MMC->SRS10;
2639                         tmp = (tmp & (~SRS10_DMA_SELECT_MASK));
2640                         MMC->SRS10 = (tmp | SRS10_DMA_SELECT_SDMA);
2641 
2642                         /* SDMA setup */
2643                         MMC->SRS22 = (uint32_t)(uintptr_t)dest;
2644                         MMC->SRS23 = (uint32_t)(((uint64_t)(uintptr_t)dest) >> MMC_64BIT_UPPER_ADDR_SHIFT);
2645                         /* Block length and count SDMA buffer boundary */
2646                         MMC->SRS01 = (blocklen | (blockcount << BLOCK_COUNT_ENABLE_SHIFT) | SRS1_DMA_BUFF_SIZE_512KB);
2647                         /* DPS, Data transfer direction - read */
2648                         srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ
2649                                             | SRS3_MULTI_BLOCK_SEL | SRS3_BLOCK_COUNT_ENABLE
2650                                             | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
2651                                             | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN
2652                                             | SRS3_DMA_ENABLE);
2653                         /* Multi block transfer */
2654                         g_mmc_is_multi_blk = MMC_CLEAR;
2655 
2656                         /* Set Block count with packed in device using CMD23 */
2657                         response_status = cif_send_cmd(blockcount | (MMC_SET << SHIFT_30BIT),
2658                                                 MMC_CMD_23_SET_BLOCK_COUNT,
2659                                                 MSS_MMC_RESPONSE_R1);
2660                         /* Enable interrupts */
2661                         MMC->SRS14 = (SRS14_COMMAND_COMPLETE_SIG_EN | SRS14_TRANSFER_COMPLETE_SIG_EN
2662                                             | SRS14_DMA_INTERRUPT_SIG_EN | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
2663                         PLIC_EnableIRQ(MMC_main_PLIC);
2664                         /* Multi Block read */
2665 
2666                         /* Check cmd and data line busy */
2667                         do
2668                         {
2669                             srs9 = MMC->SRS09;
2670                         }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
2671 
2672                         /* Command argument */
2673                         MMC->SRS02 = argument;
2674                         /* Execute command */
2675                         MMC->SRS03 = (uint32_t)((MMC_CMD_18_READ_MULTIPLE_BLOCK << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
2676 
2677                         g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
2678                         ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2679                     }
2680                     else
2681                     {
2682                         g_mmc_trs_status.state = MSS_MMC_TRANSFER_FAIL;
2683                     }
2684                 }
2685                 else
2686                 {
2687                     g_mmc_trs_status.state = MSS_MMC_TRANSFER_FAIL;
2688                     ret_status = MSS_MMC_DATA_SIZE_IS_NOT_MULTI_BLOCK;
2689                 }
2690             }
2691         }
2692     }
2693     else
2694     {
2695         ret_status = MSS_MMC_NOT_INITIALISED;
2696     }
2697     return ret_status;
2698 }
2699 
2700 /*-------------------------------------------------------------------------*//**
2701  * See "mss_mmc_internal_test.h" for details of how to use this function.
2702  */
2703 mss_mmc_status_t
MSS_MMC_cq_single_task_write(const uint8_t * src,uint32_t dest,uint8_t task_id,uint32_t size)2704 MSS_MMC_cq_single_task_write
2705 (
2706     const uint8_t *src,
2707     uint32_t dest,
2708     uint8_t task_id,
2709     uint32_t size
2710 )
2711 {
2712     uint32_t reg;
2713     uint32_t *dcmdTaskDesc = NULL_POINTER;
2714     uint32_t flags;
2715     uint32_t desc_offset;
2716     volatile uint32_t trans_status_isr;
2717     uint32_t cmd_response;
2718     uint32_t blockcount;
2719     uint32_t argument;
2720     uint32_t blocklen;
2721 
2722     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2723     cif_response_t response_status = TRANSFER_IF_FAIL;
2724 
2725     desc_offset = CQ_HOST_NUMBER_OF_TASKS * task_id;
2726 
2727     dcmdTaskDesc = (uint32_t *)(g_desc_addr + desc_offset);
2728     g_cq_task_id = MMC_CLEAR;
2729     blocklen = BLK_SIZE;
2730     argument = dest;
2731 
2732     if(g_mmc_cq_init_complete == MMC_SET)
2733     {
2734         if(MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2735         {
2736             ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2737         }
2738         else
2739         {
2740             /* Size should be divided by 512, not greater than (32MB - 512) */
2741             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
2742                     || (size == MMC_CLEAR) || (src == NULL_POINTER))
2743             {
2744                 ret_status = MSS_MMC_INVALID_PARAMETER;
2745             }
2746             else
2747             {
2748                 /* Disable PCLI interrupt for MMC */
2749                 PLIC_DisableIRQ(MMC_main_PLIC);
2750                 MMC->SRS14 = MMC_CLEAR;
2751                 /* Calculate block count */
2752                 blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
2753 
2754                 /* Check MMC device is busy */
2755                 do
2756                 {
2757                     response_status = cif_send_cq_direct_command(g_desc_addr, sdcard_RCA,
2758                                                 MMC_CMD_13_SEND_STATUS, MSS_MMC_RESPONSE_R1, CQ_DCMD_TASK_ID);
2759                 } while(DEVICE_BUSY == response_status);
2760 
2761 
2762                 flags = (uint32_t)(CQ_DESC_VALID |  CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT);
2763                 flags |= CQ_DESC_SET_CONTEXT_ID(MMC_SET) | CQ_DESC_DATA_DIR_WRITE;
2764 
2765                 dcmdTaskDesc[MMC_CLEAR] = flags | (blockcount << SHIFT_16BIT);
2766                 dcmdTaskDesc[BYTES_1] = argument;
2767                 dcmdTaskDesc[BYTES_2] = MMC_CLEAR;
2768                 dcmdTaskDesc[BYTES_3] = MMC_CLEAR;
2769 
2770                 /* Supports only 64KB */
2771                 dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN |  CQ_DESC_END) | (size << SHIFT_16BIT));
2772                 /* Data buffer address in host memory, lower part */
2773                 dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)src;
2774                 /* Data buffer address in host memory, higher part */
2775                 dcmdTaskDesc[BYTES_6] = (uint32_t)(((uint64_t)(uintptr_t)src) >> MMC_64BIT_UPPER_ADDR_SHIFT);
2776                 dcmdTaskDesc[BYTES_7] = MMC_CLEAR;
2777 
2778                 g_cq_task_id = MMC_SET;
2779                 /* Enable interrupts */
2780                 MMC->SRS14 = (SRS14_CMD_QUEUING_SIG_EN | SRS14_COMMAND_TIMEOUT_ERR_SIG_EN
2781                                      | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
2782                 PLIC_EnableIRQ(MMC_main_PLIC);
2783                 /* Set doorbell to start processing descriptors by controller */
2784                 reg = MMC_SET << task_id;
2785                 MMC->CQRS10 = reg;
2786 
2787                 g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
2788                 ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2789             }
2790         }
2791     }
2792     else
2793     {
2794         ret_status = MSS_MMC_CQ_NOT_INITIALISED;
2795     }
2796     return ret_status;
2797 }
2798 /*-------------------------------------------------------------------------*//**
2799  * See "mss_mmc_internal_test.h" for details of how to use this function.
2800  */
2801 mss_mmc_status_t
MSS_MMC_cq_single_task_read(uint32_t src,uint8_t * dest,uint8_t task_id,uint32_t size)2802 MSS_MMC_cq_single_task_read
2803 (
2804     uint32_t src,
2805     uint8_t *dest,
2806     uint8_t task_id,
2807     uint32_t size
2808 )
2809 {
2810     uint32_t reg;
2811     uint32_t *dcmdTaskDesc = NULL_POINTER;
2812     uint32_t flags;
2813     uint32_t desc_offset;
2814     volatile uint32_t trans_status_isr;
2815     uint32_t cmd_response;
2816     uint32_t blockcount;
2817     uint32_t argument;
2818     uint32_t blocklen;
2819 
2820     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2821     cif_response_t response_status = TRANSFER_IF_FAIL;
2822 
2823     desc_offset = CQ_HOST_NUMBER_OF_TASKS * task_id;
2824 
2825     dcmdTaskDesc = (uint32_t *)(g_desc_addr + desc_offset);
2826     g_cq_task_id = MMC_CLEAR;
2827     blocklen = BLK_SIZE;
2828     argument = src;
2829 
2830     if(g_mmc_cq_init_complete == MMC_SET)
2831     {
2832        if(MSS_MMC_TRANSFER_IN_PROGRESS == g_mmc_trs_status.state)
2833        {
2834            ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2835        }
2836        else
2837        {
2838             /* Size should be divided by 512, not greater than (32MB - 512) */
2839             if (((size % blocklen) != MMC_CLEAR) || (size > (SIZE_32MB - BLK_SIZE))
2840                     || (size == MMC_CLEAR) || (dest == NULL_POINTER))
2841             {
2842                 ret_status = MSS_MMC_INVALID_PARAMETER;
2843             }
2844             else
2845             {
2846                 /* Disable PCLI interrupt for MMC */
2847                 PLIC_DisableIRQ(MMC_main_PLIC);
2848                 MMC->SRS14 = MMC_CLEAR;
2849                 /* Calculate block count */
2850                 blockcount = ((size - MMC_SET) / blocklen) + MMC_SET;
2851                 /* Check MMC device is busy */
2852                 do
2853                 {
2854                    response_status = cif_send_cq_direct_command(g_desc_addr, sdcard_RCA,
2855                                                     MMC_CMD_13_SEND_STATUS, MSS_MMC_RESPONSE_R1, CQ_DCMD_TASK_ID);
2856                 } while(DEVICE_BUSY == response_status);
2857 
2858                 flags = (uint32_t)(CQ_DESC_VALID |  CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT);
2859                 flags |= CQ_DESC_SET_CONTEXT_ID(MMC_CLEAR) | CQ_DESC_DATA_DIR_READ;
2860 
2861                 dcmdTaskDesc[MMC_CLEAR] = flags | (blockcount << SHIFT_16BIT);
2862                 dcmdTaskDesc[BYTES_1] = argument;
2863                 dcmdTaskDesc[BYTES_2] = MMC_CLEAR;
2864                 dcmdTaskDesc[BYTES_3] = MMC_CLEAR;
2865 
2866                 /* Supports only 64KB */
2867                 dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN |  CQ_DESC_END) | (size << SHIFT_16BIT));
2868                 /* Data buffer address in host memory, lower part */
2869                 dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)dest;
2870                 /* Data buffer address in host memory, higher part */
2871                 dcmdTaskDesc[BYTES_6] = (uint32_t)(((uint64_t)(uintptr_t)dest) >> MMC_64BIT_UPPER_ADDR_SHIFT);
2872                 dcmdTaskDesc[BYTES_7] = MMC_CLEAR;
2873 
2874                 g_cq_task_id = MMC_SET;
2875                 /* Enable interrupts */
2876                 MMC->SRS14 = (SRS14_CMD_QUEUING_SIG_EN | SRS14_COMMAND_TIMEOUT_ERR_SIG_EN
2877                                      | SRS14_DATA_TIMEOUT_ERR_SIG_EN);
2878                 PLIC_EnableIRQ(MMC_main_PLIC);
2879 
2880                 /* Set doorbell to start processing descriptors by controller */
2881                 reg = MMC_SET << task_id;
2882                 MMC->CQRS10 = reg;
2883                 g_mmc_trs_status.state = MSS_MMC_TRANSFER_IN_PROGRESS;
2884                 ret_status = MSS_MMC_TRANSFER_IN_PROGRESS;
2885             }
2886         }
2887     }
2888     else
2889     {
2890         ret_status = MSS_MMC_CQ_NOT_INITIALISED;
2891     }
2892     return ret_status;
2893 }
2894 
2895 #endif /* MSS_MMC_INTERNAL_APIS */
2896 /*******************************************************************************
2897 ****************************** Private Functions *******************************
2898 *******************************************************************************/
phy_training_mmc(uint8_t delay_type,uint32_t clk_rate)2899 static mss_mmc_status_t phy_training_mmc(uint8_t delay_type, uint32_t clk_rate)
2900 {
2901     uint8_t delay;
2902     uint8_t max_delay;
2903     uint8_t new_delay;
2904     uint8_t pos, length, curr_length;
2905     uint8_t rx_buff[BLK_SIZE];
2906     uint32_t read_srs11;
2907     uint32_t cmd_response;
2908 
2909     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
2910     cif_response_t response_status = TRANSFER_IF_FAIL;
2911 
2912     if (clk_rate <= MSS_MMC_CLOCK_12_5MHZ)
2913     {
2914         max_delay = BYTES_20;
2915     }
2916     else
2917     {
2918         max_delay = (MSS_MMC_CLOCK_200MHZ / clk_rate) * BYTES_2;
2919     }
2920 
2921     pos = length = curr_length = MMC_CLEAR;
2922     /* Reset Data and cmd line */
2923     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
2924     for (delay = MMC_CLEAR; delay < max_delay; delay++)
2925     {
2926         phy_write_set(delay_type, delay);
2927 
2928         ret_status = read_tune_block((uint32_t *)rx_buff, BLK_SIZE, MMC_CMD_17_READ_SINGLE_BLOCK);
2929         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
2930         {
2931             curr_length++;
2932             if (curr_length > length)
2933             {
2934                 pos = delay - length;
2935                 length++;
2936                 /* Reset Data and cmd line */
2937                  MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
2938             }
2939         }
2940         else
2941         {
2942             do
2943             {
2944                 if (TRANSFER_IF_FAIL == response_status)
2945                 {
2946                     /* Reset Data and cmd line */
2947                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
2948 
2949                     do
2950                     {
2951                         read_srs11 = MMC->SRS11;
2952                     }while ((read_srs11 & MMC_RESET_DATA_CMD_LINE) != MMC_CLEAR);
2953                 }
2954 
2955                 response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
2956                                             MMC_CMD_13_SEND_STATUS,
2957                                             MSS_MMC_RESPONSE_R1);
2958                 cmd_response = MMC->SRS04;
2959             }while ((TRANSFER_IF_SUCCESS != response_status) ||
2960                     ((cmd_response & DEVICE_STATE_MASK) != DEVICE_STATE_TRANS));
2961 
2962             curr_length = MMC_CLEAR;
2963             response_status = TRANSFER_IF_FAIL;
2964         }
2965     }
2966 
2967     new_delay = pos + (length / BYTES_2);
2968     phy_write_set(delay_type, new_delay);
2969 
2970     ret_status = read_tune_block((uint32_t *)rx_buff, BLK_SIZE, MMC_CMD_17_READ_SINGLE_BLOCK);
2971     /* Reset Data and cmd line */
2972     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
2973     return ret_status;
2974 }
2975 /******************************************************************************/
phy_write_set(uint8_t delay_type,uint8_t delay_value)2976 static void phy_write_set(uint8_t delay_type, uint8_t delay_value)
2977 {
2978     uint8_t phyaddr = MMC_CLEAR;
2979     uint32_t reg = MMC_CLEAR;
2980     uint32_t phycfg = MMC_CLEAR;
2981 
2982     /* Phy delay set for eMMC modes */
2983     get_phy_addr(delay_type, &phyaddr);
2984 
2985     do
2986     {
2987         reg = MMC->HRS04;
2988     }while ((reg & HRS_PHY_ACKNOWLEDGE_REQUEST) != MMC_CLEAR);
2989 
2990     phycfg = ((uint32_t)phyaddr | (delay_value << SHIFT_8BIT));
2991 
2992     /* Set data and address */
2993     MMC->HRS04 = phycfg;
2994     /* Send write request */
2995     MMC->HRS04 |= (uint32_t)HRS_PHY_WRITE_REQUEST;
2996     /* Wait for acknowledge */
2997     do
2998     {
2999         reg = MMC->HRS04;
3000     }while ((reg & HRS_PHY_ACKNOWLEDGE_REQUEST) == MMC_CLEAR);
3001 
3002     phycfg &= ~(uint32_t)HRS_PHY_WRITE_REQUEST;
3003     /* Clear write request */
3004     MMC->HRS04 = phycfg;
3005     MMC->HRS04 = MMC_CLEAR;
3006 }
3007 /******************************************************************************/
get_phy_addr(MSS_MMC_phydelay phydelaytype,uint8_t * phySetAddr)3008 static void get_phy_addr(MSS_MMC_phydelay phydelaytype, uint8_t *phySetAddr)
3009 {
3010     uint8_t i;
3011 
3012     static const struct phydelayaddresses phydelayaddr[] = {
3013         { UIS_ADDR_DEFAULT_SPEED, MSS_MMC_PHY_DELAY_INPUT_DEFAULT_SPEED},
3014         { UIS_ADDR_HIGH_SPEED, MSS_MMC_PHY_DELAY_INPUT_HIGH_SPEED},
3015         { UIS_ADDR_UHSI_SDR12, MSS_MMC_PHY_DELAY_INPUT_SDR12},
3016         { UIS_ADDR_UHSI_SDR25, MSS_MMC_PHY_DELAY_INPUT_SDR25},
3017         { UIS_ADDR_UHSI_SDR50, MSS_MMC_PHY_DELAY_INPUT_SDR50},
3018         { UIS_ADDR_UHSI_DDR50, MSS_MMC_PHY_DELAY_INPUT_DDR50},
3019         { UIS_ADDR_MMC_LEGACY, MSS_MMC_PHY_DELAY_INPUT_MMC_LEGACY},
3020         { UIS_ADDR_MMC_SDR, MSS_MMC_PHY_DELAY_INPUT_MMC_SDR},
3021         { UIS_ADDR_MMC_DDR, MSS_MMC_PHY_DELAY_INPUT_MMC_DDR},
3022         { UIS_ADDR_SDCLK, MSS_MMC_PHY_DELAY_DLL_SDCLK},
3023         { UIS_ADDR_HS_SDCLK, MSS_MMC_PHY_DELAY_DLL_HS_SDCLK},
3024         { UIS_ADDR_DAT_STROBE, MSS_MMC_PHY_DELAY_DLL_DAT_STROBE},
3025     };
3026 
3027     for (i = MMC_CLEAR; i < (sizeof(phydelayaddr) / sizeof(phydelayaddr[MMC_CLEAR])); i++)
3028     {
3029         if (phydelayaddr[i].phydelaytype == phydelaytype)
3030         {
3031             *phySetAddr = phydelayaddr[i].address;
3032             break;
3033         }
3034     }
3035 }
3036 /******************************************************************************/
adma2_create_descriptor_table(const uint8_t * data_src,uint32_t data_sz)3037 static mss_mmc_status_t adma2_create_descriptor_table
3038 (
3039         const uint8_t *data_src,
3040         uint32_t data_sz
3041 )
3042 {
3043     uint32_t datasize = data_sz;
3044     uint32_t i = MMC_CLEAR;
3045     uint32_t j = MMC_CLEAR;
3046     uintptr_t buf_address = (uintptr_t)data_src;
3047     uint32_t offset = MMC_CLEAR;
3048     mss_mmc_status_t status = MSS_MMC_NO_ERROR;
3049 
3050     if (datasize >= SIZE_64KB)
3051     {
3052         uint32_t current_subsize = SIZE_64KB;
3053         uint32_t size = datasize;
3054 
3055         while (size > MMC_CLEAR)
3056         {
3057             if (i >= SDIO_CFG_SDIO_BUFFERS_COUNT)
3058             {
3059                 /* There is not enough buffer count to create descriptors.
3060                  You need to increase SDIO_CFG_SDIO_BUFFERS_COUNT parameter */
3061                 status = MSS_MMC_INVALID_PARAMETER;
3062                 break;
3063             }
3064 
3065             if (size < current_subsize)
3066             {
3067                 current_subsize = size;
3068             }
3069             adma_descriptor_table[j++] = (ADMA2_DESCRIPTOR_TYPE_TRAN
3070                                                 | ADMA2_DESCRIPTOR_VAL | ADMA2_DESCRIPTOR_INT
3071                                                 | ((current_subsize & MASK_16BIT) << SHIFT_16BIT));
3072             adma_descriptor_table[j++] = ((uint32_t)buf_address & MASK_32BIT);
3073             adma_descriptor_table[j++] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT);
3074             adma_descriptor_table[j] = MMC_CLEAR;
3075             j++;
3076 
3077             size -= current_subsize;
3078             buf_address += current_subsize;
3079             i++;
3080         }
3081     }
3082     else
3083     {
3084         adma_descriptor_table[j++] = (ADMA2_DESCRIPTOR_TYPE_TRAN
3085                                     | ADMA2_DESCRIPTOR_VAL | ADMA2_DESCRIPTOR_INT
3086                                     | ((datasize & MASK_16BIT) << SHIFT_16BIT));
3087         adma_descriptor_table[j++] = ((uint32_t)buf_address & MASK_32BIT);
3088         adma_descriptor_table[j++] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT);
3089         adma_descriptor_table[j] = MMC_CLEAR;
3090         i = MMC_SET;
3091     }
3092     /* Last descriptor finishes transmission */
3093     offset  = (i * WORD_SIZE) - WORD_SIZE;
3094     adma_descriptor_table[offset] |= ADMA2_DESCRIPTOR_END;
3095 
3096     return (status);
3097 }
3098 /******************************************************************************/
mmccard_oper_config(const mss_mmc_cfg_t * cfg)3099 static mss_mmc_status_t mmccard_oper_config(const mss_mmc_cfg_t * cfg)
3100 {
3101     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
3102     cif_response_t response_status;
3103     uint32_t response_reg;
3104     uint32_t power_up_status;
3105     uint32_t access_mode;
3106     uint32_t csd_max_sector_lwr;
3107     uint32_t max_sector_len;
3108     uint16_t sector_size;
3109     uint32_t oper_cond = MMC_CLEAR;
3110 
3111     response_status = cif_send_cmd(STUFF_BITS, MMC_CMD_1_SEND_OP_COND,
3112                                                 MSS_MMC_RESPONSE_R3);
3113     if (TRANSFER_IF_SUCCESS == response_status)
3114     {
3115         response_reg = MMC->SRS04;
3116         if (cfg->bus_voltage == MSS_MMC_1_8V_BUS_VOLTAGE)
3117         {
3118             if ((response_reg & MMC_DEVICE_LOW_POWER) == MMC_DEVICE_LOW_POWER)
3119             {
3120                 oper_cond = MMC_DEVICE_LOW_VOLT_SET;
3121             }
3122             else
3123             {
3124                 ret_status = MSS_MMC_DEVICE_NOT_SUPPORT_LOW_POWER;
3125             }
3126         }
3127         else
3128         {
3129             oper_cond = MMC_DEVICE_3_3V_VOLT_SET;
3130         }
3131 
3132         if (ret_status == MSS_MMC_NO_ERROR)
3133         {
3134             do
3135             {
3136                 response_status = cif_send_cmd(oper_cond,
3137                                         MMC_CMD_1_SEND_OP_COND,
3138                                         MSS_MMC_RESPONSE_R3);
3139                 response_reg = MMC->SRS04;
3140                 power_up_status = BUSY_BIT_MASK & response_reg;
3141 
3142             } while ((BUSY_BIT_MASK != power_up_status) && (TRANSFER_IF_FAIL != response_status));
3143         }
3144         else
3145         {
3146             response_status = TRANSFER_IF_FAIL;
3147         }
3148     }
3149 
3150     if (TRANSFER_IF_SUCCESS == response_status)
3151     {
3152         mmc_delay(DELAY_COUNT);
3153 
3154         response_reg = MMC->SRS04;;
3155         /* If access_mode = 2 then sector address, if access = 0 then byte mode */
3156         access_mode = ((SECTOR_ACCESS_MODE_MASK & response_reg) >> SECTOR_SHIFT);
3157 
3158         /* Read CID register from device */
3159         response_status = cif_send_cmd(STUFF_BITS, MMC_CMD_2_ALL_SEND_CID,
3160                                                     MSS_MMC_RESPONSE_R2);
3161         if (TRANSFER_IF_SUCCESS == response_status)
3162         {
3163             do
3164             {
3165                 /* Assign a RCA to the device */
3166                 response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
3167                                    MMC_CMD_3_SET_RELATIVE_ADDR,
3168                                    MSS_MMC_RESPONSE_R1);
3169             }while (TRANSFER_IF_SUCCESS != response_status);
3170         }
3171 
3172         if (TRANSFER_IF_SUCCESS == response_status)
3173         {
3174             /* Read CSD register from device */
3175             response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
3176                                             MMC_CMD_9_SEND_CSD,
3177                                             MSS_MMC_RESPONSE_R2);
3178             if (TRANSFER_IF_SUCCESS == response_status)
3179             {
3180                 /* Sector size from "Max. write data block length"  of CSD[25:22]*/
3181                 csd_max_sector_lwr  = MMC->SRS04 & SECT_SIZE_CSD_MASK;
3182                 max_sector_len = csd_max_sector_lwr >> SECT_SIZE_CSD_SHIFT;
3183                 sector_size = (uint16_t)((uint32_t)MMC_SET << max_sector_len);
3184 
3185                 /* Select device */
3186                 response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
3187                                             MMC_CMD_7_SELECT_DESELECT_CARD,
3188                                             MSS_MMC_RESPONSE_R1);
3189             }
3190 
3191             if (TRANSFER_IF_SUCCESS == response_status)
3192             {
3193                 /* Set MMC data bus width 1-bit */
3194                 response_status = cif_send_cmd( MMC_DW_CSD |(MSS_MMC_DATA_WIDTH_1BIT << SHIFT_8BIT),
3195                                                 MMC_CMD_6_SWITCH,
3196                                                 MSS_MMC_RESPONSE_R1B);
3197                 if (TRANSFER_IF_FAIL == response_status)
3198                 {
3199                     ret_status = MSS_MMC_DWIDTH_ERR;
3200                 }
3201                 else
3202                 {
3203                     response_status = check_device_status(response_status);
3204 
3205                     /* Set Phy delay for select MMC mode */
3206                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_MMC_LEGACY, MSS_MMC_CLOCK_400KHZ);
3207                     if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
3208                     {
3209                         /* Data timeout 500ms */
3210                         ret_status = set_data_timeout(DATA_TIMEOUT_VALUE);
3211                         if (ret_status == MSS_MMC_NO_ERROR)
3212                         {
3213                             g_mmc_init_complete = MMC_SET;
3214                             ret_status =  MSS_MMC_CARD_SELECT_SUCCESS;
3215                         }
3216                     }
3217                 }
3218             }
3219             else
3220             {
3221                 ret_status = MSS_MMC_CARD_SELECT_ERROR;
3222             }
3223         }
3224         else
3225         {
3226             ret_status = MSS_MMC_RCA_ERROR;
3227         }
3228     }
3229     else
3230     {
3231         ret_status = MSS_MMC_OP_COND_ERR;
3232     }
3233     return ret_status;
3234 }
3235 /******************************************************************************/
sdcard_oper_config(const mss_mmc_cfg_t * cfg)3236 static mss_mmc_status_t sdcard_oper_config(const mss_mmc_cfg_t * cfg)
3237 {
3238     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
3239     cif_response_t response_status;
3240     uint32_t temp;
3241     uint32_t scr_reg[SHIFT_2BIT];
3242     uint32_t bus_width;
3243     uint32_t argument;
3244 
3245     uint32_t S18A = MMC_CLEAR;
3246     uint8_t S18R = MMC_CLEAR;
3247     uint8_t XPC = MMC_CLEAR;
3248     uint32_t tmp, CCS;
3249     uint32_t max_current_3_3V;
3250     uint32_t max_current_1_8V;
3251 
3252     uint32_t card_ocr_reg = MASK_24BIT;
3253     uint32_t card_volt = MMC_CLEAR;
3254     uint32_t controller_volt = MMC_CLEAR;
3255 
3256     uint32_t csd_max_sector_lwr;
3257     uint32_t max_sector_len;
3258     uint16_t sector_size;
3259 
3260     response_status = cif_send_cmd(IF_COND_27V_33V,
3261                                     SD_CMD_8_SEND_IF_COND,
3262                                     MSS_MMC_RESPONSE_R7);
3263     if (TRANSFER_IF_SUCCESS == response_status)
3264     {
3265         tmp = MMC->SRS18;
3266         max_current_3_3V = ((tmp & MASK_8BIT) * SHIFT_4BIT);
3267         max_current_1_8V = (((tmp & BYTE_3_MASK) >> SHIFT_16BIT) * SHIFT_4BIT);
3268         /* Flag used for SDXC cards
3269            if card is initialized with XPC=1
3270            then it is operating less than 150mA
3271         */
3272         XPC = ((max_current_1_8V >= MAX_CURRENT_MA) && (max_current_3_3V >= MAX_CURRENT_MA)) ? MMC_SET : MMC_CLEAR;
3273         /* Check if UHS-I is supported by SDIO host controller, then set to 1 */
3274         S18R = (is_uhsi_supported() != MMC_CLEAR) ? MMC_SET : MMC_CLEAR;
3275 
3276         response_status = cif_send_cmd(MMC_CLEAR,
3277                                         SD_CMD_55,
3278                                         MSS_MMC_RESPONSE_R1);
3279         if (TRANSFER_IF_SUCCESS == response_status)
3280         {
3281             response_status = cif_send_cmd(MMC_CLEAR,
3282                                         SD_ACMD_41_SEND_OP_COND,
3283                                         MSS_MMC_RESPONSE_R3);
3284             if (TRANSFER_IF_SUCCESS == response_status)
3285             {
3286                  /* Read OCR register */
3287                 card_ocr_reg = MMC->SRS04;
3288 
3289                 if ((cfg->bus_speed_mode == MSS_SDCARD_MODE_DEFAULT_SPEED) ||
3290                         (cfg->bus_speed_mode == MSS_SDCARD_MODE_HIGH_SPEED))
3291                 {
3292                     S18R = MMC_CLEAR;
3293                 }
3294                 /* Check the voltage capabilities of the SDIO host controller and a card
3295                    to set appropriate voltage */
3296                 if ((card_ocr_reg & SDCARD_REG_OCR_3_3_3_4) != MMC_CLEAR)
3297                 {
3298                     card_volt = (uint32_t)SDCARD_REG_OCR_3_3_3_4;
3299                     controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3300                 }
3301                 else if ((card_ocr_reg & SDCARD_REG_OCR_3_2_3_3) != MMC_CLEAR)
3302                 {
3303                     card_volt = (uint32_t)SDCARD_REG_OCR_3_2_3_3;
3304                     controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3305                 }
3306                 else if ((card_ocr_reg & SDCARD_REG_OCR_3_0_3_1) != MMC_CLEAR)
3307                 {
3308                     card_volt = (uint32_t)SDCARD_REG_OCR_3_0_3_1;
3309                     controller_volt = SRS10_SET_3_0V_BUS_VOLTAGE;
3310                 }
3311                 else if ((card_ocr_reg & SDCARD_REG_OCR_2_9_3_0) != MMC_CLEAR)
3312                 {
3313                     card_volt = (uint32_t)SDCARD_REG_OCR_2_9_3_0;
3314                     controller_volt = SRS10_SET_3_0V_BUS_VOLTAGE;
3315                 }
3316                 else
3317                 {
3318                     /* Default values */
3319                     card_volt = (uint32_t)SDCARD_REG_OCR_3_3_3_4;
3320                     controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3321                 }
3322 
3323                 /* If the voltage is different to 3.3v */
3324                 if (controller_volt != SRS10_SET_3_3V_BUS_VOLTAGE)
3325                 {
3326                     set_sdhost_power(controller_volt);
3327                     response_status = cif_send_cmd(RESET_ARG,
3328                                                 MMC_CMD_0_GO_IDLE_STATE,
3329                                                 MSS_MMC_RESPONSE_NO_RESP);
3330 
3331                     if (TRANSFER_IF_SUCCESS == response_status)
3332                     {
3333                         mmc_delay(DELAY_COUNT);
3334                         response_status = cif_send_cmd(IF_COND_27V_33V,
3335                                                         SD_CMD_8_SEND_IF_COND,
3336                                                         MSS_MMC_RESPONSE_R7);
3337                         if (TRANSFER_IF_SUCCESS == response_status)
3338                         {
3339                             temp = MMC->SRS04;
3340                         }
3341                         else
3342                         {
3343                             return MSS_MMC_SDCARD_NOT_SUPPORT_VOLTAGE;
3344                         }
3345                     }
3346                 }
3347                 argument = card_volt;
3348                 /* If card sent response on CMD8 command
3349                    set host high capacity flag to 1 */
3350                 argument |= (uint32_t)SDCARD_ACMD41_HCS;
3351                 if (S18R != MMC_CLEAR)
3352                 {
3353                     argument |= (uint32_t)SDCARD_REG_OCR_S18R;
3354                 }
3355 
3356                 if (XPC != MMC_CLEAR)
3357                 {
3358                     argument |= (uint32_t)SDCARD_REG_OCR_XPC;
3359                 }
3360                 ret_status = MSS_MMC_TRANSFER_SUCCESS;
3361 
3362                 /* Read OCR register from SD card*/
3363                 do
3364                 {
3365                     mmc_delay(DELAY_COUNT);
3366                     response_status = cif_send_cmd(MMC_CLEAR,
3367                                         SD_CMD_55,
3368                                         MSS_MMC_RESPONSE_R1);
3369                     if (TRANSFER_IF_SUCCESS == response_status)
3370                     {
3371                         mmc_delay(DELAY_COUNT);
3372                         response_status = cif_send_cmd(argument,
3373                                         SD_ACMD_41_SEND_OP_COND,
3374                                         MSS_MMC_RESPONSE_R3);
3375                     }
3376                     else
3377                     {
3378                         break;
3379                     }
3380                     tmp = MMC->SRS04;
3381                 }while ((tmp & SDCARD_REG_OCR_READY) == MMC_CLEAR);
3382                 /* If CCS = 0, SDSC card < 2gb. If CCS = 1, SDHC/XC >2gb */
3383                 CCS = MMC->SRS04 & SDCARD_REG_OCR_CCS;
3384                 S18A = MMC->SRS04 & SDCARD_REG_OCR_S18A;
3385                 /* UHI -I Support */
3386                 if ((S18A != MMC_CLEAR) && (TRANSFER_IF_SUCCESS == response_status))
3387                 {
3388                     if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_4BIT)
3389                     {
3390                         MMC->SRS10 |= SRS10_DATA_WIDTH_4BIT;
3391                     }
3392                     else
3393                     {
3394                         return MSS_MMC_MODE_NOT_SUPPORT_DATAWIDTH;
3395                     }
3396 
3397                     const uint32_t dat_level = (SRS9_DAT0_SIGNAL_LEVEL | SRS9_DAT1_SIGNAL_LEVEL
3398                                               | SRS9_DAT2_SIGNAL_LEVEL | SRS9_DAT3_SIGNAL_LEVEL);
3399 
3400                     response_status = cif_send_cmd(MMC_CLEAR,
3401                                                 SD_CMD_11_VOLAGE_SWITCH,
3402                                                 MSS_MMC_RESPONSE_R1);
3403                     if (TRANSFER_IF_SUCCESS == response_status)
3404                     {
3405                         /* Disable sd clock */
3406                         temp = MMC->SRS11;
3407                         temp &= ~(uint32_t)SRS11_SD_CLOCK_ENABLE;
3408                         MMC->SRS11 = temp;
3409                         /* If dat line is not 0000b return error */
3410                         tmp = MMC->SRS09;
3411                         if ((tmp & dat_level) != MMC_CLEAR)
3412                         {
3413                             ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3414                         }
3415                         else
3416                         {
3417                             /* 1.8V signal enable */
3418                             tmp = MMC->SRS15;
3419                             tmp |= SRS15_18V_ENABLE;
3420                             MMC->SRS15 = tmp;
3421 
3422                             /* Wait 5ms */
3423                             mmc_delay(DELAY_COUNT);
3424                             mmc_delay(DELAY_COUNT);
3425                             /* If 1.8V signal enable is cleared by host return with error */
3426                             tmp = MMC->SRS15;
3427                             if ((tmp & SRS15_18V_ENABLE) == MMC_CLEAR)
3428                             {
3429                                 ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3430                             }
3431                             else
3432                             {
3433                                 /* Internal clock enable */
3434                                 tmp = MMC->SRS11;
3435                                 tmp |= (uint32_t)SRS11_INT_CLOCK_ENABLE;
3436                                 MMC->SRS11 = tmp;
3437                                 while (MMC_CLEAR == (MMC->SRS11 & SRS11_INT_CLOCK_STABLE));
3438 
3439                                 /* Enable sd clock */
3440                                 temp = MMC->SRS11;
3441                                 temp |= (uint32_t)SRS11_SD_CLOCK_ENABLE;
3442                                 MMC->SRS11 = temp;
3443                                 /* Wait 1ms */
3444                                 mmc_delay(DELAY_COUNT);
3445                                 /* If dat line is not 1111b return error */
3446                                 tmp = MMC->SRS09;
3447                                 if ((tmp & dat_level) != dat_level)
3448                                 {
3449                                     ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3450                                     response_status = TRANSFER_IF_FAIL;
3451                                 }
3452                                 else
3453                                 {
3454                                     ret_status = MSS_MMC_TRANSFER_SUCCESS;
3455                                 }
3456                             }
3457                         }
3458                     }
3459                 }
3460 
3461                 if ((TRANSFER_IF_SUCCESS == response_status) && (ret_status == MSS_MMC_TRANSFER_SUCCESS))
3462                 {
3463                     response_status = cif_send_cmd(MMC_CLEAR,
3464                                                     MMC_CMD_2_ALL_SEND_CID,
3465                                                     MSS_MMC_RESPONSE_R2);
3466                     if (TRANSFER_IF_SUCCESS == response_status)
3467                     {
3468 
3469                         response_status = cif_send_cmd(MMC_CLEAR,
3470                                                     MMC_CMD_3_SET_RELATIVE_ADDR,
3471                                                     MSS_MMC_RESPONSE_R6);
3472 
3473                         sdcard_RCA = ((MMC->SRS04 >> SHIFT_16BIT) & MASK_16BIT);
3474 
3475                         if ((S18A == MMC_CLEAR) && (S18R != MMC_CLEAR))
3476                         {
3477                             sd_card_uhsi_supported();
3478                         }
3479 
3480                         if (TRANSFER_IF_SUCCESS == response_status)
3481                         {
3482                             /* Read CSD register from device */
3483                             response_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
3484                                                         MMC_CMD_9_SEND_CSD,
3485                                                         MSS_MMC_RESPONSE_R2);
3486                             /* Sector size from "Max. write data block length"  of CSD[25:22]*/
3487                             csd_max_sector_lwr  = MMC->SRS04 & SECT_SIZE_CSD_MASK;
3488                             max_sector_len = csd_max_sector_lwr >> SECT_SIZE_CSD_SHIFT;
3489                             sector_size = (uint16_t)((uint32_t)MMC_SET << max_sector_len);
3490                         }
3491 
3492                         if (TRANSFER_IF_SUCCESS == response_status)
3493                         {
3494                             response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
3495                                                     MMC_CMD_7_SELECT_DESELECT_CARD,
3496                                                     MSS_MMC_RESPONSE_R1B);
3497                             if(TRANSFER_IF_FAIL != response_status)
3498                             {
3499                                 response_status = check_device_status(response_status);
3500                             }
3501                         }
3502 
3503                         if (TRANSFER_IF_SUCCESS == response_status)
3504                         {
3505                             /* Disable host normal interrupts for masking  incorrect interrupts
3506                                 that may occur while changing the bus width.*/
3507                             tmp = MMC->SRS13;
3508                             MMC->SRS13 = tmp & ~(uint32_t)SRS13_CARD_INTERRUPT_STAT_EN;
3509                             mmc_delay(DELAY_COUNT);
3510                             response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
3511                                                                 SD_CMD_55,
3512                                                             MSS_MMC_RESPONSE_R1);
3513                             if (TRANSFER_IF_SUCCESS == response_status)
3514                             {
3515                                 if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_4BIT)
3516                                 {
3517                                     /* 4-bit bus data width */
3518                                     bus_width = SHIFT_2BIT;
3519                                 }
3520                                 else
3521                                 {
3522                                     /* 1-bit bus data width */
3523                                     bus_width = MMC_CLEAR;
3524                                 }
3525                                 /* Set bus with in the card 4-bit -2, 1-bit - 0 */
3526                                 response_status = cif_send_cmd(bus_width,
3527                                                                 SD_ACMD_6,
3528                                                            MSS_MMC_RESPONSE_R1);
3529                                 if (TRANSFER_IF_SUCCESS == response_status)
3530                                 {
3531                                     if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_4BIT)
3532                                     {
3533                                         MMC->SRS10 |= SRS10_DATA_WIDTH_4BIT;
3534                                     }
3535                                     MMC->SRS13 = tmp;
3536                                     /* MMC init success */
3537                                     g_mmc_init_complete = MMC_SET;
3538                                     /* Get SCR register */
3539                                     ret_status = MSS_MMC_single_block_read(READ_SEND_SCR, scr_reg);
3540                                     if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
3541                                     {
3542                                         ret_status = set_sd_host_device_bus_mode(cfg);
3543                                         if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
3544                                         {
3545                                             /* Up the Host MMC clock frequency */
3546                                             set_host_sdclk(cfg->clk_rate);
3547 
3548                                             switch(cfg->bus_speed_mode)
3549                                             {
3550 
3551                                                 case MSS_SDCARD_MODE_SDR12:
3552                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_SDR12, cfg->clk_rate);
3553                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3554                                                     {
3555                                                         response_status = TRANSFER_IF_FAIL;
3556                                                     }
3557                                                     break;
3558                                                 case MSS_SDCARD_MODE_SDR25:
3559                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_SDR25, cfg->clk_rate);
3560                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3561                                                     {
3562                                                         response_status = TRANSFER_IF_FAIL;
3563                                                     }
3564                                                     break;
3565                                                 case MSS_SDCARD_MODE_SDR50:
3566                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_SDR50, cfg->clk_rate);
3567                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3568                                                     {
3569                                                         response_status = TRANSFER_IF_FAIL;
3570                                                     }
3571                                                     tmp = MMC->SRS17;
3572                                                     if (((tmp & SRS17_USE_TUNING_SDR50) != MMC_CLEAR) && (response_status != TRANSFER_IF_FAIL))
3573                                                     {
3574                                                         ret_status = sd_tuning();
3575                                                         if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3576                                                         {
3577                                                             response_status = TRANSFER_IF_FAIL;
3578                                                         }
3579                                                     }
3580                                                     break;
3581                                                 case MSS_SDCARD_MODE_SDR104:
3582                                                     ret_status = sd_tuning();
3583                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3584                                                     {
3585                                                         response_status = TRANSFER_IF_FAIL;
3586                                                     }
3587                                                     break;
3588                                                 case MSS_SDCARD_MODE_DDR50:
3589                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_DDR50, cfg->clk_rate);
3590                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3591                                                     {
3592                                                         response_status = TRANSFER_IF_FAIL;
3593                                                     }
3594                                                     break;
3595                                                 case MSS_MMC_PHY_DELAY_INPUT_HIGH_SPEED:
3596                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_HIGH_SPEED, cfg->clk_rate);
3597                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3598                                                     {
3599                                                         response_status = TRANSFER_IF_FAIL;
3600                                                     }
3601                                                     break;
3602 
3603                                                 default:
3604                                                     ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_DEFAULT_SPEED, cfg->clk_rate);
3605                                                     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
3606                                                     {
3607                                                         response_status = TRANSFER_IF_FAIL;
3608                                                     }
3609                                                     break;
3610                                             }
3611                                         }
3612                                         else
3613                                         {
3614                                             response_status = TRANSFER_IF_FAIL;
3615                                         }
3616                                     }
3617                                     else
3618                                     {
3619                                         response_status = TRANSFER_IF_FAIL;
3620                                     }
3621                                 }
3622                                 else
3623                                 {
3624                                     response_status = TRANSFER_IF_FAIL;
3625                                 }
3626                             }
3627                             else
3628                             {
3629                                 MMC->SRS13 = tmp;
3630                             }
3631                         }
3632                     }
3633                 }
3634             }
3635         }
3636     }
3637 
3638     if (TRANSFER_IF_SUCCESS == response_status)
3639     {
3640         ret_status = MSS_MMC_TRANSFER_SUCCESS;
3641     }
3642     else
3643     {
3644         ret_status = MSS_MMC_TRANSFER_FAIL;
3645     }
3646     return(ret_status);
3647 }
3648 /*****************************SDIO START***************************************/
3649 /******************************************************************************/
sdio_oper_config(const mss_mmc_cfg_t * cfg)3650 static mss_mmc_status_t sdio_oper_config(const mss_mmc_cfg_t * cfg)
3651 {
3652     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
3653     cif_response_t response_status;
3654     uint32_t temp;
3655     uint32_t power_up_status;
3656     uint32_t scr_reg[BYTES_2];
3657     uint32_t bus_width;
3658     uint32_t tmp, argument;
3659 
3660     uint32_t S18A;
3661     uint8_t S18R;
3662 
3663     uint32_t card_ocr_reg = MASK_24BIT;
3664     uint32_t card_volt = MMC_CLEAR;
3665     uint32_t controller_volt = MMC_CLEAR;
3666 
3667     /* Check if UHS-I is supported by SDIO host controller, then set to 1 */
3668     S18R = (is_uhsi_supported() != MMC_CLEAR) ? MMC_SET : MMC_CLEAR;
3669 
3670     response_status = cif_send_cmd(MMC_CLEAR, SD_CMD_5, MSS_MMC_RESPONSE_R4);
3671     if (TRANSFER_IF_SUCCESS == response_status)
3672     {
3673          /* Read OCR register */
3674         card_ocr_reg = MMC->SRS04;
3675 
3676         if ((cfg->bus_speed_mode == MSS_SDCARD_MODE_DEFAULT_SPEED) ||
3677                     (cfg->bus_speed_mode == MSS_SDCARD_MODE_HIGH_SPEED))
3678         {
3679             S18R = MMC_CLEAR;
3680         }
3681         /* Check the voltage capabilities of the SDIO host controller and a card
3682            to set appropriate voltage */
3683         if ((card_ocr_reg & SDCARD_REG_OCR_3_3_3_4) != MMC_CLEAR)
3684         {
3685             card_volt = (uint32_t)SDCARD_REG_OCR_3_3_3_4;
3686             controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3687         }
3688         else if ((card_ocr_reg & SDCARD_REG_OCR_3_2_3_3) != MMC_CLEAR)
3689         {
3690             card_volt = (uint32_t)SDCARD_REG_OCR_3_2_3_3;
3691             controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3692         }
3693         else if ((card_ocr_reg & SDCARD_REG_OCR_3_0_3_1) != MMC_CLEAR)
3694         {
3695             card_volt = (uint32_t)SDCARD_REG_OCR_3_0_3_1;
3696             controller_volt = SRS10_SET_3_0V_BUS_VOLTAGE;
3697         }
3698         else if ((card_ocr_reg & SDCARD_REG_OCR_2_9_3_0) != MMC_CLEAR)
3699         {
3700             card_volt = (uint32_t)SDCARD_REG_OCR_2_9_3_0;
3701             controller_volt = SRS10_SET_3_0V_BUS_VOLTAGE;
3702         }
3703         else
3704         {
3705             card_volt = (uint32_t)SDCARD_REG_OCR_3_3_3_4;
3706             controller_volt = SRS10_SET_3_3V_BUS_VOLTAGE;
3707         }
3708         /* If the voltage is different to 3.3v */
3709         if (controller_volt != SRS10_SET_3_3V_BUS_VOLTAGE)
3710         {
3711             set_sdhost_power(controller_volt);
3712         }
3713 
3714         argument = card_volt;
3715 
3716         if (S18R != MMC_CLEAR)
3717         {
3718             argument |= (uint32_t)SDCARD_REG_OCR_S18R;
3719         }
3720 
3721         ret_status = MSS_MMC_TRANSFER_SUCCESS;
3722 
3723         /* Read OCR register from SD card*/
3724         do
3725         {
3726             mmc_delay(DELAY_COUNT);
3727             response_status = cif_send_cmd(argument, SD_CMD_5, MSS_MMC_RESPONSE_R4);
3728 
3729         }while ((MMC->SRS04 & SDCARD_REG_OCR_READY) == MMC_CLEAR);
3730 
3731         S18A = MMC->SRS04 & SDCARD_REG_OCR_S18A;
3732         /* UHI -I Support */
3733         if ((S18A != MMC_CLEAR) && (TRANSFER_IF_SUCCESS == response_status))
3734         {
3735             if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_4BIT)
3736             {
3737                 MMC->SRS10 |= SRS10_DATA_WIDTH_4BIT;
3738             }
3739             else
3740             {
3741                 return MSS_MMC_MODE_NOT_SUPPORT_DATAWIDTH;
3742             }
3743             const uint32_t dat_level = (SRS9_DAT0_SIGNAL_LEVEL | SRS9_DAT1_SIGNAL_LEVEL
3744                                       | SRS9_DAT2_SIGNAL_LEVEL | SRS9_DAT3_SIGNAL_LEVEL);
3745 
3746             response_status = cif_send_cmd(MMC_CLEAR,
3747                                         SD_CMD_11_VOLAGE_SWITCH,
3748                                         MSS_MMC_RESPONSE_R1);
3749             if (TRANSFER_IF_SUCCESS == response_status)
3750             {
3751                 /* Disable sd clock */
3752                 temp = MMC->SRS11;
3753                 temp &= ~(uint32_t)SRS11_SD_CLOCK_ENABLE;
3754                 MMC->SRS11 = temp;
3755                 /* If dat line is not 0000b return error */
3756                 tmp = MMC->SRS09;
3757                 if ((tmp & dat_level) != MMC_CLEAR)
3758                 {
3759                     ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3760                 }
3761                 else
3762                 {
3763                     /* 1.8V signal enable */
3764                     tmp = MMC->SRS15;
3765                     tmp |= SRS15_18V_ENABLE;
3766                     MMC->SRS15 = tmp;
3767 
3768                     /* wait 5ms */
3769                     mmc_delay(DELAY_COUNT);
3770                     mmc_delay(DELAY_COUNT);
3771                     mmc_delay(DELAY_COUNT);
3772                     mmc_delay(DELAY_COUNT);
3773                     /* If 1.8V signal enable is cleared by host return with error */
3774                     tmp = MMC->SRS15;
3775                     if ((tmp & SRS15_18V_ENABLE) == MMC_CLEAR)
3776                     {
3777                         ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3778                     }
3779                     else
3780                     {
3781                         /* Internal clock enable */
3782                         tmp = MMC->SRS11;
3783                         tmp |= (uint32_t)SRS11_INT_CLOCK_ENABLE;
3784                         MMC->SRS11 = tmp;
3785                         while (MMC_CLEAR == (MMC->SRS11 & SRS11_INT_CLOCK_STABLE));
3786 
3787                         /* Enable sd clock */
3788                         temp = MMC->SRS11;
3789                         temp |= (uint32_t)SRS11_SD_CLOCK_ENABLE;
3790                         MMC->SRS11 = temp;
3791                         /* Wait 1ms */
3792                         mmc_delay(DELAY_COUNT);
3793                         mmc_delay(DELAY_COUNT);
3794                         /* If dat line is not 1111b return error */
3795                         tmp = MMC->SRS09;
3796                         if ((tmp & dat_level) != dat_level)
3797                         {
3798                             ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
3799                             response_status = TRANSFER_IF_FAIL;
3800                         }
3801                         else
3802                         {
3803                             ret_status = MSS_MMC_TRANSFER_SUCCESS;
3804                         }
3805                     }
3806                 }
3807             }
3808 
3809         }
3810         if ((TRANSFER_IF_SUCCESS == response_status) &&
3811                 (ret_status == MSS_MMC_TRANSFER_SUCCESS))
3812         {
3813 
3814             response_status = cif_send_cmd(MMC_CLEAR,
3815                                 MMC_CMD_3_SET_RELATIVE_ADDR,
3816                                 MSS_MMC_RESPONSE_R6);
3817 
3818             sdcard_RCA = ((MMC->SRS04 >> SHIFT_16BIT) & MASK_16BIT);
3819 
3820             if ((S18A == MMC_CLEAR) && (S18R != MMC_CLEAR))
3821             {
3822                 sd_card_uhsi_supported();
3823             }
3824             cif_send_cmd(sdcard_RCA << SHIFT_16BIT,
3825                                         MMC_CMD_7_SELECT_DESELECT_CARD,
3826                                         MSS_MMC_RESPONSE_R1B);
3827             {
3828                 uint8_t dum_tmp;
3829                 uint8_t tmp_1;
3830                 uint8_t card_int_stat;
3831                 /* Disable host normal interrupts for masking  incorrect interrupts
3832                    that may occur while changing the bus width.*/
3833                 dum_tmp = MMC->SRS13;
3834                 MMC->SRS13 = dum_tmp & ~(uint32_t)SRS13_CARD_INTERRUPT_STAT_EN;
3835                 mmc_delay(DELAY_COUNT);
3836 
3837                 /* Read status of the card interrupt register */
3838                 sdio_host_access_cccr(SDIOHOST_CCCR_READ, &card_int_stat,
3839                                 sizeof(card_int_stat), MSS_MMC_CCCR_INT_ENABLE, MMC_CLEAR);
3840 
3841                 /* Clear interrupt enable master bit */
3842                 if ((card_int_stat & CARD_INT_STATUS_MASK) != MMC_CLEAR)
3843                 {
3844                     tmp_1 = card_int_stat & CARD_INT_STATUS_MASK;
3845                     /* Disable all card interrupts */
3846                     sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &tmp_1,
3847                                          sizeof(tmp_1), MSS_MMC_CCCR_INT_ENABLE, MMC_CLEAR);
3848                 }
3849 
3850                 /* Read bus interface control */
3851                 sdio_host_access_cccr(SDIOHOST_CCCR_READ, &tmp_1,
3852                                         sizeof(tmp_1), MSS_MMC_CCCR_BUS_CONTROL, MMC_CLEAR);
3853 
3854                 if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_1BIT)
3855                 {
3856                     tmp_1 = (tmp_1 & SDCARD_BUSWIDTH_MASK) | SDCARD_BIS_BUS_WIDTH_1BIT;
3857                 }
3858                 else
3859                 {
3860                     tmp_1 = (tmp_1 & SDCARD_BUSWIDTH_MASK) | SDCARD_BIS_BUS_WIDTH_4BIT;
3861                 }
3862 
3863                 /* Set bus width in the SDIO card */
3864                 sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &tmp_1,
3865                                          sizeof(tmp_1), MSS_MMC_CCCR_BUS_CONTROL, MMC_CLEAR);
3866 
3867 
3868                 if (cfg->data_bus_width == MSS_MMC_DATA_WIDTH_4BIT)
3869                 {
3870                     MMC->SRS10 |= SRS10_DATA_WIDTH_4BIT;
3871                 }
3872                 /* Check if the interrupts was enabled before */
3873                 if ((card_int_stat & CARD_INT_STATUS_MASK) != MMC_CLEAR)
3874                 {
3875                     /* Resume card interrupts state */
3876                     sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &card_int_stat,
3877                                 sizeof(card_int_stat), MSS_MMC_CCCR_INT_ENABLE, MMC_CLEAR);
3878                 }
3879                 uint16_t blck_size = BLK_SIZE;
3880                 /* Set block size 512 in the SDIO card for Function 0 */
3881                 sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &blck_size,
3882                                  sizeof(blck_size), MSS_MMC_CCCR_FN0_BLOCK_SIZE, MMC_CLEAR);
3883 
3884                 MMC->SRS13 = dum_tmp;
3885 
3886                 uint16_t manufacturerCode, manufacturer_information;
3887                 uint8_t buffer[BYTES_4];
3888                 uint32_t common_cis_address;
3889                 /* Get CIS pointer */
3890                 sdio_host_access_cccr(SDIOHOST_CCCR_READ,
3891                                         &common_cis_address,
3892                                         sizeof(common_cis_address),
3893                                         MSS_MMC_CCCR_CIS_POINTER,
3894                                         MMC_CLEAR);
3895                 /* Get manufacturer ID and manufacturer informations */
3896                 sdio_host_get_tuple_from_cis(common_cis_address,
3897                                             MSS_MMC_TUPLE_CISTPL_MANFID,
3898                                             buffer, sizeof(buffer));
3899 
3900                 manufacturerCode = buffer[MMC_CLEAR] | ((uint16_t)buffer[BYTES_1] << SHIFT_8BIT);
3901                 manufacturer_information = buffer[BYTES_2] | ((uint16_t)buffer[BYTES_3] << SHIFT_8BIT);
3902 
3903                 ret_status = change_sdio_device_bus_mode(cfg);
3904                 if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
3905                 {
3906                     uint8_t sdio_csa_enable = SDIO_CSA_ENABLE;
3907                     uint8_t sdio_csa_support;
3908                     uint8_t fun_num = BYTES_2;  /* function 1 */
3909 
3910                     /* Up the Host MMC clock frequency */
3911                     set_host_sdclk(cfg->clk_rate);
3912                     mmc_delay(MASK_8BIT);
3913                     sdio_host_access_fbr(SDIOHOST_CCCR_READ,  &sdio_csa_support, BYTES_1,
3914                                                    MSS_MMC_FBR_STD_SDIO_FN, MMC_SET, MMC_CLEAR);
3915                     if (sdio_csa_support & SDIO_CSA_SUPPORT != MMC_CLEAR)
3916                     {
3917                         sdio_host_access_fbr(SDIOHOST_CCCR_WRITE,  &sdio_csa_enable, BYTES_1,
3918                                                    MSS_MMC_FBR_STD_SDIO_FN, MMC_SET, MMC_SET);
3919                         sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &fun_num, BYTES_1,
3920                                                         MSS_MMC_CCCR_IO_ENABLE, MMC_SET);
3921                         sdio_host_access_cccr(SDIOHOST_CCCR_READ, &fun_num, BYTES_1,
3922                                                 MSS_MMC_CCCR_IO_READY, MMC_CLEAR);
3923                         while(fun_num == MMC_CLEAR)
3924                         {
3925                             sdio_host_access_cccr(SDIOHOST_CCCR_READ, &fun_num, BYTES_1,
3926                                                         MSS_MMC_CCCR_IO_READY, MMC_CLEAR);
3927                         }
3928                         sdio_host_access_fbr(SDIOHOST_CCCR_WRITE,  &blck_size, BYTES_2,
3929                                             MSS_MMC_FBR_BLOCK_SIZE, MMC_SET, MMC_CLEAR);
3930                         /* SDIO init success */
3931                         g_mmc_init_complete = MMC_SET;
3932                     }
3933                     else
3934                     {
3935                         response_status = TRANSFER_IF_FAIL;
3936                     }
3937                 }
3938                 else
3939                 {
3940                     response_status = TRANSFER_IF_FAIL;
3941                 }
3942             }
3943         }
3944     }
3945 
3946     if (TRANSFER_IF_SUCCESS == response_status)
3947     {
3948         ret_status = MSS_MMC_TRANSFER_SUCCESS;
3949     }
3950     else
3951     {
3952         ret_status = MSS_MMC_TRANSFER_FAIL;
3953     }
3954     return(ret_status);
3955 }
3956 
3957 /******************************************************************************/
change_sdio_device_bus_mode(const mss_mmc_cfg_t * cfg)3958 static mss_mmc_status_t change_sdio_device_bus_mode(const mss_mmc_cfg_t * cfg)
3959 {
3960     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
3961     uint8_t high_speed_reg, uhsi_support;
3962     uint8_t enable_high_speed = MMC_CLEAR;
3963     uint32_t tmp;
3964     /* Get high speed register from a card */
3965     sdio_host_access_cccr(SDIOHOST_CCCR_READ, &high_speed_reg,
3966                                 sizeof(high_speed_reg),
3967                                 MSS_MMC_CCCR_HIGH_SPEED,
3968                                 MMC_CLEAR);
3969 
3970     /* Clear all access mode settings */
3971     high_speed_reg &= ~SDIO_CCCR_13_BSS_MASK;
3972 
3973     if (cfg->bus_speed_mode > MSS_SDCARD_MODE_SDR25)
3974     {
3975         sdio_host_access_cccr(SDIOHOST_CCCR_READ, &uhsi_support,
3976                                     sizeof(uhsi_support),
3977                                     MSS_MMC_CCCR_UHSI_SUPPORT,
3978                                     MMC_CLEAR);
3979     }
3980 
3981     switch (cfg->bus_speed_mode)
3982     {
3983     case MSS_SDCARD_MODE_SDR12:
3984     case MSS_SDCARD_MODE_DEFAULT_SPEED:
3985         break;
3986     case MSS_SDCARD_MODE_SDR25:
3987     case MSS_SDCARD_MODE_HIGH_SPEED:
3988         /* Check if card supports SDR25 mode (high speed) */
3989         if (MMC_CLEAR == (high_speed_reg & SDIO_CCCR_13_SHS))
3990         {
3991             return MSS_MMC_SDIO_ERR_BUS_SPEED_UNSUPP;
3992         }
3993         high_speed_reg |= SDIO_CCCR_13_EHS;
3994         enable_high_speed = MMC_SET;
3995         break;
3996     case MSS_SDCARD_MODE_SDR50:
3997         /* Check if card supports SDR50 access mode */
3998         if (MMC_CLEAR == (uhsi_support & SDIO_CCCR_14_SSDR50))
3999         {
4000             return MSS_MMC_SDIO_ERR_BUS_SPEED_UNSUPP;
4001         }
4002         high_speed_reg |= SDIO_CCCR_13_BSS_SDR50;
4003         enable_high_speed = MMC_SET;
4004         break;
4005     case MSS_SDCARD_MODE_SDR104:
4006         /* Check if card supports SDR104 access mode */
4007         if (MMC_CLEAR == (uhsi_support & SDIO_CCCR_14_SSDR104))
4008         {
4009             return MSS_MMC_SDIO_ERR_BUS_SPEED_UNSUPP;
4010         }
4011         high_speed_reg |= SDIO_CCCR_13_BSS_SDR104;
4012         enable_high_speed = MMC_SET;
4013         break;
4014     case MSS_SDCARD_MODE_DDR50:
4015         /* Check if card supports DDR50 access mode */
4016         if (MMC_CLEAR == (uhsi_support & SDIO_CCCR_14_SDDR50))
4017         {
4018             return MSS_MMC_SDIO_ERR_BUS_SPEED_UNSUPP;
4019         }
4020         high_speed_reg |= SDIO_CCCR_13_BSS_DDR50;
4021         enable_high_speed = MMC_SET;
4022         break;
4023     default: /* Nothing */
4024         break;
4025 
4026     }
4027 
4028     /* Apply access bus mode to sdio card */
4029     sdio_host_access_cccr(SDIOHOST_CCCR_WRITE, &high_speed_reg,
4030                                 sizeof(high_speed_reg),
4031                                 MSS_MMC_CCCR_HIGH_SPEED,
4032                                 MMC_CLEAR);
4033 
4034     if (enable_high_speed != MMC_CLEAR)
4035     {
4036         /* Enable high-speed in the SDIO host controller */
4037         tmp = MMC->SRS10;
4038         tmp |= SRS10_HIGH_SPEED_ENABLE;
4039         MMC->SRS10 = tmp;
4040     }
4041     else
4042     {
4043         /* Disable high-speed in the SDIO host controller */
4044         tmp = MMC->SRS10;
4045         tmp &= ~SRS10_HIGH_SPEED_ENABLE;
4046         MMC->SRS10 = tmp;
4047     }
4048 
4049     return MSS_MMC_TRANSFER_SUCCESS;
4050 }
4051 /******************************************************************************/
sdio_host_access_cccr(uint8_t transfer_direction,void * data,uint8_t data_size,uint8_t register_address,uint8_t raw)4052 static void sdio_host_access_cccr
4053 (
4054     uint8_t transfer_direction,
4055     void *data,
4056     uint8_t data_size,
4057     uint8_t register_address,
4058     uint8_t raw
4059 )
4060 {
4061 
4062     uint8_t number_of_bytes, i = MMC_CLEAR;
4063     uint32_t argument, response, tmp = MMC_CLEAR;
4064     cif_response_t response_status = TRANSFER_IF_SUCCESS;
4065     /* Set numbers of bytes to transfer
4066        and check if the data parameter has appropriate size */
4067     switch (register_address) {
4068     case MSS_MMC_CCCR_CIS_POINTER:
4069         number_of_bytes = BYTES_3;
4070         if (data_size < BYTES_4) {
4071         }
4072         break;
4073     case MSS_MMC_CCCR_FN0_BLOCK_SIZE:
4074         if (data_size < BYTES_2) {
4075         }
4076         number_of_bytes = BYTES_2;
4077         break;
4078     default:
4079         if (data_size < BYTES_1) {
4080         }
4081         number_of_bytes = BYTES_1;
4082         break;
4083     }
4084 
4085     /* Read data from the CCCR register */
4086     if (transfer_direction == MMC_CLEAR)
4087     {
4088         for (i = MMC_CLEAR; i < number_of_bytes; i++)
4089         {
4090             /* Set address of register to read */
4091             argument = (uint32_t)((register_address + i) << SHIFT_9BIT)
4092                                 | (raw << SHIFT_27BIT)
4093                                 | (uint32_t)(transfer_direction << SHIFT_31BIT);
4094 
4095             /* Execute command CMD52 to read data /from CCCR register */
4096             response_status = cif_send_cmd(argument,
4097                                             SDIO_CMD_52_IO_RW_DIRECT,
4098                                             MSS_MMC_RESPONSE_R5);
4099             response = MMC->SRS04;
4100 
4101             tmp |= (response & MASK_8BIT) << (i * SHIFT_8BIT);
4102         }
4103 
4104         switch (register_address)
4105         {
4106         case MSS_MMC_CCCR_CIS_POINTER:
4107             *((uint32_t *)data) = (uint32_t)tmp;
4108             break;
4109         case MSS_MMC_CCCR_FN0_BLOCK_SIZE:
4110             *((uint16_t *)data) = (uint16_t)tmp;
4111             break;
4112         default:
4113             *((uint8_t *)data) = (uint8_t)tmp;
4114             break;
4115         }
4116     }
4117     /* Write data to the CCCR register */
4118     else
4119     {
4120         uint8_t *data_byte = data;
4121         for (i = MMC_CLEAR; i < number_of_bytes; i++)
4122         {
4123             /* Set address of register to write */
4124             argument = (uint32_t)((register_address + i) << SHIFT_9BIT)
4125                                 | (raw << SHIFT_27BIT)
4126                                 | (uint32_t)(transfer_direction << SHIFT_31BIT)
4127                                 | *data_byte++;
4128 
4129             /* Execute command CMD52 to write data to CCCR register */
4130             response_status = cif_send_cmd(argument,
4131                                         SDIO_CMD_52_IO_RW_DIRECT,
4132                                         MSS_MMC_RESPONSE_R5);
4133         }
4134     }
4135 }
4136 /******************************************************************************/
sdio_host_access_fbr(uint8_t transfer_direction,void * data,uint8_t data_size,uint32_t register_address,uint8_t fun_num,uint8_t raw)4137 static void sdio_host_access_fbr
4138 (
4139     uint8_t transfer_direction,
4140     void *data,
4141     uint8_t data_size,
4142     uint32_t register_address,
4143     uint8_t fun_num,
4144     uint8_t raw
4145 )
4146 {
4147 
4148     uint8_t number_of_bytes, i = MMC_CLEAR;
4149     uint32_t argument, response, tmp = MMC_CLEAR;
4150     cif_response_t response_status = TRANSFER_IF_SUCCESS;
4151     /* Set numbers of bytes to transfer
4152        and check if the data parameter has appropriate size */
4153     switch (register_address) {
4154     case MSS_MMC_FBR_ADDR_CIS:
4155     case MSS_MMC_FBR_ADDR_CSA:
4156         number_of_bytes = BYTES_3;
4157         if (data_size < BYTES_4) {
4158         }
4159         break;
4160     case MSS_MMC_FBR_BLOCK_SIZE:
4161         if (data_size < BYTES_2) {
4162         }
4163         number_of_bytes = BYTES_2;
4164         break;
4165     default:
4166         if (data_size < BYTES_1) {
4167         }
4168         number_of_bytes = BYTES_1;
4169         break;
4170     }
4171     if (fun_num == MMC_CLEAR)
4172     {
4173         register_address = register_address + SDIO_FBR_BASE_ADDR;
4174     }
4175     else
4176     {
4177         register_address = register_address + (SDIO_FBR_BASE_ADDR * fun_num);
4178     }
4179     /* Read data from the CCCR register */
4180     if (transfer_direction == MMC_CLEAR)
4181     {
4182         for (i = MMC_CLEAR; i < number_of_bytes; i++)
4183         {
4184             /* Set address of register to read */
4185             argument = (uint32_t)((register_address + i) << SHIFT_9BIT)
4186                                 | (raw << SHIFT_27BIT)
4187                                 | (uint32_t)(transfer_direction << SHIFT_31BIT);
4188 
4189             /* Execute command CMD52 to read data /from CCCR register */
4190             response_status = cif_send_cmd(argument,
4191                                             SDIO_CMD_52_IO_RW_DIRECT,
4192                                             MSS_MMC_RESPONSE_R5);
4193             response = MMC->SRS04;
4194 
4195             tmp |= (response & MASK_8BIT) << (i * SHIFT_8BIT);
4196         }
4197 
4198         switch (register_address)
4199         {
4200         case MSS_MMC_FBR_ADDR_CIS:
4201         case MSS_MMC_FBR_ADDR_CSA:
4202             *((uint32_t *)data) = (uint32_t)tmp;
4203             break;
4204         case MSS_MMC_FBR_BLOCK_SIZE:
4205             *((uint16_t *)data) = (uint16_t)tmp;
4206             break;
4207         default:
4208             *((uint8_t *)data) = (uint8_t)tmp;
4209             break;
4210         }
4211     }
4212     /* Write data to the CCCR register */
4213     else
4214     {
4215         uint8_t *data_byte = data;
4216         for (i = MMC_CLEAR; i < number_of_bytes; i++)
4217         {
4218             /* Set address of register to write */
4219             argument = (uint32_t)((register_address + i) << SHIFT_9BIT)
4220                                 | (raw << SHIFT_27BIT)
4221                                 | (uint32_t)(transfer_direction << SHIFT_31BIT)
4222                                 | *data_byte++;
4223 
4224             /* Execute command CMD52 to write data to CCCR register */
4225             response_status = cif_send_cmd(argument,
4226                                         SDIO_CMD_52_IO_RW_DIRECT,
4227                                         MSS_MMC_RESPONSE_R5);
4228         }
4229     }
4230 }
4231 /******************************************************************************/
sdio_host_get_tuple_from_cis(uint32_t tuple_address,uint8_t tuple_code,uint8_t * buffer,uint8_t buffer_size)4232 static void sdio_host_get_tuple_from_cis
4233 (
4234     uint32_t tuple_address,
4235     uint8_t tuple_code,
4236     uint8_t *buffer,
4237     uint8_t buffer_size
4238 )
4239 {
4240     uint32_t argument, response;
4241     uint8_t i;
4242     uint8_t next_tuple_offset;
4243     cif_response_t response_status = TRANSFER_IF_SUCCESS;
4244 
4245     argument = (tuple_address << SHIFT_9BIT);
4246     while (MMC_SET)
4247     {
4248         uint8_t read_tuple_code;
4249         /* Read tuple code name */
4250         response_status = cif_send_cmd(argument,
4251                                         SDIO_CMD_52_IO_RW_DIRECT,
4252                                         MSS_MMC_RESPONSE_R5);
4253         response = MMC->SRS04;
4254         if ((response & MASK_8BIT) == MSS_MMC_TUPLE_CISTPL_END)
4255         {
4256            /* SDIO ERR TUPLE NOT FOUND */
4257         }
4258         read_tuple_code = response & MASK_8BIT;
4259 
4260         tuple_address++;
4261         argument = tuple_address << SHIFT_9BIT;
4262         /* Read link to next tuple */
4263         response_status = cif_send_cmd(argument,
4264                                         SDIO_CMD_52_IO_RW_DIRECT,
4265                                         MSS_MMC_RESPONSE_R5);
4266         response = MMC->SRS04;
4267         if ((response & MASK_8BIT) == MSS_MMC_TUPLE_CISTPL_END)
4268         {
4269             /* SDIO ERR TUPLE NOT FOUND */
4270         }
4271 
4272         /* Save size of tuple body */
4273         next_tuple_offset = response & MASK_8BIT;
4274         tuple_address++;
4275 
4276         if (read_tuple_code == tuple_code)
4277         {
4278             if (buffer_size < next_tuple_offset)
4279             {
4280                 /* To small buffer for data */
4281             }
4282 
4283             for (i = MMC_CLEAR; i < next_tuple_offset; i++)
4284             {
4285                 argument = (tuple_address + i) << SHIFT_9BIT;
4286                 /* Read tuple body */
4287                 response_status = cif_send_cmd(argument,
4288                                                 SDIO_CMD_52_IO_RW_DIRECT,
4289                                                 MSS_MMC_RESPONSE_R5);
4290                 response = MMC->SRS04;
4291 
4292                 buffer[i] = (uint8_t)(response & MASK_8BIT);
4293             }
4294             break;
4295         }
4296         else
4297         {
4298             tuple_address += next_tuple_offset;
4299             argument = tuple_address << SHIFT_9BIT;
4300         }
4301     }
4302 
4303 }
4304 /*****************************SDIO END*****************************************/
4305 /******************************************************************************/
set_sd_host_device_bus_mode(const mss_mmc_cfg_t * cfg)4306 static mss_mmc_status_t set_sd_host_device_bus_mode(const mss_mmc_cfg_t * cfg)
4307 {
4308     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4309     uint8_t card_access_mode;
4310     uint8_t card_driver_strength = SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_B;
4311     switch (cfg->bus_speed_mode)
4312     {
4313     case (uint8_t)MSS_SDCARD_MODE_SDR12:
4314     case (uint8_t)MSS_SDCARD_MODE_DEFAULT_SPEED:
4315         card_access_mode = SDCARD_SWITCH_ACCESS_MODE_SDR12;
4316         break;
4317     case (uint8_t)MSS_SDCARD_MODE_HIGH_SPEED:
4318     case (uint8_t)MSS_SDCARD_MODE_SDR25:
4319         card_access_mode = SDCARD_SWITCH_ACCESS_MODE_SDR25;
4320         break;
4321     case (uint8_t)MSS_SDCARD_MODE_SDR50:
4322         card_access_mode = SDCARD_SWITCH_ACCESS_MODE_SDR50;
4323         break;
4324     case (uint8_t)MSS_SDCARD_MODE_SDR104:
4325         card_access_mode = SDCARD_SWITCH_ACCESS_MODE_SDR104;
4326         break;
4327     case (uint8_t)MSS_SDCARD_MODE_DDR50:
4328         card_access_mode = SDCARD_SWITCH_ACCESS_MODE_DDR50;
4329         break;
4330     default:
4331         ret_status = MSS_MMC_INVALID_PARAMETER;
4332         break;
4333     }
4334     if (ret_status == MSS_MMC_NO_ERROR)
4335     {
4336         ret_status= sd_host_process_switch_function(card_access_mode, SDCARD_SWITCH_GROUP_NR_1);
4337         if (ret_status == MSS_MMC_TRANSFER_SUCCESS)
4338         {
4339             ret_status = set_host_uhsi_mode(cfg->bus_speed_mode, card_driver_strength);
4340         }
4341     }
4342     return ret_status;
4343 }
4344 /******************************************************************************/
set_host_uhsi_mode(uint8_t access_mode,uint8_t driver_strengh)4345 static mss_mmc_status_t set_host_uhsi_mode
4346 (
4347     uint8_t access_mode,
4348     uint8_t driver_strengh
4349 )
4350 {
4351     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4352     uint32_t tmp;
4353     uint32_t uhs_mode;
4354     uint8_t enable_high_speed = MMC_CLEAR;
4355 
4356     switch (access_mode) {
4357     case (uint8_t)MSS_SDCARD_MODE_SDR12:
4358     case (uint8_t)MSS_SDCARD_MODE_DEFAULT_SPEED:
4359         uhs_mode = SRS15_UHS_MODE_SDR12;
4360         break;
4361     case (uint8_t)MSS_SDCARD_MODE_SDR25:
4362     case (uint8_t)MSS_SDCARD_MODE_HIGH_SPEED:
4363         uhs_mode = SRS15_UHS_MODE_SDR25;
4364         enable_high_speed = MMC_SET;
4365         break;
4366     case (uint8_t)MSS_SDCARD_MODE_SDR50:
4367         uhs_mode = SRS15_UHS_MODE_SDR50;
4368         enable_high_speed = MMC_SET;
4369         break;
4370     case (uint8_t)MSS_SDCARD_MODE_SDR104:
4371         uhs_mode = SRS15_UHS_MODE_SDR104;
4372         enable_high_speed = MMC_SET;
4373         break;
4374     case (uint8_t)MSS_SDCARD_MODE_DDR50:
4375         uhs_mode = SRS15_UHS_MODE_DDR50;
4376         enable_high_speed = MMC_SET;
4377         break;
4378     default:
4379         ret_status = MSS_MMC_INVALID_PARAMETER;
4380         break;
4381     }
4382 
4383     if (ret_status == MSS_MMC_NO_ERROR)
4384     {
4385         uint32_t SRS15 = MMC->SRS15;
4386 
4387         SRS15 &= ~SRS15_DRIVER_TYPE_MASK;
4388 
4389         switch (driver_strengh) {
4390         case SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_A:
4391             SRS15 |= SRS15_DRIVER_TYPE_A;
4392             break;
4393         case SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_B:
4394             SRS15 |= SRS15_DRIVER_TYPE_B;
4395             break;
4396         case SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_C:
4397             SRS15 |= SRS15_DRIVER_TYPE_C;
4398             break;
4399         case SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_D:
4400             SRS15 |= SRS15_DRIVER_TYPE_D;
4401             break;
4402         default:
4403             /* nothing */
4404             break;
4405         }
4406 
4407         MMC->SRS15 = SRS15;
4408 
4409         if (enable_high_speed != MMC_CLEAR)
4410         {
4411             /* Enable high-speed in the SDIO host controller */
4412             tmp = MMC->SRS10;
4413             tmp |= SRS10_HIGH_SPEED_ENABLE;
4414             MMC->SRS10 = tmp;
4415         }
4416         else
4417         {
4418             /* Disable high-speed in the SDIO host controller */
4419             tmp = MMC->SRS10;
4420             tmp &= ~SRS10_HIGH_SPEED_ENABLE;
4421             MMC->SRS10 = tmp;
4422         }
4423 
4424         tmp = MMC->SRS15;
4425         tmp &= ~SRS15_UHS_MODE_MASK;
4426         tmp |= uhs_mode;
4427         MMC->SRS15 = tmp;
4428         ret_status = MSS_MMC_TRANSFER_SUCCESS;
4429     }
4430 
4431     return (ret_status);
4432 }
4433 /******************************************************************************/
sd_host_process_switch_function(uint8_t function_num,uint8_t group_num)4434 static mss_mmc_status_t sd_host_process_switch_function
4435 (
4436     uint8_t function_num,
4437     uint8_t group_num
4438 )
4439 {
4440     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4441     uint8_t tmp_buffer[BLK_SIZE];
4442     uint32_t argument;
4443     uint32_t argumentBase = MMC_CLEAR;
4444 
4445     const uint32_t shift = (((uint32_t)group_num - MMC_SET) * SHIFT_4BIT);
4446 
4447     if (shift < SHIFT_32BIT)
4448     {
4449         argumentBase = (uint32_t)(MASK_24BIT & ~(MASK_4BIT << shift))
4450                        | ((uint32_t)function_num << shift);
4451     }
4452 
4453     argument = argumentBase | (uint32_t)SDCARD_SWITCH_FUNC_MODE_CHECK;
4454     /* First check if function is supported */
4455     ret_status = sd_host_exec_cmd6_command(argument, tmp_buffer, function_num, group_num);
4456     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
4457     {
4458         ret_status = MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE;
4459     }
4460     else if (SDCARD_SWICH_FUNC_GET_STAT_CODE(tmp_buffer, group_num) == MASK_4BIT)
4461     {
4462         /* If status code for function is 0xF
4463          then function is not supported by a card */
4464         ret_status = MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE;
4465     }
4466     else
4467     {
4468         argument = argumentBase | (uint32_t)SDCARD_SWITCH_FUNC_MODE_SWITCH;
4469         /* Execute command to switch function */
4470         ret_status = sd_host_exec_cmd6_command(argument, tmp_buffer, function_num, group_num);
4471         if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
4472         {
4473             ret_status = MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE;
4474         }
4475         else if (SDCARD_SWICH_FUNC_GET_STAT_CODE(tmp_buffer, group_num) != function_num) {
4476             /* Status indicates the same function number as specified in the argument,
4477                which means Supported function successful function change. */
4478 
4479             ret_status = MSS_MMC_SDCARD_CMD6_SWITCH_ERROR;
4480         } else {
4481             ret_status = MSS_MMC_TRANSFER_SUCCESS;
4482         }
4483     }
4484     return (ret_status);
4485 }
4486 /******************************************************************************/
sd_tuning(void)4487 static mss_mmc_status_t sd_tuning(void)
4488 {
4489     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4490     uint8_t repeat_count;
4491     uint32_t tmp;
4492     uint32_t read_pattern[BYTES_128];
4493     tmp = MMC->SRS15;
4494 
4495     /* Reset tuning unit */
4496     tmp &= ~SRS15_SAMPLING_CLOCK_SELECT;
4497     /* Start of tuning */
4498     tmp |= SRS15_EXECUTE_TUNING;
4499     MMC->SRS15 = tmp;
4500 
4501     repeat_count = BYTES_40;
4502     while ((tmp & SRS15_EXECUTE_TUNING) != MMC_CLEAR)
4503     {
4504         ret_status = read_tune_block(read_pattern, BYTES_64, SD_CMD_19_SEND_TUNING_BLK);
4505 
4506         if ((repeat_count == MMC_CLEAR) || (ret_status != MSS_MMC_TRANSFER_SUCCESS))
4507         {
4508             break;
4509         }
4510 
4511         tmp = MMC->SRS15;
4512         --repeat_count;
4513     }
4514 
4515     if ((ret_status == MSS_MMC_TRANSFER_SUCCESS) && ((tmp & SRS15_SAMPLING_CLOCK_SELECT) == MMC_CLEAR))
4516     {
4517         ret_status = MSS_MMC_SDCARD_TUNING_FAILED;
4518     }
4519 
4520     /* Tuning completed */
4521     return (ret_status);
4522 }
4523 /******************************************************************************/
sd_host_exec_cmd6_command(uint32_t argument,uint8_t * buffer,uint8_t function_num,uint8_t group_num)4524 static mss_mmc_status_t sd_host_exec_cmd6_command
4525 (
4526     uint32_t argument,
4527     uint8_t *buffer,
4528     uint8_t function_num,
4529     uint8_t group_num
4530 )
4531 {
4532     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4533     volatile uint32_t timeout = COMMANDS_TIMEOUT;
4534     uint8_t do_continue = MMC_SET;
4535     do
4536     {
4537         ret_status = cmd6_single_block_read(argument, (uint32_t *)buffer, BYTES_64);
4538         if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
4539         {
4540             break;
4541         }
4542         /* Check data structure version
4543            if it is 1 then checking the busy status is possible */
4544         if (buffer[17u] == MMC_SET)
4545         {
4546             /* If function is busy continue loop
4547                wait until function will be ready */
4548             if (SDCARD_SWICH_FUNC_GET_BUSY_STAT(buffer, group_num, function_num) == MMC_CLEAR)
4549             {
4550                 do_continue = MMC_CLEAR;
4551             }
4552         }
4553         else
4554         {
4555             do_continue = MMC_CLEAR;
4556         }
4557         --timeout;
4558     } while ((timeout != MMC_CLEAR) && (do_continue != MMC_CLEAR));
4559 
4560     if (timeout == MMC_CLEAR)
4561     {
4562         ret_status = MSS_MMC_TRANSFER_FAIL;
4563     } else {
4564         ret_status = MSS_MMC_TRANSFER_SUCCESS;
4565     }
4566     return ret_status;
4567 }
4568 /******************************************************************************/
sd_card_uhsi_supported(void)4569 static mss_mmc_status_t sd_card_uhsi_supported(void)
4570 {
4571     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4572     const uint8_t group_num = MMC_SET;
4573     uint8_t function_num = SDCARD_SWITCH_ACCESS_MODE_SDR50;
4574     uint32_t data_c6[BYTES_128];
4575     uint8_t *tmp_buffer = (uint8_t *)data_c6;
4576     uint32_t tmp;
4577     uint32_t argument = MMC_CLEAR;
4578     const uint32_t shift = ((group_num - MMC_SET) * SHIFT_4BIT);
4579 
4580     if (shift < SHIFT_32BIT)
4581     {
4582         argument = (uint32_t)(MASK_24BIT & ~(MASK_4BIT << shift))
4583                    | ((uint32_t)function_num << shift)
4584                    | (uint32_t)SDCARD_SWITCH_FUNC_MODE_CHECK;
4585     }
4586     ret_status = cmd6_single_block_read(argument, data_c6, BYTES_64);
4587     if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
4588     {
4589         ret_status = MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE;
4590     }
4591     else if (SDCARD_SWICH_FUNC_GET_STAT_CODE(tmp_buffer, group_num) == MASK_4BIT)
4592     {
4593         /* If status code for function is 0xF
4594          then function is not supported by a card */
4595         ret_status = MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE;
4596     }
4597     else if (SDCARD_SWICH_FUNC_GET_STAT_CODE(tmp_buffer, group_num) == function_num)
4598     {
4599         MMC->SRS10 |= SRS10_DATA_WIDTH_4BIT;
4600 
4601         /* Disable sd clock */
4602         tmp = MMC->SRS11;
4603         tmp &= ~(uint32_t)SRS11_SD_CLOCK_ENABLE;
4604         MMC->SRS11 = tmp;
4605         /* 1.8V signal enable */
4606         tmp = MMC->SRS15;
4607         tmp |= SRS15_18V_ENABLE;
4608         MMC->SRS15 = tmp;
4609 
4610         /* Wait 5ms */
4611         mmc_delay(DELAY_COUNT);
4612         mmc_delay(DELAY_COUNT);
4613 
4614         /* If 1.8V signal enable is cleared by host return with error */
4615         tmp = MMC->SRS15;
4616         if ((tmp & SRS15_18V_ENABLE) == MMC_CLEAR)
4617         {
4618              ret_status = MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED;
4619         }
4620         else
4621         {
4622             /* Internal clock enable */
4623             tmp = MMC->SRS11;
4624             tmp |= (uint32_t)SRS11_INT_CLOCK_ENABLE;
4625             MMC->SRS11 = tmp;
4626             while (MMC_CLEAR == (MMC->SRS11 & SRS11_INT_CLOCK_STABLE));
4627 
4628             /* Enable sd clock */
4629             tmp = MMC->SRS11;
4630             tmp |= (uint32_t)SRS11_SD_CLOCK_ENABLE;
4631             MMC->SRS11 = tmp;
4632             /* Wait 1ms */
4633             mmc_delay(DELAY_COUNT);
4634 
4635             ret_status = MSS_MMC_TRANSFER_SUCCESS;
4636         }
4637     }
4638     else
4639     {
4640         ret_status = MSS_MMC_TRANSFER_FAIL;
4641     }
4642     return (ret_status);
4643 }
4644 
4645 /******************************************************************************/
is_uhsi_supported(void)4646 static uint8_t is_uhsi_supported(void)
4647 {
4648     uint8_t result = MMC_SET;
4649     uint32_t tmp;
4650 
4651     tmp = MMC->SRS16;
4652 
4653     if ((tmp & SRS16_VOLTAGE_1_8V_SUPPORT) == MMC_CLEAR)
4654     {
4655         result = MMC_CLEAR;
4656     }
4657     else
4658     {
4659         tmp = MMC->SRS17;
4660 
4661         uint32_t uhsi_modes = (uint32_t)(SRS17_SDR50_SUPPORTED | SRS17_SDR104_SUPPORTED
4662                                         | SRS17_DDR50_SUPPORTED);
4663         if ((tmp & uhsi_modes) == MMC_CLEAR)
4664         {
4665             result = MMC_CLEAR;
4666         }
4667     }
4668     return (result);
4669 }
4670 /******************************************************************************/
set_device_hs400_mode(const mss_mmc_cfg_t * cfg)4671 static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg)
4672 {
4673     cif_response_t response_status = TRANSFER_IF_SUCCESS;
4674     uint32_t srs10, hrs6;
4675     uint32_t hs_timing = MMC_HS200_MODE;
4676     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4677     uint32_t csd_reg[BLK_SIZE/WORD_SIZE];
4678     uint8_t  *pcsd_reg;
4679 
4680     uint32_t hw_sec_count;
4681     uint8_t  hw_ext_csd_rev;
4682     uint8_t  hw_device_type;
4683     uint8_t  hw_hs_timing;
4684 
4685     uint32_t data_width = cfg->data_bus_width;
4686 
4687     if (MSS_MMC_DATA_WIDTH_8BIT != data_width)
4688     {
4689         ret_status = MSS_MMC_TRANSFER_FAIL;
4690         return ret_status;
4691     }
4692 
4693     /* Set 8-bit bus mode */
4694     srs10 = MMC->SRS10;
4695     srs10 |= SRS10_EXTENDED_DATA_TRANSFER_WIDTH;
4696     MMC->SRS10 = srs10;
4697     /* Do HS400 Mode Operation, not HS400_ES  */
4698     if (MSS_MMC_MODE_HS400 == cfg->bus_speed_mode)
4699     {
4700         /* Set MMC data bus width */
4701         response_status = cif_send_cmd(MMC_DW_CSD | (data_width << SHIFT_8BIT),
4702                                 MMC_CMD_6_SWITCH,
4703                                 MSS_MMC_RESPONSE_R1B);
4704         if (TRANSFER_IF_FAIL != response_status)
4705         {
4706             response_status = check_device_status(response_status);
4707         }
4708 
4709         if (TRANSFER_IF_SUCCESS == response_status)
4710         {
4711             hs_timing = MMC_HS200_MODE;
4712 
4713             response_status = cif_send_cmd(hs_timing,
4714                                    MMC_CMD_6_SWITCH,
4715                                    MSS_MMC_RESPONSE_R1B);
4716             if (TRANSFER_IF_FAIL != response_status)
4717             {
4718                 response_status = check_device_status(response_status);
4719             }
4720         }
4721 
4722         if (TRANSFER_IF_SUCCESS == response_status)
4723         {
4724             /* eMMC Mode select in Host controller */
4725             hrs6 = MMC->HRS06;
4726             hrs6 &= ~MSS_MMC_MODE_MASK;
4727             hrs6 |= MSS_MMC_MODE_HS200;
4728             MMC->HRS06 = hrs6;
4729             /* Up the Host MMC clock frequency */
4730             set_host_sdclk(cfg->clk_rate);
4731             /* HS200 tuning */
4732             ret_status = execute_tunning_mmc(MSS_MMC_DATA_WIDTH_8BIT);
4733 
4734             ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
4735             if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
4736             {
4737                 pcsd_reg = (uint8_t *)csd_reg;
4738                 /* Offsets defined in JESD84-B51 extended CSD */
4739                 hw_sec_count   = csd_reg[EXT_CSD_SECTOR_COUNT_OFFSET/WORD_SIZE];
4740                 hw_ext_csd_rev = pcsd_reg[EXT_CSD_REVISION_OFFSET] & BYTE_MASK;
4741                 hw_hs_timing   = pcsd_reg[EXT_CSD_HS_TIMING_OFFSET];
4742             }
4743             else
4744             {
4745                 ret_status = MSS_MMC_TRANSFER_FAIL;
4746                 return ret_status;
4747             }
4748         }
4749 
4750         if (TRANSFER_IF_SUCCESS != response_status)
4751         {
4752             ret_status = MSS_MMC_TRANSFER_FAIL;
4753             return ret_status;
4754         }
4755     }
4756 
4757     /* High Speed Mode set */
4758     hs_timing = MMC_HS_MODE;
4759 
4760     response_status = cif_send_cmd(hs_timing,
4761                                 MMC_CMD_6_SWITCH,
4762                                 MSS_MMC_RESPONSE_R1B);
4763 
4764     if (TRANSFER_IF_FAIL != response_status)
4765     {
4766         response_status = check_device_status(response_status);
4767     }
4768 
4769     if (TRANSFER_IF_SUCCESS == response_status)
4770     {
4771         set_host_sdclk(MSS_MMC_CLOCK_50MHZ);
4772         /* Enable Host High Speed */
4773         MMC->SRS10 |= (MMC_SET << SHIFT_2BIT);
4774 
4775         if (MSS_MMC_MODE_HS400 == cfg->bus_speed_mode)
4776         {
4777             data_width = MMC_DUAL_DATA_WIDTH_8BIT;
4778         }
4779         else if (MSS_MMC_MODE_HS400_ES == cfg->bus_speed_mode)
4780         {
4781             /* Enable strobe support*/
4782             data_width = MMC_ES_DUAL_DATA_WIDTH_8BIT;
4783         }
4784         else
4785         {
4786             data_width = MMC_DUAL_DATA_WIDTH_8BIT;
4787         }
4788         /* Set MMC data bus width */
4789         response_status = cif_send_cmd(MMC_DW_CSD | (data_width << SHIFT_8BIT),
4790                                         MMC_CMD_6_SWITCH,
4791                                         MSS_MMC_RESPONSE_R1B);
4792         if (TRANSFER_IF_FAIL != response_status)
4793         {
4794             response_status = check_device_status(response_status);
4795         }
4796 
4797         if (TRANSFER_IF_SUCCESS == response_status)
4798         {
4799             /* eMMC Mode select in Host controller */
4800             hrs6 = MMC->HRS06;
4801             hrs6 &= ~MSS_MMC_MODE_MASK;
4802             hrs6 |= MSS_MMC_MODE_DDR;
4803             MMC->HRS06 = hrs6;
4804 
4805             set_host_sdclk(MSS_MMC_CLOCK_50MHZ);
4806 
4807             ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg);
4808             if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
4809             {
4810                 pcsd_reg = (uint8_t *)csd_reg;
4811                 /* Offsets defined in JESD84-B51 extended CSD */
4812                 hw_device_type   =  pcsd_reg[EXT_CSD_CARD_TYPE_OFFSET];
4813                 hw_sec_count   = csd_reg[EXT_CSD_SECTOR_COUNT_OFFSET/WORD_SIZE];
4814                 hw_ext_csd_rev = pcsd_reg[EXT_CSD_REVISION_OFFSET] & BYTE_MASK;
4815                 hw_hs_timing   = pcsd_reg[EXT_CSD_HS_TIMING_OFFSET];
4816             }
4817 
4818             /* Set HS400 mode */
4819             hs_timing = MMC_HS400_MODE;
4820             response_status = cif_send_cmd(hs_timing,
4821                                     MMC_CMD_6_SWITCH,
4822                                     MSS_MMC_RESPONSE_R1B);
4823 
4824             if (TRANSFER_IF_FAIL != response_status)
4825             {
4826                 response_status = check_device_status(response_status);
4827             }
4828 
4829             if (TRANSFER_IF_SUCCESS == response_status)
4830             {
4831                 /* eMMC Mode select in Host controller */
4832                 hrs6 = MMC->HRS06;
4833                 hrs6 &= ~MSS_MMC_MODE_MASK;
4834                 if (MSS_MMC_MODE_HS400 == cfg->bus_speed_mode)
4835                 {
4836                     hrs6 |= MSS_MMC_MODE_HS400;
4837                 }
4838                 else if (MSS_MMC_MODE_HS400_ES == cfg->bus_speed_mode)
4839                 {
4840                     hrs6 |= MSS_MMC_MODE_HS400_ES;
4841                 }
4842                 else
4843                 {
4844                     hrs6 = MMC_CLEAR;
4845                 }
4846 
4847                 MMC->HRS06 = hrs6;
4848                 /* Up the Host MMC clock frequency */
4849                 set_host_sdclk(cfg->clk_rate);
4850                 ret_status = MSS_MMC_single_block_read(MMC_CLEAR, (uint32_t *)csd_reg);
4851                 if (MSS_MMC_TRANSFER_SUCCESS != ret_status)
4852                 {
4853                     ret_status = MSS_MMC_TRANSFER_FAIL;
4854                 }
4855             }
4856         }
4857     }
4858 
4859     if (TRANSFER_IF_SUCCESS != response_status)
4860     {
4861         ret_status = MSS_MMC_TRANSFER_FAIL;
4862     }
4863     return ret_status;
4864 }
4865 /******************************************************************************/
device_set_hs_timing(uint32_t hs_mode,const mss_mmc_cfg_t * cfg)4866 static mss_mmc_status_t device_set_hs_timing
4867 (
4868     uint32_t hs_mode,
4869     const mss_mmc_cfg_t * cfg
4870 )
4871 {
4872     cif_response_t response_status = TRANSFER_IF_SUCCESS;
4873     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
4874     uint32_t srs10, hrs6;
4875     volatile uint32_t hs_timing = MMC_HS_MODE_DEFAULT;
4876     uint8_t phy_delay_type;
4877 
4878     uint32_t data_width = cfg->data_bus_width;
4879 
4880     /* Set 4/8-bit bus mode */
4881     srs10 = MMC->SRS10;
4882     if (data_width == MSS_MMC_DATA_WIDTH_4BIT)
4883     {
4884         srs10 |= SRS10_DATA_WIDTH_4BIT;
4885     }
4886     else if (data_width == MSS_MMC_DATA_WIDTH_8BIT)
4887     {
4888         srs10 |= SRS10_EXTENDED_DATA_TRANSFER_WIDTH;
4889     }
4890     else
4891     {
4892         srs10 &= ~SRS10_DATA_WIDTH_4BIT;
4893         srs10 &= ~SRS10_EXTENDED_DATA_TRANSFER_WIDTH;
4894     }
4895     MMC->SRS10 = srs10;
4896 
4897     switch (hs_mode)
4898     {
4899         case DEVICE_SUPPORT_LEGACY:
4900 
4901             hs_timing = MMC_LEGACY_MODE;
4902             phy_delay_type = MSS_MMC_PHY_DELAY_INPUT_MMC_LEGACY;
4903             if (cfg->clk_rate > MSS_MMC_CLOCK_26MHZ)
4904             {
4905                 response_status = TRANSFER_IF_FAIL;
4906             }
4907             break;
4908 
4909         case DEVICE_SUPPORT_SDR:
4910 
4911             hs_timing = MMC_HS_MODE;
4912             phy_delay_type = MSS_MMC_PHY_DELAY_INPUT_MMC_SDR;
4913             break;
4914 
4915         case DEVICE_SUPPORT_DDR:
4916 
4917             hs_timing = MMC_HS_MODE;
4918             phy_delay_type = MSS_MMC_PHY_DELAY_INPUT_MMC_DDR;
4919             if (MSS_MMC_DATA_WIDTH_8BIT == data_width)
4920             {
4921                 data_width = MMC_DUAL_DATA_WIDTH_8BIT;
4922             }
4923             else if (MSS_MMC_DATA_WIDTH_4BIT == data_width)
4924             {
4925                 data_width = MMC_DUAL_DATA_WIDTH_4BIT;
4926             }
4927             else
4928             {
4929                 response_status = TRANSFER_IF_FAIL;
4930             }
4931             break;
4932 
4933         case DEVICE_SUPPORT_HS200:
4934 
4935             hs_timing = MMC_HS200_MODE;
4936             if (MSS_MMC_DATA_WIDTH_1BIT == data_width)
4937             {
4938                 response_status = TRANSFER_IF_FAIL;
4939             }
4940             break;
4941 
4942         default:
4943             response_status = TRANSFER_IF_FAIL;
4944             break;
4945     }
4946 
4947     if (TRANSFER_IF_SUCCESS == response_status)
4948     {
4949         if (DEVICE_SUPPORT_DDR == hs_mode)
4950         {
4951             response_status = cif_send_cmd(hs_timing,
4952                                            MMC_CMD_6_SWITCH,
4953                                            MSS_MMC_RESPONSE_R1B);
4954             if (TRANSFER_IF_FAIL != response_status)
4955             {
4956                 response_status = check_device_status(response_status);
4957                 if (TRANSFER_IF_SUCCESS == response_status)
4958                 {
4959                     /* Set MMC data bus width */
4960                     response_status = cif_send_cmd(MMC_DW_CSD | (data_width << SHIFT_8BIT),
4961                                             MMC_CMD_6_SWITCH,
4962                                             MSS_MMC_RESPONSE_R1B);
4963                     if (TRANSFER_IF_FAIL != response_status)
4964                     {
4965                         response_status = check_device_status(response_status);
4966                     }
4967                 }
4968             }
4969 
4970         }
4971         else if (DEVICE_SUPPORT_LEGACY == hs_mode)
4972         {
4973             /* Set MMC data bus width */
4974             response_status = cif_send_cmd(MMC_DW_CSD | (data_width << SHIFT_8BIT),
4975                                         MMC_CMD_6_SWITCH,
4976                                         MSS_MMC_RESPONSE_R1B);
4977             if (TRANSFER_IF_FAIL != response_status)
4978             {
4979                 response_status = check_device_status(response_status);
4980             }
4981         }
4982         else
4983         {
4984             /* Set MMC data bus width */
4985             response_status = cif_send_cmd(MMC_DW_CSD | (data_width << SHIFT_8BIT),
4986                                         MMC_CMD_6_SWITCH,
4987                                         MSS_MMC_RESPONSE_R1B);
4988             if (TRANSFER_IF_FAIL != response_status)
4989             {
4990                 response_status = check_device_status(response_status);
4991 
4992                 if (TRANSFER_IF_SUCCESS == response_status)
4993                 {
4994                     response_status = cif_send_cmd(hs_timing,
4995                                            MMC_CMD_6_SWITCH,
4996                                            MSS_MMC_RESPONSE_R1B);
4997 
4998                     if (TRANSFER_IF_FAIL != response_status)
4999                     {
5000                         response_status = check_device_status(response_status);
5001                     }
5002                 }
5003             }
5004         }
5005 
5006         if (TRANSFER_IF_SUCCESS == response_status)
5007         {
5008             /* eMMC Mode select in Host controller */
5009             hrs6 = MMC->HRS06;
5010             hrs6 &= ~MSS_MMC_MODE_MASK;
5011             hrs6 |= cfg->bus_speed_mode;
5012             MMC->HRS06 = hrs6;
5013             /* Up the Host MMC clock frequency */
5014             set_host_sdclk(cfg->clk_rate);
5015             if(DEVICE_SUPPORT_HS200 == hs_mode)
5016             {
5017                 ret_status = MSS_MMC_TRANSFER_SUCCESS;
5018             }
5019             else
5020             {
5021                 /* Set Phy delay for select MMC mode */
5022                 ret_status = phy_training_mmc(phy_delay_type, cfg->clk_rate);
5023                 if (ret_status != MSS_MMC_TRANSFER_SUCCESS)
5024                 {
5025                     response_status = TRANSFER_IF_FAIL;
5026                 }
5027             }
5028         }
5029     }
5030     if (TRANSFER_IF_SUCCESS != response_status)
5031     {
5032         ret_status = MSS_MMC_TRANSFER_FAIL;
5033     }
5034     return ret_status;
5035 }
5036 /******************************************************************************/
set_host_sdclk(uint32_t frequencyKHz)5037 static uint8_t set_host_sdclk(uint32_t frequencyKHz)
5038 {
5039     uint32_t temp, temp1;
5040     uint32_t baseclkkHz;
5041     uint32_t i;
5042     uint32_t setFreqKhz;
5043 
5044     /* Disable sd clock */
5045     temp = MMC->SRS11;
5046     temp &= ~(uint32_t)SRS11_SD_CLOCK_ENABLE;
5047     MMC->SRS11 = temp;
5048     /* Read base clock frequency for SD clock in kilo herz */
5049     temp = MMC->SRS16;
5050     baseclkkHz = ((temp & 0x0000FF00u) >> 8U) * 1000u;
5051 
5052     if (baseclkkHz == 0u)
5053     {
5054         return 1u;
5055     }
5056     /* Read current value of SRS11 register */
5057     temp = MMC->SRS11;
5058     /* Clear old frequency base settings */
5059     temp &= ~(uint32_t)SRS11_SEL_FREQ_BASE_MASK;
5060 
5061     /* 10-bit Divider Clock Mode */
5062     for (i = 1u; i < 2046u; i++)
5063     {
5064         if (((baseclkkHz / i) < frequencyKHz)
5065             || (((baseclkkHz / i) == frequencyKHz) && ((baseclkkHz % i) == 0u)))
5066         {
5067             break;
5068         }
5069     }
5070     temp1 = ((i / 2u) << 8);
5071     /* Set SDCLK Frequency Select and Internal Clock Enable */
5072     temp |= (temp1 & 0xFF00u) | ((temp1 & 0x30000u) >> 10)
5073             | (uint32_t)SRS11_INT_CLOCK_ENABLE;
5074     temp &= ~(uint32_t)SRS11_CLOCK_GENERATOR_SELECT;
5075     setFreqKhz = baseclkkHz / i;
5076 
5077     MMC->SRS11 = temp;
5078 
5079     while ((MMC->SRS11 & SRS11_INT_CLOCK_STABLE) == 0u);
5080 
5081     /* Enable sd clock */
5082     temp = MMC->SRS11;
5083     temp |= (uint32_t)SRS11_SD_CLOCK_ENABLE;
5084     MMC->SRS11 = temp;
5085     return 0;
5086 }
5087 /******************************************************************************/
set_data_timeout(uint32_t timeout_val_us)5088 static mss_mmc_status_t set_data_timeout(uint32_t timeout_val_us)
5089 {
5090     mss_mmc_status_t status = MSS_MMC_NO_ERROR;
5091     uint32_t temp, sdmclk_khz, sdmclk_Mhz, timeout_interval;
5092     uint8_t j;
5093     uint32_t sdmclk, timeoutVal;
5094 
5095     temp = MMC->SRS16;
5096     sdmclk_khz = (temp & 0x0000003Fu);/* 0x4u; - 0x4 is dummy -> 50Mhz * 4 = 200Mhz, */
5097 
5098     if (((temp & SRS16_TIMEOUT_CLOCK_UNIT_MHZ) == 0u) && (timeout_val_us < 1000u))
5099     {
5100 
5101         status = MSS_MMC_INVALID_PARAMETER;
5102     }
5103     else if (sdmclk_khz == 0u)
5104     {
5105         status = MSS_MMC_BASE_CLK_IS_ZERO_ERR;
5106     }
5107     else
5108     {
5109         if ((temp & SRS16_TIMEOUT_CLOCK_UNIT_MHZ) != 0u)
5110         {
5111             sdmclk_khz *= 1000u;
5112         }
5113         sdmclk_Mhz = sdmclk_khz / 1000u;
5114 
5115         if (sdmclk_Mhz == 0u)
5116         {
5117             sdmclk = sdmclk_khz;
5118             timeoutVal = timeout_val_us / 1000u;
5119         }
5120         else
5121         {
5122             sdmclk = sdmclk_Mhz;
5123             timeoutVal = timeout_val_us;
5124         }
5125         /* Calculate data Timeout Counter Value */
5126         timeout_interval = 8192u/*2 ^ 13*/;
5127         for (j = 0u; j < 15u; j++)
5128         {
5129             /* If  (timeoutVal < ((1 / sdmclk) * timeout_interval)) */
5130             if (timeoutVal < (timeout_interval / sdmclk))
5131             {
5132                 break;
5133             }
5134             timeout_interval *= 2u;
5135         }
5136         timeout_interval = (uint32_t)j << 16u;
5137 
5138         temp = MMC->SRS11;
5139         temp &= (uint32_t)~SRS11_TIMEOUT_MASK;
5140         temp |= timeout_interval;
5141         MMC->SRS11 = temp;
5142     }
5143     return status;
5144 }
5145 /******************************************************************************/
set_sdhost_power(uint32_t voltage)5146 static mss_mmc_status_t  set_sdhost_power(uint32_t voltage)
5147 {
5148     uint32_t temp, srs16;
5149     mss_mmc_status_t status = MSS_MMC_NO_ERROR;
5150 
5151         /* Disable SD bus power */
5152     temp = MMC->SRS10;
5153     temp &= ~SRS10_SD_BUS_POWER;
5154     MMC->SRS10 = temp;
5155 
5156     /* Clear current voltage settings*/
5157     temp &= ~SRS10_BUS_VOLTAGE_MASK;
5158     srs16 = MMC->SRS16;
5159 
5160     /* If Voltage == 0
5161      * disable bus power
5162      * power is disabled so do nothing, return no error
5163      */
5164     if (voltage != MMC_CLEAR)
5165     {
5166         switch (voltage)
5167         {
5168             case SRS10_SET_3_3V_BUS_VOLTAGE:
5169                 if ((srs16 & SRS16_VOLTAGE_3_3V_SUPPORT) == MMC_CLEAR)
5170                 {
5171                    status = MSS_MMC_INVALID_PARAMETER;
5172                     break;
5173                 }
5174                 /* Set new voltage value */
5175                 temp |= (SRS10_SET_3_3V_BUS_VOLTAGE | SRS10_SD_BUS_POWER);
5176                 break;
5177             case SRS10_SET_3_0V_BUS_VOLTAGE:
5178                 if ((srs16 & SRS16_VOLTAGE_3_0V_SUPPORT) == MMC_CLEAR)
5179                 {
5180                     status = MSS_MMC_INVALID_PARAMETER;
5181                     break;
5182                 }
5183                 /* Set new voltage value */
5184                 temp |= (SRS10_SET_3_0V_BUS_VOLTAGE | SRS10_SD_BUS_POWER);
5185                 break;
5186             case SRS10_SET_1_8V_BUS_VOLTAGE:
5187                 if ((srs16 & SRS16_VOLTAGE_1_8V_SUPPORT) == MMC_CLEAR)
5188                 {
5189                     status = MSS_MMC_INVALID_PARAMETER;
5190                     break;
5191                 }
5192                 /* Set new voltage value */
5193                 temp |= (SRS10_SET_1_8V_BUS_VOLTAGE | SRS10_SD_BUS_POWER);
5194                 break;
5195             default:
5196                 status = MSS_MMC_INVALID_PARAMETER;
5197                 break;
5198         }
5199 
5200         if (status == MSS_MMC_NO_ERROR)
5201         {
5202             MMC->SRS10 = temp;
5203         }
5204         mmc_delay(DELAY_COUNT);
5205     }
5206     return (status);
5207 }
5208 /******************************************************************************/
mmc_delay(uint32_t value)5209 static void mmc_delay(uint32_t value)
5210 {
5211     while (value--) asm volatile("");
5212 }
5213 /******************************************************************************/
cmd6_single_block_read(uint32_t src_addr,uint32_t * dst_addr,uint32_t size)5214 static mss_mmc_status_t cmd6_single_block_read
5215 (
5216     uint32_t src_addr,
5217     uint32_t * dst_addr,
5218     uint32_t size
5219 )
5220 {
5221     uint32_t isr_errors;
5222     uint32_t blk_read, srs03_data, srs9;
5223     uint16_t word_cnt = (BLK_SIZE/WORD_SIZE);
5224     uint32_t idx_cnt = MMC_CLEAR;
5225 
5226     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
5227 
5228     /* Block length and count*/
5229     MMC->SRS01 = (size | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
5230 
5231     /* DPS, Data transfer direction - read */
5232     srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ |SRS3_BLOCK_COUNT_ENABLE
5233                         | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
5234                         | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
5235                         | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
5236     /* Check cmd and data line busy */
5237     do
5238     {
5239         srs9 = MMC->SRS09;
5240     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
5241 
5242     word_cnt = (size/WORD_SIZE);
5243     /* Command argument */
5244     MMC->SRS02 = src_addr;
5245     /* Execute command */
5246     MMC->SRS03 = (uint32_t)((SD_CMD_6 << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
5247 
5248     idx_cnt = MMC_CLEAR;
5249 
5250     do
5251     {
5252         blk_read = MMC->SRS12;
5253     } while (MMC_CLEAR == (blk_read & (SRS12_BUFFER_READ_READY | SRS12_ERROR_INTERRUPT)));
5254     /* Read in the contents of the Buffer */
5255     if ((blk_read & SRS12_BUFFER_READ_READY) != MMC_CLEAR)
5256     {
5257         while (word_cnt > (BUFF_EMPTY))
5258         {
5259             dst_addr[idx_cnt] = MMC->SRS08;
5260             ++idx_cnt;
5261             --word_cnt;
5262         }
5263     }
5264     isr_errors = MMC->SRS12;
5265     /* Abort if any errors*/
5266     if ((SRS12_ERROR_STATUS_MASK & isr_errors) == MMC_CLEAR)
5267     {
5268         ret_status = MSS_MMC_TRANSFER_SUCCESS;
5269     }
5270     else
5271     {
5272         ret_status = MSS_MMC_ERR_INTERRUPT;
5273     }
5274     /* Clear all status interrupts except:
5275     *  current limit error, card interrupt, card removal, card insertion */
5276     MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR
5277                             | SRS12_CARD_INTERRUPT
5278                             | SRS12_CARD_REMOVAL
5279                             | SRS12_CARD_INSERTION);
5280     return (ret_status);
5281 }
5282 /******************************************************************************/
execute_tunning_mmc(uint8_t data_width)5283 static mss_mmc_status_t execute_tunning_mmc(uint8_t data_width)
5284 {
5285     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
5286 
5287     uint32_t ReadPattern[128u];
5288     uint8_t i, j, PatternOk[40u];
5289     uint8_t Pos;
5290     uint8_t BufferSize =  (data_width == MSS_MMC_DATA_WIDTH_4BIT)? 64u:128u;
5291     uint32_t const *WritePattern = calc_write_pattern(data_width);
5292 
5293     for (j = 0u; j < 40u; j++)
5294     {
5295         host_mmc_tune(j);
5296         mmc_delay(0xFFu);
5297         for (i = 0u; i < (BufferSize / 4u); i++)
5298         {
5299             ReadPattern[i] = 0u;
5300         }
5301         ret_status = read_tune_block(ReadPattern, BufferSize, MMC_CMD_21_SEND_TUNE_BLK);
5302         if (MSS_MMC_TRANSFER_SUCCESS == ret_status)
5303         {
5304             /* Compare data with pattern */
5305             PatternOk[j] = 1u;
5306             for (i = 0u; i < (BufferSize / 4u); i++)
5307             {
5308                 if (WritePattern[i] != ReadPattern[i])
5309                 {
5310                     PatternOk[j] = 0u;
5311                     /* Reset Data and cmd line */
5312                     MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
5313                     /* Read pattern is not correct - exit loop */
5314                     break;
5315                 }
5316             }
5317         }
5318         else
5319         {
5320             /* Reset Data and cmd line */
5321             MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE;
5322             PatternOk[j] = 0u;
5323         }
5324     }
5325     Pos = calc_longest_valid_delay_chain_val(PatternOk);
5326     /* Delay value set to Pos */
5327     host_mmc_tune(Pos);
5328     ret_status = read_tune_block(ReadPattern, BufferSize, MMC_CMD_21_SEND_TUNE_BLK);
5329     return ret_status;
5330 }
5331 /******************************************************************************/
read_tune_block(uint32_t * read_data,uint32_t size,uint8_t cmd)5332 static mss_mmc_status_t read_tune_block
5333 (
5334     uint32_t *read_data,
5335     uint32_t size,
5336     uint8_t cmd
5337 )
5338 {
5339 
5340     uint32_t isr_errors;
5341     uint32_t blk_read, srs03_data, srs9;
5342     uint16_t word_cnt = (BLK_SIZE/WORD_SIZE);
5343     uint32_t idx_cnt = MMC_CLEAR;
5344     mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR;
5345 
5346     /* Clear all status interrupts */
5347     MMC->SRS12 = MMC_STATUS_CLEAR;
5348     /* Block length and count*/
5349     MMC->SRS01 = (size | (MMC_SET << BLOCK_COUNT_ENABLE_SHIFT));
5350     /* DPS, Data transfer direction - read */
5351     srs03_data = (uint32_t)(SRS3_DATA_PRESENT | SRS3_TRANS_DIRECT_READ |SRS3_BLOCK_COUNT_ENABLE
5352                         | SRS3_RESP_ERR_CHECK_EN | SRS3_RESP_INTER_DISABLE
5353                         | SRS3_RESPONSE_CHECK_TYPE_R1 | SRS3_RESP_LENGTH_48
5354                         | SRS3_CRC_CHECK_EN | SRS3_INDEX_CHECK_EN);
5355     /* Check cmd and data line busy */
5356     do
5357     {
5358         srs9 = MMC->SRS09;
5359     }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR);
5360 
5361     word_cnt = size/WORD_SIZE;
5362     /* Command argument */
5363     MMC->SRS02 = MMC_CLEAR;
5364     /* Execute command */
5365     MMC->SRS03 = (uint32_t)((cmd << MMC_SRS03_COMMAND_SHIFT) | srs03_data);
5366 
5367     idx_cnt = MMC_CLEAR;
5368 
5369     do
5370     {
5371         blk_read = MMC->SRS12;
5372     } while (MMC_CLEAR == (blk_read & (SRS12_BUFFER_READ_READY | SRS12_ERROR_INTERRUPT)));
5373 
5374     /* Read in the contents of the Buffer */
5375     if ((blk_read & SRS12_BUFFER_READ_READY) != MMC_CLEAR)
5376     {
5377         while (word_cnt > (BUFF_EMPTY))
5378         {
5379             read_data[idx_cnt] = MMC->SRS08;
5380             ++idx_cnt;
5381             --word_cnt;
5382         }
5383     }
5384     isr_errors = MMC->SRS12;
5385     /* Abort if any errors*/
5386     if ((SRS12_ERROR_STATUS_MASK & isr_errors) == MMC_CLEAR)
5387     {
5388         ret_status = MSS_MMC_TRANSFER_SUCCESS;
5389     }
5390     else
5391     {
5392         ret_status = MSS_MMC_ERR_INTERRUPT;
5393     }
5394     /* Clear all status interrupts */
5395     MMC->SRS12 = MMC_STATUS_CLEAR;
5396     return (ret_status);
5397 }
5398 /******************************************************************************/
calc_write_pattern(const uint8_t bus_width)5399 static const uint32_t* calc_write_pattern(const uint8_t bus_width)
5400 {
5401     static const uint32_t emmc_pattern4b[64 / 4] = {
5402         0x00ff0fffU,
5403         0xccc3ccffU,
5404         0xffcc3cc3U,
5405         0xeffefffeU,
5406         0xddffdfffU,
5407         0xfbfffbffU,
5408         0xff7fffbfU,
5409         0xefbdf777U,
5410         0xf0fff0ffU,
5411         0x3cccfc0fU,
5412         0xcfcc33ccU,
5413         0xeeffefffU,
5414         0xfdfffdffU,
5415         0xffbfffdfU,
5416         0xfff7ffbbU,
5417         0xde7b7ff7U
5418     };
5419 
5420     static const uint32_t emmc_pattern8b[128 / 4] = {
5421         0xff00ffffU,
5422         0x0000ffffU,
5423         0xccccffffU,
5424         0xcccc33ccU,
5425         0xcc3333ccU,
5426         0xffffccccU,
5427         0xffffeeffU,
5428         0xffeeeeffU,
5429         0xffddffffU,
5430         0xddddffffU,
5431         0xbbffffffU,
5432         0xbbffffffU,
5433         0xffffffbbU,
5434         0xffffff77U,
5435         0x77ff7777U,
5436         0xffeeddbbU,
5437         0x00ffffffU,
5438         0x00ffffffU,
5439         0xccffff00u,
5440         0xcc33ccccU,
5441         0x3333ccccU,
5442         0xffccccccU,
5443         0xffeeffffU,
5444         0xeeeeffffU,
5445         0xddffffffU,
5446         0xddffffffU,
5447         0xffffffddU,
5448         0xffffffbbU,
5449         0xffffbbbbU,
5450         0xffff77ffU,
5451         0xff7777ffU,
5452         0xeeddbb77U
5453     };
5454 
5455     const uint32_t* write_pattern = NULL_POINTER;
5456 
5457     if ((uint8_t)MSS_MMC_DATA_WIDTH_8BIT == bus_width) {
5458         write_pattern = (const uint32_t*)emmc_pattern8b;
5459     }
5460     if ((uint8_t)MSS_MMC_DATA_WIDTH_4BIT == bus_width) {
5461         write_pattern = (const uint32_t*)emmc_pattern4b;
5462     }
5463 
5464     return (write_pattern);
5465 }
5466 /******************************************************************************/
host_mmc_tune(uint8_t value)5467 static void host_mmc_tune(uint8_t value)
5468 {
5469     uint32_t hrs6, read_data;
5470 
5471     hrs6 = MMC->HRS06;
5472     hrs6 &= ~HRS6_EMMC_TUNE_VALUE_MASK;
5473     hrs6 |= (uint32_t)((value << SHIFT_8BIT) | HRS6_EMMC_TUNE_REQUEST);
5474     MMC->HRS06 = hrs6;
5475 
5476     do
5477     {
5478         read_data = MMC->HRS06;
5479     }while ((read_data & HRS6_EMMC_TUNE_REQUEST) != MMC_CLEAR);
5480 
5481 }
5482 /******************************************************************************/
calc_longest_valid_delay_chain_val(const uint8_t * pattern_ok)5483 static uint8_t calc_longest_valid_delay_chain_val(const uint8_t* pattern_ok)
5484 {
5485     /* Looking for longest valid delay chain value (the best tuning value) */
5486     uint8_t pos = 0u;
5487     uint8_t length = 0u;
5488     uint8_t curr_length = 0u;
5489     uint8_t i;
5490     for (i = 0u; i < 40u; i++)
5491     {
5492         if (pattern_ok[i] == 1u)
5493         {
5494             curr_length++;
5495             if (curr_length > length)
5496             {
5497                 pos = i - length;
5498                 length++;
5499             }
5500         }
5501         else
5502         {
5503             curr_length = 0u;
5504         }
5505     }
5506     pos += (length / 2u);
5507 
5508     return (pos);
5509 }
5510 /******************************************************************************/
check_device_status(cif_response_t rsp_status)5511 static cif_response_t check_device_status(cif_response_t rsp_status)
5512 {
5513     uint32_t srs9;
5514 
5515     do
5516     {
5517         srs9 = MMC->SRS09;
5518     }while ((srs9 & SRS9_DAT0_SIGNAL_LEVEL) == MMC_CLEAR);
5519 
5520     /*
5521     * Writing to the EXT CSD register takes significant time,
5522     * so function must not return until the 'READY FOR DATA'
5523     * bit is set in the Card Status Register.
5524     */
5525     while (DEVICE_BUSY == rsp_status)
5526     {
5527         rsp_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT,
5528                                     MMC_CMD_13_SEND_STATUS,
5529                                     MSS_MMC_RESPONSE_R1);
5530     }
5531     return rsp_status;
5532 }
5533 /******************************************************************************/
5534 
5535 #ifdef __cplusplus
5536 }
5537 #endif
5538