175 static uint8_t fc_sharing_hw(uint32_t cfg)  in fc_sharing_hw()  argument
179     if (cfg & MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS)) {  in fc_sharing_hw()
180         if (cfg & MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_CAF_POS)) {  in fc_sharing_hw()
194     uint32_t cfg = 0;  in fc_sharing_get()  local
198         cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS);  in fc_sharing_get()
200         cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_CAF_POS);  in fc_sharing_get()
202             cfg |= MEC_BIT(MEC_ESPI_CFG_FLASH_SHARED_TAF_POS);  in fc_sharing_get()
206     return cfg;  in fc_sharing_get()
324 int mec_hal_espi_init(struct mec_espi_config *cfg)  in mec_hal_espi_init()  argument
326     if (!cfg) {  in mec_hal_espi_init()
330     struct mec_espi_io_regs *iobase = cfg->iobase;  in mec_hal_espi_init()
333     set_supported_channels(iobase, cfg->capabilities);  in mec_hal_espi_init()
334     set_supported_max_freq(iobase, cfg->capabilities);  in mec_hal_espi_init()
335     set_supported_io_modes(iobase, cfg->capabilities);  in mec_hal_espi_init()
336     set_supported_alert_io_pin_mode(iobase, cfg->capabilities);  in mec_hal_espi_init()
337     set_pc_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
338     set_vw_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
339     set_oob_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
340     set_fc_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
341     set_pltrst_source(iobase, cfg->capabilities);  in mec_hal_espi_init()
346     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_VW_CT_GIRQ_EN_POS)) {  in mec_hal_espi_init()
351     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_PC_GIRQ_EN_POS)) {  in mec_hal_espi_init()
355     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_BM1_GIRQ_EN_POS)) {  in mec_hal_espi_init()
359     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_BM2_GIRQ_EN_POS)) {  in mec_hal_espi_init()
363     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_LTR_GIRQ_EN_POS)) {  in mec_hal_espi_init()
367     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_OOB_UP_GIRQ_EN_POS)) {  in mec_hal_espi_init()
371     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_OOB_DN_GIRQ_EN_POS)) {  in mec_hal_espi_init()
375     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_FC_GIRQ_EN_POS)) {  in mec_hal_espi_init()
379     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_VW_CHEN_GIRQ_EN_POS)) {  in mec_hal_espi_init()
383     if (cfg->cfg_flags & MEC_BIT(MEC_ESPI_CFG_FLAG_ERST_GIRQ_EN_POS)) {  in mec_hal_espi_init()
416                                 enum mec_espi_global_cap cap, uint32_t cfg)  in mec_hal_espi_capability_set()  argument
424         set_supported_max_freq(iobase, cfg);  in mec_hal_espi_capability_set()
427         set_supported_io_modes(iobase, cfg);  in mec_hal_espi_capability_set()
430         set_supported_alert_io_pin_mode(iobase, cfg);  in mec_hal_espi_capability_set()
433         if (cfg & MEC_BIT(MEC_ESPI_CFG_PERIPH_CHAN_SUP_POS)) {  in mec_hal_espi_capability_set()
440         set_pc_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
443         if (cfg & MEC_BIT(MEC_ESPI_CFG_VW_CHAN_SUP_POS)) {  in mec_hal_espi_capability_set()
450         set_vw_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
453         if (cfg & MEC_BIT(MEC_ESPI_CFG_OOB_CHAN_SUP_POS)) {  in mec_hal_espi_capability_set()
460         set_oob_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
463         if (cfg & MEC_BIT(MEC_ESPI_CFG_FLASH_CHAN_SUP_POS)) {  in mec_hal_espi_capability_set()
470         set_fc_max_pld(iobase, cfg);  in mec_hal_espi_capability_set()
473         set_fc_shared_mode(iobase, cfg);  in mec_hal_espi_capability_set()
482 int mec_hal_espi_capabilities_get(struct mec_espi_io_regs *iobase, uint32_t *cfg)  in mec_hal_espi_capabilities_get()  argument
486     if (!iobase || !cfg) {  in mec_hal_espi_capabilities_get()
528     *cfg = cv;  in mec_hal_espi_capabilities_get()
533 static void set_espi_global_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_global_cap()  argument
539     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_SUPP_PC_POS)) {  in set_espi_global_cap()
542     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_SUPP_VW_POS)) {  in set_espi_global_cap()
545     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_SUPP_OOB_POS)) {  in set_espi_global_cap()
548     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_SUPP_FLASH_POS)) {  in set_espi_global_cap()
553     cap = (cfg & MEC_ESPI_CAP_GL_MAX_FREQ_MSK) >> MEC_ESPI_CAP_GL_MAX_FREQ_POS;  in set_espi_global_cap()
554     cap |= (((cfg & MEC_ESPI_CAP_GL_IOM_MSK) >> MEC_ESPI_CAP_GL_IOM_POS)  in set_espi_global_cap()
557     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_SUPP_ALERT_OD_POS)) {  in set_espi_global_cap()
567     if (cfg & MEC_BIT(MEC_ESPI_CAP_GL_PLTRST_EXT_POS)) {  in set_espi_global_cap()
576     uint32_t cfg = 0;  in get_espi_global_cap()  local
580         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_SUPP_PC_POS);  in get_espi_global_cap()
583         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_SUPP_VW_POS);  in get_espi_global_cap()
586         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_SUPP_OOB_POS);  in get_espi_global_cap()
589         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_SUPP_FLASH_POS);  in get_espi_global_cap()
593     cfg |= (((hwval & MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk) >> MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Pos)  in get_espi_global_cap()
595     cfg |= (((hwval & MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Msk) >> MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Pos)  in get_espi_global_cap()
598         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_SUPP_ALERT_OD_POS);  in get_espi_global_cap()
602         cfg |= MEC_BIT(MEC_ESPI_CAP_GL_PLTRST_EXT_POS);  in get_espi_global_cap()
605     return cfg;  in get_espi_global_cap()
608 static void set_espi_pc_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_pc_cap()  argument
611     uint32_t cap = (((cfg & MEC_ESPI_CAP_PC_MAX_PLD_SIZE_MSK) >> MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS)  in set_espi_pc_cap()
625 static void set_espi_vw_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_vw_cap()  argument
629         (((cfg & MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_MSK) >> MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_POS)  in set_espi_vw_cap()
643 static void set_espi_oob_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_oob_cap()  argument
647         (((cfg & MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_MSK) >> MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS)  in set_espi_oob_cap()
661 static void set_espi_fc_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_fc_cap()  argument
668         (uint8_t)((cfg & MEC_ESPI_CAP_FC_TAF_ERBSZ_MSK) >> MEC_ESPI_CAP_FC_TAF_ERBSZ_POS);  in set_espi_fc_cap()
670     cap = ((cfg & MEC_ESPI_CAP_FC_MAX_PLD_SIZE_MSK) >> MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS);  in set_espi_fc_cap()
672     cap |= (((cfg & MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_MSK)  in set_espi_fc_cap()
675     cap |= fc_sharing_hw(cfg);  in set_espi_fc_cap()
683     uint32_t cfg = fc_sharing_get(capfc);  in get_espi_fc_cap()  local
687     cfg |= (temp << MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS);  in get_espi_fc_cap()
691     cfg |= (temp << MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_POS);  in get_espi_fc_cap()
692     cfg |= (((uint32_t)iobase->TAFEBS & 0xffu) << MEC_ESPI_CAP_FC_TAF_ERBSZ_POS);  in get_espi_fc_cap()
694     return cfg;  in get_espi_fc_cap()
697 int mec_hal_espi_cap_set(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id, uint32_t cfg)  in mec_hal_espi_cap_set()  argument
705         set_espi_global_cap(iobase, cfg);  in mec_hal_espi_cap_set()
708         set_espi_pc_cap(iobase, cfg);  in mec_hal_espi_cap_set()
711         set_espi_vw_cap(iobase, cfg);  in mec_hal_espi_cap_set()
714         set_espi_oob_cap(iobase, cfg);  in mec_hal_espi_cap_set()
717         set_espi_fc_cap(iobase, cfg);  in mec_hal_espi_cap_set()