Lines Matching refs:cfg

845     pf_pcie_master_atr_cfg_t * cfg,  in PF_PCIE_master_atr_table_init()  argument
863 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
878 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
901 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
902 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
904 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
920 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
921 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
923 if (cfg->bar_type == PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM) in PF_PCIE_master_atr_table_init()
937 phy_reg = (uint32_t)(cfg->src_addr & ATR_ADDR_MASK); in PF_PCIE_master_atr_table_init()
938 phy_reg |= (uint32_t)((cfg->table_size) << PCIE_SET); in PF_PCIE_master_atr_table_init()
939 phy_reg |= (uint32_t)(cfg->state); in PF_PCIE_master_atr_table_init()
944 *(p_pcie_master_table + WIN0_SRC_ADDR) = (cfg->src_addr_msb); in PF_PCIE_master_atr_table_init()
946 *(p_pcie_master_table + WIN0_TRSL_ADDR_LSB) = (cfg->trns_addr & ATR_ADDR_MASK); in PF_PCIE_master_atr_table_init()
948 *(p_pcie_master_table + WIN0_TRSL_ADDR_UDW) = (cfg->trns_addr_msb); in PF_PCIE_master_atr_table_init()
970 pf_pcie_slave_atr_cfg_t * cfg, in PF_PCIE_slave_atr_table_init() argument
998 phy_reg = (uint32_t)(cfg->src_addr & ATR_ADDR_MASK); in PF_PCIE_slave_atr_table_init()
999 phy_reg |= (uint32_t)((cfg->size) << PCIE_SET); in PF_PCIE_slave_atr_table_init()
1000 phy_reg |= (uint32_t)(cfg->state); in PF_PCIE_slave_atr_table_init()
1004 *(p_pcie_slave + SLV0_SRC_ADDR) = (cfg->src_addr_msb); in PF_PCIE_slave_atr_table_init()
1006 phy_reg = (cfg->trns_addr & ATR_ADDR_MASK); in PF_PCIE_slave_atr_table_init()
1009 *(p_pcie_slave + SLV0_TRSL_ADDR_UDW) = (cfg->trns_addr_msb); in PF_PCIE_slave_atr_table_init()