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Searched refs:base (Results 1 – 25 of 27) sorted by relevance

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/hal_microchip-latest/mec5/drivers/
Dmec_qspi.c61 static struct mec_qspi_info const *qspi_get_info(struct mec_qspi_regs *base) in qspi_get_info() argument
66 if (p->base_addr == (uintptr_t)base) { in qspi_get_info()
81 static uint32_t qspi_get_freq(struct mec_qspi_regs *base) in qspi_get_freq() argument
84 uint32_t fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos; in qspi_get_freq()
93 uint32_t mec_hal_qspi_get_freq(struct mec_qspi_regs *base) in mec_hal_qspi_get_freq() argument
95 if (!base) { in mec_hal_qspi_get_freq()
99 return qspi_get_freq(base); in mec_hal_qspi_get_freq()
102 uint32_t mec_hal_qspi_freq_div(struct mec_qspi_regs *base) in mec_hal_qspi_freq_div() argument
106 if ((uintptr_t)base == (uintptr_t)(MEC_QSPI0_BASE)) { in mec_hal_qspi_freq_div()
107 fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos; in mec_hal_qspi_freq_div()
[all …]
Dmec_kbc.c69 int mec_hal_kbc_init(struct mec_kbc_regs *base, uint32_t flags) in mec_hal_kbc_init() argument
73 if ((uintptr_t)base != (uintptr_t)MEC_KBC0_BASE) { in mec_hal_kbc_init()
81 base->ACTV &= (uint8_t)~MEC_BIT(MEC_KBC_ACTV_ENABLE_Pos); in mec_hal_kbc_init()
84 mec_hal_kbc_girq_dis(base, MEC_KBC_IBF_IRQ | MEC_KBC_OBE_IRQ); in mec_hal_kbc_init()
85 mec_hal_kbc_girq_clr(base, MEC_KBC_IBF_IRQ | MEC_KBC_OBE_IRQ); in mec_hal_kbc_init()
151 base->KESTATUS = (base->KESTATUS & ~msk) | val; in mec_hal_kbc_init()
154 base->KECR = ctrl; in mec_hal_kbc_init()
155 base->ACTV |= MEC_BIT(MEC_KBC_ACTV_ENABLE_Pos); in mec_hal_kbc_init()
156 mec_hal_kbc_girq_en(base, flags); in mec_hal_kbc_init()
161 int mec_hal_kbc_activate(struct mec_kbc_regs *base, uint8_t enable, uint8_t flags) in mec_hal_kbc_activate() argument
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Dmec_mailbox.c49 int mec_hal_mbox_init(struct mec_mbox_regs *base, uint32_t swi_ien_msk, uint32_t flags) in mec_hal_mbox_init() argument
51 const struct mec_mbox_info *mbi = find_mbox_info((uint32_t)base); in mec_hal_mbox_init()
79 int mec_hal_mbox_girq_ctrl(struct mec_mbox_regs *base, uint8_t enable) in mec_hal_mbox_girq_ctrl() argument
81 const struct mec_mbox_info *mbi = find_mbox_info((uint32_t)base); in mec_hal_mbox_girq_ctrl()
92 int mec_hal_mbox_girq_clr(struct mec_mbox_regs *base) in mec_hal_mbox_girq_clr() argument
94 const struct mec_mbox_info *mbi = find_mbox_info((uint32_t)base); in mec_hal_mbox_girq_clr()
105 uint32_t mec_hal_mbox_girq_result(struct mec_mbox_regs *base) in mec_hal_mbox_girq_result() argument
107 const struct mec_mbox_info *mbi = find_mbox_info((uint32_t)base); in mec_hal_mbox_girq_result()
116 int mec_hal_mbox_sirq_set(struct mec_mbox_regs *base, uint8_t bitmap) in mec_hal_mbox_sirq_set() argument
118 if (!base) { in mec_hal_mbox_sirq_set()
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Dmec_uart.c82 static uint32_t uart_baud_divider_get(struct mec_uart_regs *base) in uart_baud_divider_get() argument
86 base->LCR |= MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
87 brdiv = base->IER; in uart_baud_divider_get()
89 brdiv |= base->RXB; in uart_baud_divider_get()
90 base->LCR &= (uint8_t)~MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
95 static void uart_prog_fifos(struct mec_uart_regs *base, uint8_t fifo_mode) in uart_prog_fifos() argument
101 base->FCR = temp; in uart_prog_fifos()
102 base->SCR = temp; in uart_prog_fifos()
106 base->FCR = temp; in uart_prog_fifos()
107 base->SCR = temp; in uart_prog_fifos()
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Dmec_i2c.c126 static struct mec_i2c_info const *get_i2c_smb_info(struct mec_i2c_smb_regs *base) in get_i2c_smb_info() argument
131 if (p->base_addr == (uintptr_t)base) { in get_i2c_smb_info()
145 const struct mec_i2c_info *info = get_i2c_smb_info(ctx->base); in mec_hal_i2c_smb_reset()
156 static void i2c_timing(struct mec_i2c_smb_regs *base, const struct mec_i2c_freq_cfg *freq_cfg) in i2c_timing() argument
158 base->BUSCLK = freq_cfg->bus_clk; in i2c_timing()
159 base->RSHT = freq_cfg->rpt_start_hold_time; in i2c_timing()
160 base->DATATM = freq_cfg->data_timing; in i2c_timing()
161 base->IDLESC = freq_cfg->idle_scaling; in i2c_timing()
162 base->TMOUTSC = freq_cfg->timeout_scaling; in i2c_timing()
168 struct mec_i2c_smb_regs *base = ctx->base; in i2c_config() local
[all …]
Dmec_espi_host_dev.c113 int mec_hal_espi_iobar_cfg(struct mec_espi_io_regs *base, uint8_t ldn, in mec_hal_espi_iobar_cfg() argument
120 if (!base || !ldi) { in mec_hal_espi_iobar_cfg()
131 base->HOST_BAR[idx] = bar_val; in mec_hal_espi_iobar_cfg()
134 base->HOST_BAR[idx] |= MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos); in mec_hal_espi_iobar_cfg()
140 int mec_hal_espi_iobar_enable(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t enable) in mec_hal_espi_iobar_enable() argument
145 if (!base || !ldi) { in mec_hal_espi_iobar_enable()
156 base->HOST_BAR[idx] |= MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos); in mec_hal_espi_iobar_enable()
158 base->HOST_BAR[idx] &= (uint32_t)~MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos); in mec_hal_espi_iobar_enable()
164 int mec_hal_espi_iobar_is_enabled(struct mec_espi_io_regs *base, uint8_t ldn) in mec_hal_espi_iobar_is_enabled() argument
169 if (!base || !ldi) { in mec_hal_espi_iobar_is_enabled()
[all …]
Dmec_uart_api.h139 int mec_hal_uart_init(struct mec_uart_regs *base, uint32_t baud_rate,
151 int mec_hal_uart_clock_freq_get(struct mec_uart_regs *base, uint32_t *clock_freq);
153 int mec_hal_uart_baud_rate_set(struct mec_uart_regs *base, uint32_t baud, uint32_t extclk_hz);
155 int mec_hal_uart_word_len_set(struct mec_uart_regs *base, uint8_t word_len);
156 int mec_hal_uart_word_len_get(struct mec_uart_regs *base, uint8_t *word_len);
158 int mec_hal_uart_stop_bits_set(struct mec_uart_regs *base, uint8_t stop_bits);
159 int mec_hal_uart_stop_bits_get(struct mec_uart_regs *base, uint8_t *stop_bits);
161 int mec_hal_uart_parity_set(struct mec_uart_regs *base, uint8_t parity);
162 int mec_hal_uart_parity_get(struct mec_uart_regs *base, uint8_t *parity);
164 int mec_hal_uart_fifo_control(struct mec_uart_regs *base, uint8_t fifo_cfg);
[all …]
Dmec_qspi_api.h159 uint32_t mec_hal_qspi_get_freq(struct mec_qspi_regs *base);
160 uint32_t mec_hal_qspi_freq_div(struct mec_qspi_regs *base);
161 uint16_t mec_hal_qspi_freq_div_raw(struct mec_qspi_regs *base);
162 int mec_hal_qspi_set_freq(struct mec_qspi_regs *base, uint32_t freqhz);
163 int mec_hal_qspi_byte_time_ns(struct mec_qspi_regs *base, uint32_t *btime_ns);
166 int mec_hal_qspi_reset(struct mec_qspi_regs *base);
171 int mec_hal_qspi_reset_sr(struct mec_qspi_regs *base);
173 void mec_hal_qspi_girq_clr(struct mec_qspi_regs *base);
174 void mec_hal_qspi_girq_ctrl(struct mec_qspi_regs *base, uint8_t enable);
175 uint32_t mec_hal_qspi_girq_is_result(struct mec_qspi_regs *base);
[all …]
Dmec_mailbox_api.h40 int mec_hal_mbox_init(struct mec_mbox_regs *base, uint32_t swi_ien_msk, uint32_t flags);
41 int mec_hal_mbox_girq_ctrl(struct mec_mbox_regs *base, uint8_t enable);
42 int mec_hal_mbox_girq_clr(struct mec_mbox_regs *base);
43 uint32_t mec_hal_mbox_girq_result(struct mec_mbox_regs *base);
45 int mec_hal_mbox_sirq_set(struct mec_mbox_regs *base, uint8_t bitmap);
46 int mec_hal_mbox_sirq_en_mask(struct mec_mbox_regs *base, uint8_t val, uint8_t mask);
48 int mec_hal_mbox_get_host_to_ec(struct mec_mbox_regs *base, uint8_t *data);
49 int mec_hal_mbox_set_host_to_ec(struct mec_mbox_regs *base, uint8_t data);
50 int mec_hal_mbox_get_ec_to_host(struct mec_mbox_regs *base, uint8_t *data);
51 int mec_hal_mbox_set_ec_to_host(struct mec_mbox_regs *base, uint8_t data);
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Dmec_kbc_api.h77 int mec_hal_kbc_init(struct mec_kbc_regs *base, uint32_t flags);
82 int mec_hal_kbc_activate(struct mec_kbc_regs *base, uint8_t enable, uint8_t flags);
84 int mec_hal_kbc_girq_en(struct mec_kbc_regs *base, uint32_t flags);
85 int mec_hal_kbc_girq_dis(struct mec_kbc_regs *base, uint32_t flags);
86 int mec_hal_kbc_girq_clr(struct mec_kbc_regs *base, uint32_t flags);
87 uint32_t mec_hal_kbc_girq_result(struct mec_kbc_regs *base);
88 int mec_hal_kbc_is_enabled(struct mec_kbc_regs *base);
89 int mec_hal_kbc_is_irq_gen_enabled(struct mec_kbc_regs *base);
90 uint8_t mec_hal_kbc_status(struct mec_kbc_regs *base);
96 void mec_hal_kbc_wr_data(struct mec_kbc_regs *base, uint8_t data, uint8_t data_is_aux);
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Dmec_i3c.c37 static struct mec_i3c_info const *get_i3c_info(uintptr_t base) in get_i3c_info() argument
42 if (p->base_addr == base) { in get_i3c_info()
58 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_I2C_Init()
61 const struct mec_i3c_info *info = get_i3c_info(ctx->base); in MEC_HAL_I3C_Controller_Clk_I2C_Init()
90 const struct mec_i3c_info *info = get_i3c_info(ctx->base); in MEC_HAL_I3C_Controller_Clk_Init()
113 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_Cfg()
138 struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base; in MEC_HAL_I3C_Target_Init()
141 const struct mec_i3c_info *info = get_i3c_info(ctx->base); in MEC_HAL_I3C_Target_Init()
187 struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base; in MEC_HAL_I3C_Target_MRL_MWL_update()
206 struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base; in MEC_HAL_I3C_Target_MRL_MWL_set()
[all …]
Dmec_dmac.c135 struct mec_dmac_regs *base = MEC_DMAC; in mec_hal_dmac_reset() local
137 base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MRST_Pos); in mec_hal_dmac_reset()
144 struct mec_dmac_regs *base = MEC_DMAC; in mec_hal_dmac_enable() local
147 base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos); in mec_hal_dmac_enable()
149 base->MCTRL &= (uint32_t)~MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos); in mec_hal_dmac_enable()
157 struct mec_dmac_regs *base = MEC_DMAC; in mec_hal_dmac_is_enabled() local
159 if (base->MCTRL & MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos)) { in mec_hal_dmac_is_enabled()
254 struct mec_dmac_regs *base = MEC_DMAC; in mec_hal_dma_chan_init() local
260 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_init()
276 struct mec_dmac_regs *base = MEC_DMAC; in mec_hal_dma_chan_intr_status() local
[all …]
Dmec_espi_pc.h159 int mec_hal_espi_iobar_cfg(struct mec_espi_io_regs *base, uint8_t ldn, uint16_t io_base,
161 int mec_hal_espi_iobar_enable(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t enable);
162 int mec_hal_espi_iobar_is_enabled(struct mec_espi_io_regs *base, uint8_t ldn);
163 uint32_t mec_hal_espi_iobar_mask(struct mec_espi_io_regs *base, uint8_t ldn);
164 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask);
167 int mec_hal_espi_bar_inhibit(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t inhibit);
168 int mec_hal_espi_bar_inhibit_msk(struct mec_espi_io_regs *base, uint8_t inhibit,
171 int mec_hal_espi_mbar_enable(struct mec_espi_mem_regs *base, uint8_t ldn, uint8_t enable);
172 int mec_hal_espi_mbar_is_enabled(struct mec_espi_mem_regs *base, uint8_t ldn);
173 int mec_hal_espi_mbar_cfg(struct mec_espi_mem_regs *base, uint8_t ldn, uint32_t mem_base,
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Dmec_ps2_api.h62 int mec_hal_ps2_init(struct mec_ps2_regs *base, uint32_t flags);
76 int mec_hal_ps2_girq_ctrl(struct mec_ps2_regs *base, uint8_t enable);
77 uint32_t mec_hal_ps2_girq_result(struct mec_ps2_regs *base);
78 int mec_hal_ps2_girq_clr(struct mec_ps2_regs *base);
80 int mec_hal_ps2_girq_wake_enable(struct mec_ps2_regs *base, uint8_t port, uint8_t enable);
81 uint32_t mec_hal_ps2_girq_wake_result(struct mec_ps2_regs *base, uint8_t port);
82 void mec_hal_ps2_girq_wake_clr(struct mec_ps2_regs *base, uint8_t port);
Dmec_ps2.c167 int mec_hal_ps2_girq_ctrl(struct mec_ps2_regs *base, uint8_t enable) in mec_hal_ps2_girq_ctrl() argument
169 const struct mec_ps2_info *psi = find_ps2_info((uint32_t)base); in mec_hal_ps2_girq_ctrl()
180 int mec_hal_ps2_girq_clr(struct mec_ps2_regs *base) in mec_hal_ps2_girq_clr() argument
182 const struct mec_ps2_info *psi = find_ps2_info((uint32_t)base); in mec_hal_ps2_girq_clr()
193 uint32_t mec_hal_ps2_girq_result(struct mec_ps2_regs *base) in mec_hal_ps2_girq_result() argument
195 const struct mec_ps2_info *psi = find_ps2_info((uint32_t)base); in mec_hal_ps2_girq_result()
204 int mec_hal_ps2_girq_wake_enable(struct mec_ps2_regs *base, uint8_t port, uint8_t enable) in mec_hal_ps2_girq_wake_enable() argument
206 const struct mec_ps2_info *psi = find_ps2_info((uint32_t)base); in mec_hal_ps2_girq_wake_enable()
227 uint32_t mec_hal_ps2_girq_wake_result(struct mec_ps2_regs *base, uint8_t port) in mec_hal_ps2_girq_wake_result() argument
229 const struct mec_ps2_info *psi = find_ps2_info((uint32_t)base); in mec_hal_ps2_girq_wake_result()
[all …]
Dmec_emi.c65 int mec_hal_emi_girq_ctrl(struct mec_emi_regs *base, uint8_t enable) in mec_hal_emi_girq_ctrl() argument
67 const struct mec_emi_info *info = find_emi_info((uintptr_t)base); in mec_hal_emi_girq_ctrl()
78 int mec_hal_emi_girq_clr(struct mec_emi_regs *base) in mec_hal_emi_girq_clr() argument
80 const struct mec_emi_info *info = find_emi_info((uintptr_t)base); in mec_hal_emi_girq_clr()
91 uint32_t mec_hal_emi_girq_result(struct mec_emi_regs *base) in mec_hal_emi_girq_result() argument
93 const struct mec_emi_info *info = find_emi_info((uintptr_t)base); in mec_hal_emi_girq_result()
Dmec_bclink.c53 int mec_hal_bcl_init(struct mec_bcl_regs *base, uint32_t flags) in mec_hal_bcl_init() argument
58 if ((uintptr_t)base != (uintptr_t)MEC_BCL0_BASE) { in mec_hal_bcl_init()
65 base->STATUS = MEC_BIT(MEC_BCL_STATUS_SRST_Pos) | MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_init()
68 base->CLKSEL = (flags & MEC_BCL_CFG_FREQ_DIV_MSK) >> MEC_BCL_CFG_FREQ_DIV_POS; in mec_hal_bcl_init()
73 base->STATUS &= (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_init()
Dmec_emi_api.h57 int mec_hal_emi_girq_ctrl(struct mec_emi_regs *base, uint8_t enable);
58 int mec_hal_emi_girq_clr(struct mec_emi_regs *base);
59 uint32_t mec_hal_emi_girq_result(struct mec_emi_regs *base);
Dmec_pwm.c39 uintptr_t base; member
60 static struct mec5_pwm_info const *get_pwm_info(uintptr_t base) in get_pwm_info() argument
65 if (p->base == base) { in get_pwm_info()
Dmec_bclink_api.h53 int mec_hal_bcl_init(struct mec_bcl_regs *base, uint32_t flags);
Dmec_bbled.c50 static inline uint32_t bbled_fast_idx(uintptr_t base) in bbled_fast_idx() argument
52 return (((uint32_t)base >> 8) & 0x3u); in bbled_fast_idx()
/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_mpu.c238 uint64_t base, in MSS_MPU_configure() argument
260 MSS_MPU(master_port)->PMPCFG[pmp_region].raw = (base | range) >> 2U; in MSS_MPU_configure()
276 uint64_t* base, in MSS_MPU_get_config() argument
288 *base = pmp_get_napot_base_and_range(reg, size); in MSS_MPU_get_config()
307 uint64_t base = reg; in pmp_get_napot_base_and_range() local
316 base = reg & ~mask; in pmp_get_napot_base_and_range()
324 return (base << 2U); in pmp_get_napot_base_and_range()
Dmss_mpu.h127 uint64_t base,
135 uint64_t* base,
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr_debug.h232 uint64_t base,
Dmss_ddr_debug.c751 void load_ddr_pattern(uint64_t base, uint32_t size, uint8_t pattern_offset) in load_ddr_pattern() argument
755 uint8_t *p_ddr = (uint8_t *)base; in load_ddr_pattern()
762 while(((uint64_t)p_ddr + pattern_length) < (base + size)) in load_ddr_pattern()

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