Lines Matching refs:base

82 static uint32_t uart_baud_divider_get(struct mec_uart_regs *base)  in uart_baud_divider_get()  argument
86 base->LCR |= MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
87 brdiv = base->IER; in uart_baud_divider_get()
89 brdiv |= base->RXB; in uart_baud_divider_get()
90 base->LCR &= (uint8_t)~MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
95 static void uart_prog_fifos(struct mec_uart_regs *base, uint8_t fifo_mode) in uart_prog_fifos() argument
101 base->FCR = temp; in uart_prog_fifos()
102 base->SCR = temp; in uart_prog_fifos()
106 base->FCR = temp; in uart_prog_fifos()
107 base->SCR = temp; in uart_prog_fifos()
110 int mec_hal_uart_tx_fifo_size(struct mec_uart_regs *base) in mec_hal_uart_tx_fifo_size() argument
112 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_tx_fifo_size()
118 if (base->SCR & MEC_BIT(MEC_UART_FCR_EXRF_Pos)) { in mec_hal_uart_tx_fifo_size()
125 int mec_hal_uart_rx_fifo_size(struct mec_uart_regs *base) in mec_hal_uart_rx_fifo_size() argument
127 return mec_hal_uart_tx_fifo_size(base); in mec_hal_uart_rx_fifo_size()
136 int mec_hal_uart_clock_freq_get(struct mec_uart_regs *base, uint32_t *clock_freq) in mec_hal_uart_clock_freq_get() argument
138 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_clock_freq_get()
145 if (base->CFGS & MEC_BIT(MEC_UART_CFGS_CLK_SRC_EXT_Pos)) { in mec_hal_uart_clock_freq_get()
150 brdiv = uart_baud_divider_get(base); in mec_hal_uart_clock_freq_get()
160 int mec_hal_uart_parity_set(struct mec_uart_regs *base, uint8_t parity) in mec_hal_uart_parity_set() argument
162 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_parity_set()
171 base->LSR = (base->LSR & (uint8_t)~(MEC_UART_LCR_PARITY_Msk | MEC_UART_LCR_PARITY_SEL_Msk)) in mec_hal_uart_parity_set()
177 int mec_hal_uart_parity_get(struct mec_uart_regs *base, uint8_t *parity) in mec_hal_uart_parity_get() argument
179 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_parity_get()
186 reg_val = base->LCR & (MEC_UART_LCR_PARITY_Msk | MEC_UART_LCR_PARITY_SEL_Msk); in mec_hal_uart_parity_get()
198 int mec_hal_uart_word_len_set(struct mec_uart_regs *base, uint8_t word_len) in mec_hal_uart_word_len_set() argument
200 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_word_len_set()
209 base->LCR = (base->LCR & (uint8_t)~MEC_UART_LCR_WORD_LEN_Msk) | val; in mec_hal_uart_word_len_set()
214 int mec_hal_uart_word_len_get(struct mec_uart_regs *base, uint8_t *word_len) in mec_hal_uart_word_len_get() argument
216 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_word_len_get()
223 temp = base->LCR & MEC_UART_LCR_WORD_LEN_Msk; in mec_hal_uart_word_len_get()
238 int mec_hal_uart_stop_bits_set(struct mec_uart_regs *base, uint8_t stop_bits) in mec_hal_uart_stop_bits_set() argument
240 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_stop_bits_set()
247 base->LCR |= MEC_BIT(MEC_UART_LCR_STOP_BITS_Pos); in mec_hal_uart_stop_bits_set()
249 base->LCR &= (uint8_t)~MEC_BIT(MEC_UART_LCR_STOP_BITS_Pos); in mec_hal_uart_stop_bits_set()
255 int mec_hal_uart_stop_bits_get(struct mec_uart_regs *base, uint8_t *stop_bits) in mec_hal_uart_stop_bits_get() argument
257 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_stop_bits_get()
263 if (base->LCR & MEC_BIT(MEC_UART_LCR_STOP_BITS_Pos)) { in mec_hal_uart_stop_bits_get()
272 int mec_hal_uart_fifo_control(struct mec_uart_regs *base, uint8_t fifo_mode) in mec_hal_uart_fifo_control() argument
274 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_fifo_control()
280 uart_prog_fifos(base, fifo_mode); in mec_hal_uart_fifo_control()
535 int mec_hal_uart_baud_rate_set(struct mec_uart_regs *base, uint32_t baud, uint32_t extclk_hz) in mec_hal_uart_baud_rate_set() argument
537 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_baud_rate_set()
544 ret = prog_baud_rate(base, baud, extclk_hz); in mec_hal_uart_baud_rate_set()
549 int mec_hal_uart_intr_control(struct mec_uart_regs *base, uint8_t enmask) in mec_hal_uart_intr_control() argument
551 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_intr_control()
557 base->IER = enmask & (MEC_UART_IER_ERDAI_Msk | MEC_UART_IER_ETHREI_Msk in mec_hal_uart_intr_control()
567 int mec_hal_uart_intr_mask(struct mec_uart_regs *base, uint8_t msk, uint8_t val) in mec_hal_uart_intr_mask() argument
569 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_intr_mask()
575 base->IER = (base->IER & ~msk) | val; in mec_hal_uart_intr_mask()
580 int mec_hal_uart_raw_status(struct mec_uart_regs *base, enum mec_uart_sts_reg regid, in mec_hal_uart_raw_status() argument
583 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_raw_status()
591 *status = base->IIR; in mec_hal_uart_raw_status()
594 *status = base->LSR; in mec_hal_uart_raw_status()
597 *status = base->MSR; in mec_hal_uart_raw_status()
607 int mec_hal_uart_pending_status(struct mec_uart_regs *base, enum mec_uart_ipend *ipend) in mec_hal_uart_pending_status() argument
609 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_pending_status()
616 iir = base->IIR; in mec_hal_uart_pending_status()
646 int mec_hal_uart_is_rx_data(struct mec_uart_regs *base) in mec_hal_uart_is_rx_data() argument
648 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_is_rx_data()
654 if (base->LSR & MEC_BIT(MEC_UART_LSR_DRDY_Pos)) { in mec_hal_uart_is_rx_data()
662 int mec_hal_uart_is_tx_fifo_empty(struct mec_uart_regs *base) in mec_hal_uart_is_tx_fifo_empty() argument
664 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_is_tx_fifo_empty()
670 if (base->LSR & MEC_BIT(MEC_UART_LSR_THRE_Pos)) { in mec_hal_uart_is_tx_fifo_empty()
678 int mec_hal_uart_is_tx_empty(struct mec_uart_regs *base) in mec_hal_uart_is_tx_empty() argument
680 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_is_tx_empty()
686 if (base->LSR & MEC_BIT(MEC_UART_LSR_THSE_Pos)) { in mec_hal_uart_is_tx_empty()
693 int mec_hal_uart_dtr_rts_set(struct mec_uart_regs *base, uint8_t sel_rts, in mec_hal_uart_dtr_rts_set() argument
696 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_dtr_rts_set()
708 base->MCR |= MEC_BIT(bitpos); in mec_hal_uart_dtr_rts_set()
710 base->MCR &= (uint8_t)~MEC_BIT(bitpos); in mec_hal_uart_dtr_rts_set()
737 int mec_hal_uart_tx_byte(struct mec_uart_regs *base, uint8_t data) in mec_hal_uart_tx_byte() argument
739 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_tx_byte()
746 if (base->IIR & MEC_UART_IIR_FIFO_STATE_Msk) { /* FIFOs enabled? */ in mec_hal_uart_tx_byte()
747 if (!(base->LSRB & MEC_BIT(MEC_UART_LSRB_TXF_FULL_STS_Pos))) { /* if not full */ in mec_hal_uart_tx_byte()
748 base->TXB = data; in mec_hal_uart_tx_byte()
757 if (base->LSR & MEC_BIT(MEC_UART_LSR_THRE_Pos)) { in mec_hal_uart_tx_byte()
758 base->TXB = data; in mec_hal_uart_tx_byte()
765 int mec_hal_uart_tx(struct mec_uart_regs * base, const uint8_t *data, size_t datasz) in mec_hal_uart_tx() argument
767 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_tx()
779 if (base->IIR & MEC_UART_IIR_FIFO_STATE_Msk) { /* FIFOs enabled? */ in mec_hal_uart_tx()
781 if (!(base->LSRB & MEC_BIT(MEC_UART_LSRB_TXF_FULL_STS_Pos))) { in mec_hal_uart_tx()
782 base->TXB = data[n++]; in mec_hal_uart_tx()
791 if (base->LSR & MEC_BIT(MEC_UART_LSR_THRE_Pos)) { in mec_hal_uart_tx()
798 base->TXB = data[n]; in mec_hal_uart_tx()
807 int mec_hal_uart_rx_byte(struct mec_uart_regs *base, uint8_t *data) in mec_hal_uart_rx_byte() argument
809 const struct mec_uart_info *info = get_uart_info(base); in mec_hal_uart_rx_byte()
817 lsr = base->LSR; in mec_hal_uart_rx_byte()
818 if (base->LSR & MEC_BIT(MEC_UART_LSR_DRDY_Pos)) { in mec_hal_uart_rx_byte()
819 temp = base->RXB; in mec_hal_uart_rx_byte()