61 static struct mec_qspi_info const *qspi_get_info(struct mec_qspi_regs *base)  in qspi_get_info()  argument
66         if (p->base_addr == (uintptr_t)base) {  in qspi_get_info()
81 static uint32_t qspi_get_freq(struct mec_qspi_regs *base)  in qspi_get_freq()  argument
84     uint32_t fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in qspi_get_freq()
93 uint32_t mec_hal_qspi_get_freq(struct mec_qspi_regs *base)  in mec_hal_qspi_get_freq()  argument
95     if (!base) {  in mec_hal_qspi_get_freq()
99     return qspi_get_freq(base);  in mec_hal_qspi_get_freq()
102 uint32_t mec_hal_qspi_freq_div(struct mec_qspi_regs *base)  in mec_hal_qspi_freq_div()  argument
106     if ((uintptr_t)base == (uintptr_t)(MEC_QSPI0_BASE)) {  in mec_hal_qspi_freq_div()
107         fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in mec_hal_qspi_freq_div()
121 uint16_t mec_hal_qspi_freq_div_raw(struct mec_qspi_regs *base)  in mec_hal_qspi_freq_div_raw()  argument
123     if ((uintptr_t)base != (uintptr_t)(MEC_QSPI0_BASE)) {  in mec_hal_qspi_freq_div_raw()
127     return (uint16_t)((base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos);  in mec_hal_qspi_freq_div_raw()
158 static uint32_t qspi_byte_time_ns(struct mec_qspi_regs *base)  in qspi_byte_time_ns()  argument
160     uint32_t clkdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in qspi_byte_time_ns()
161     uint32_t iom = (base->CTRL & MEC_QSPI_CTRL_IFM_Msk) >> MEC_QSPI_CTRL_IFM_Pos;  in qspi_byte_time_ns()
186 int mec_hal_qspi_byte_time_ns(struct mec_qspi_regs *base, uint32_t *btime_ns)  in mec_hal_qspi_byte_time_ns()  argument
188     if ((!base) || (!btime_ns)) {  in mec_hal_qspi_byte_time_ns()
192     *btime_ns = qspi_byte_time_ns(base);  in mec_hal_qspi_byte_time_ns()
220 static void qspi_set_freq(struct mec_qspi_regs *base, uint32_t freqhz)  in qspi_set_freq()  argument
224     base->MODE = ((base->MODE & (uint32_t)~MEC_QSPI_MODE_CLKDIV_Msk)  in qspi_set_freq()
228 int mec_hal_qspi_set_freq(struct mec_qspi_regs *base, uint32_t freqhz)  in mec_hal_qspi_set_freq()  argument
230     if (!base) {  in mec_hal_qspi_set_freq()
234     qspi_set_freq(base, freqhz);  in mec_hal_qspi_set_freq()
239 static void qspi_intr_clr_dis(struct mec_qspi_regs *base)  in qspi_intr_clr_dis()  argument
241     const struct mec_qspi_info *info = qspi_get_info(base);  in qspi_intr_clr_dis()
247     base->INTR_CTRL = 0;  in qspi_intr_clr_dis()
248     base->STATUS = UINT32_MAX;  in qspi_intr_clr_dis()
253 static void qspi_reset(struct mec_qspi_regs *base)  in qspi_reset()  argument
256     base->MODE |= MEC_BIT(MEC_QSPI_MODE_SRST_Pos);  in qspi_reset()
258     qspi_intr_clr_dis(base);  in qspi_reset()
262 void mec_hal_qspi_girq_clr(struct mec_qspi_regs *base)  in mec_hal_qspi_girq_clr()  argument
264     (void)base;  in mec_hal_qspi_girq_clr()
269 void mec_hal_qspi_girq_ctrl(struct mec_qspi_regs *base, uint8_t enable)  in mec_hal_qspi_girq_ctrl()  argument
271     (void)base;  in mec_hal_qspi_girq_ctrl()
277 uint32_t mec_hal_qspi_girq_is_result(struct mec_qspi_regs *base)  in mec_hal_qspi_girq_is_result()  argument
279     (void)base;  in mec_hal_qspi_girq_is_result()
284 int mec_hal_qspi_reset(struct mec_qspi_regs *base)  in mec_hal_qspi_reset()  argument
286     if (!base) {  in mec_hal_qspi_reset()
290     qspi_reset(base);  in mec_hal_qspi_reset()
295 int mec_hal_qspi_reset_sr(struct mec_qspi_regs *base)  in mec_hal_qspi_reset_sr()  argument
299     if (!base) {  in mec_hal_qspi_reset_sr()
305     saved[0] = base->MODE & (MEC_QSPI_MODE_CPOL_Msk | MEC_QSPI_MODE_CPHA_MOSI_Msk  in mec_hal_qspi_reset_sr()
307     saved[1] = base->CSTM;  in mec_hal_qspi_reset_sr()
308     saved[2] = base->TAPSS;  in mec_hal_qspi_reset_sr()
309     saved[3] = base->TAPSA;  in mec_hal_qspi_reset_sr()
310     saved[4] = base->TAPSC;  in mec_hal_qspi_reset_sr()
312     qspi_reset(base);  in mec_hal_qspi_reset_sr()
315     base->MODE = saved[0];  in mec_hal_qspi_reset_sr()
316     base->CSTM = saved[1];  in mec_hal_qspi_reset_sr()
317     base->TAPSS = saved[2];  in mec_hal_qspi_reset_sr()
318     base->TAPSA = saved[3];  in mec_hal_qspi_reset_sr()
319     base->TAPSC = saved[4];  in mec_hal_qspi_reset_sr()
328 static void qspi_cs1_freq(struct mec_qspi_regs *base, uint32_t freq)  in qspi_cs1_freq()  argument
334         base->ALT1_MODE = (fdiv << MEC_QSPI_MODE_CLKDIV_Pos) & MEC_QSPI_MODE_CLKDIV_Msk;  in qspi_cs1_freq()
335         base->ALT1_MODE |= MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos);  in qspi_cs1_freq()
337         base->ALT1_MODE = 0u;  in qspi_cs1_freq()
341 int mec_hal_qspi_cs1_freq(struct mec_qspi_regs *base, uint32_t freq)  in mec_hal_qspi_cs1_freq()  argument
343     if (!base) {  in mec_hal_qspi_cs1_freq()
347     qspi_cs1_freq(base, freq);  in mec_hal_qspi_cs1_freq()
352 static uint32_t qspi_compute_byte_time_ns(struct mec_qspi_regs *base)  in qspi_compute_byte_time_ns()  argument
355     uint32_t fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in qspi_compute_byte_time_ns()
359     if ((base->MODE & MEC_QSPI_MODE_CS_Msk) &&  in qspi_compute_byte_time_ns()
360         (base->ALT1_MODE & MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos))) {  in qspi_compute_byte_time_ns()
361         fdiv = ((base->ALT1_MODE & MEC_QSPI_ALT1_MODE_CS1_ALT_CLKDIV_Msk)  in qspi_compute_byte_time_ns()
377 static void qspi_cs_select(struct mec_qspi_regs *base, enum mec_qspi_cs cs)  in qspi_cs_select()  argument
379     uint32_t mode = base->MODE & (uint32_t)~MEC_QSPI_MODE_CS_Msk;  in qspi_cs_select()
382     base->MODE = mode;  in qspi_cs_select()
385 int mec_hal_qspi_cs_select(struct mec_qspi_regs *base, enum mec_qspi_cs cs)  in mec_hal_qspi_cs_select()  argument
387     if (!base || (cs >= MEC_QSPI_CS_MAX)) {  in mec_hal_qspi_cs_select()
391     qspi_cs_select(base, cs);  in mec_hal_qspi_cs_select()
399 static void qspi_spi_signal_mode(struct mec_qspi_regs *base, enum mec_qspi_signal_mode spi_mode)  in qspi_spi_signal_mode()  argument
401     uint32_t freq = qspi_get_freq(base);  in qspi_spi_signal_mode()
410     base->MODE = (base->MODE & ~0x700u) | (hwsm << MEC_QSPI_MODE_CPOL_Pos);  in qspi_spi_signal_mode()
414 int mec_hal_qspi_spi_signal_mode(struct mec_qspi_regs *base, enum mec_qspi_signal_mode spi_mode)  in mec_hal_qspi_spi_signal_mode()  argument
416     if ((base == NULL) || (spi_mode >= MEC_SPI_SIGNAL_MODE_MAX)) {  in mec_hal_qspi_spi_signal_mode()
420     qspi_spi_signal_mode(base, spi_mode);  in mec_hal_qspi_spi_signal_mode()
425 int mec_hal_qspi_sampling_phase_pol(struct mec_qspi_regs *base, uint8_t phpol)  in mec_hal_qspi_sampling_phase_pol()  argument
427     if (!base) {  in mec_hal_qspi_sampling_phase_pol()
431     base->MODE = (base->MODE & ~0x700u) | ((uint32_t)(phpol & 0x7u) << 8);  in mec_hal_qspi_sampling_phase_pol()
451 static void qspi_io(struct mec_qspi_regs *base, enum mec_qspi_io io)  in qspi_io()  argument
453     base->CTRL = (base->CTRL & (uint32_t)~MEC_QSPI_CTRL_IFM_Msk) | qspi_ifm(io);  in qspi_io()
456 int mec_hal_qspi_io(struct mec_qspi_regs *base, enum mec_qspi_io io)  in mec_hal_qspi_io()  argument
458     if (!base || (io >= MEC_QSPI_IO_MAX)) {  in mec_hal_qspi_io()
462     qspi_io(base, io);  in mec_hal_qspi_io()
479 int mec_hal_qspi_cs_timing_adjust(struct mec_qspi_regs *base, enum mec_qspi_cstm field,  in mec_hal_qspi_cs_timing_adjust()  argument
482     if ((!base) || (field >= MEC_QSPI_CSTM_MAX)) {  in mec_hal_qspi_cs_timing_adjust()
489     base->CSTM = (base->CSTM & ~(msk0 << pos)) | ((val & msk0) << pos);  in mec_hal_qspi_cs_timing_adjust()
494 int mec_hal_qspi_cs_timing(struct mec_qspi_regs *base, uint32_t cs_timing)  in mec_hal_qspi_cs_timing()  argument
496     if (!base) {  in mec_hal_qspi_cs_timing()
500     base->CSTM = cs_timing;  in mec_hal_qspi_cs_timing()
505 int mec_hal_qspi_tap_select(struct mec_qspi_regs *base, uint8_t sel_sck_tap, uint8_t sel_ctrl_tap)  in mec_hal_qspi_tap_select()  argument
509     if (!base) {  in mec_hal_qspi_tap_select()
515 …base->TAPSS = (base->TAPSS & (uint32_t)~(MEC_QSPI_TAPSS_TSCK_Msk | MEC_QSPI_TAPSS_TSCK_Msk)) | tap…  in mec_hal_qspi_tap_select()
521 int mec_hal_qspi_init(struct mec_qspi_regs *base,  in mec_hal_qspi_init()  argument
527     const struct mec_qspi_info *info = qspi_get_info(base);  in mec_hal_qspi_init()
534     mec_hal_qspi_reset_sr(base);  in mec_hal_qspi_init()
535     qspi_set_freq(base, freq_hz);  in mec_hal_qspi_init()
536     qspi_spi_signal_mode(base, spi_signal_mode);  in mec_hal_qspi_init()
537     qspi_io(base, iom);  in mec_hal_qspi_init()
538     qspi_cs_select(base, chip_sel);  in mec_hal_qspi_init()
540     base->MODE |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos);  in mec_hal_qspi_init()
590 int mec_hal_qspi_force_stop(struct mec_qspi_regs *base)  in mec_hal_qspi_force_stop()  argument
594     if (!base) {  in mec_hal_qspi_force_stop()
598     base->EXE = MEC_BIT(MEC_QSPI_EXE_STOP_Pos);  in mec_hal_qspi_force_stop()
601     btime_ns = qspi_compute_byte_time_ns(base);  in mec_hal_qspi_force_stop()
606     while (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_ACTIVE_Pos)) {  in mec_hal_qspi_force_stop()
616 int mec_hal_qspi_done(struct mec_qspi_regs *base)  in mec_hal_qspi_done()  argument
620     if (!base) {  in mec_hal_qspi_done()
624     qsts = base->STATUS;  in mec_hal_qspi_done()
637 uint32_t mec_hal_qspi_hw_status(struct mec_qspi_regs *base)  in mec_hal_qspi_hw_status()  argument
639     if (!base) {  in mec_hal_qspi_hw_status()
643     return base->STATUS;  in mec_hal_qspi_hw_status()
646 int mec_hal_qspi_hw_status_clr(struct mec_qspi_regs *base, uint32_t msk)  in mec_hal_qspi_hw_status_clr()  argument
648     if (!base) {  in mec_hal_qspi_hw_status_clr()
652     base->STATUS = msk;  in mec_hal_qspi_hw_status_clr()
657 static void qspi_intr_ctrl(struct mec_qspi_regs *base, int enable)  in qspi_intr_ctrl()  argument
669     base->INTR_CTRL = qien;  in qspi_intr_ctrl()
672 int mec_hal_qspi_intr_ctrl(struct mec_qspi_regs *base, int enable)  in mec_hal_qspi_intr_ctrl()  argument
674     if (!base) {  in mec_hal_qspi_intr_ctrl()
678     qspi_intr_ctrl(base, enable);  in mec_hal_qspi_intr_ctrl()
683 int mec_hal_qspi_intr_ctrl_msk(struct mec_qspi_regs *base, int enable, uint32_t msk)  in mec_hal_qspi_intr_ctrl_msk()  argument
685     if (!base) {  in mec_hal_qspi_intr_ctrl_msk()
690         base->INTR_CTRL |= msk;  in mec_hal_qspi_intr_ctrl_msk()
692         base->INTR_CTRL &= (uint32_t)~msk;  in mec_hal_qspi_intr_ctrl_msk()
698 int mec_hal_qspi_tx_fifo_is_empty(struct mec_qspi_regs *base)  in mec_hal_qspi_tx_fifo_is_empty()  argument
700     if (base) {  in mec_hal_qspi_tx_fifo_is_empty()
701         if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBE_Pos)) {  in mec_hal_qspi_tx_fifo_is_empty()
709 int mec_hal_qspi_tx_fifo_is_full(struct mec_qspi_regs *base)  in mec_hal_qspi_tx_fifo_is_full()  argument
711     if (base) {  in mec_hal_qspi_tx_fifo_is_full()
712         if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBF_Pos)) {  in mec_hal_qspi_tx_fifo_is_full()
720 int mec_hal_qspi_rx_fifo_is_empty(struct mec_qspi_regs *base)  in mec_hal_qspi_rx_fifo_is_empty()  argument
722     if (base) {  in mec_hal_qspi_rx_fifo_is_empty()
723         if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBE_Pos)) {  in mec_hal_qspi_rx_fifo_is_empty()
731 int mec_hal_qspi_rx_fifo_is_full(struct mec_qspi_regs *base)  in mec_hal_qspi_rx_fifo_is_full()  argument
733     if (base) {  in mec_hal_qspi_rx_fifo_is_full()
734         if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBF_Pos)) {  in mec_hal_qspi_rx_fifo_is_full()
742 int mec_hal_qspi_start(struct mec_qspi_regs *base, uint32_t ien_mask)  in mec_hal_qspi_start()  argument
744     if (!base) {  in mec_hal_qspi_start()
748     base->STATUS = UINT32_MAX;  in mec_hal_qspi_start()
749     base->INTR_CTRL = ien_mask;  in mec_hal_qspi_start()
750     base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos);  in mec_hal_qspi_start()
817 static void qspi_ldma_init(struct mec_qspi_regs *base)  in qspi_ldma_init()  argument
819     base->MODE &= ~(MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos) | MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos));  in qspi_ldma_init()
820     base->LDMA_RXEN = 0u;  in qspi_ldma_init()
821     base->LDMA_TXEN = 0u;  in qspi_ldma_init()
822     base->RX_LDMA_CHAN[0].CTRL = 0;  in qspi_ldma_init()
823     base->RX_LDMA_CHAN[1].CTRL = 0;  in qspi_ldma_init()
824     base->RX_LDMA_CHAN[2].CTRL = 0;  in qspi_ldma_init()
825     base->TX_LDMA_CHAN[0].CTRL = 0;  in qspi_ldma_init()
826     base->TX_LDMA_CHAN[1].CTRL = 0;  in qspi_ldma_init()
827     base->TX_LDMA_CHAN[2].CTRL = 0;  in qspi_ldma_init()
836 static void qspi_ldma_cfg1(struct mec_qspi_regs *base, const uint8_t *txb,  in qspi_ldma_cfg1()  argument
854     base->RX_LDMA_CHAN[0].LEN = lenb;  in qspi_ldma_cfg1()
856         base->RX_LDMA_CHAN[0].MEM_START = (uintptr_t)rxb;  in qspi_ldma_cfg1()
859         base->RX_LDMA_CHAN[0].MEM_START = (uintptr_t)&base->BCNT_STS;  in qspi_ldma_cfg1()
861     base->RX_LDMA_CHAN[0].CTRL = rctrl;  in qspi_ldma_cfg1()
864         base->TX_LDMA_CHAN[0].LEN = lenb;  in qspi_ldma_cfg1()
865         base->TX_LDMA_CHAN[0].MEM_START = (uintptr_t)txb;  in qspi_ldma_cfg1()
866         base->TX_LDMA_CHAN[0].CTRL = wctrl | MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_INCRA_Pos);  in qspi_ldma_cfg1()
913 static int qspi_gen_ts_clocks(struct mec_qspi_regs *base, uint32_t nclocks, uint32_t flags)  in qspi_gen_ts_clocks()  argument
915     uint32_t descr = qspi_clocks_to_bits(base->CTRL, nclocks);  in qspi_gen_ts_clocks()
920     descr |= (base->CTRL & MEC_QSPI_CTRL_IFM_Msk);  in qspi_gen_ts_clocks()
927     base->DESCR[0] = descr;  in qspi_gen_ts_clocks()
933     qspi_intr_ctrl(base, ien);  in qspi_gen_ts_clocks()
937         base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos);  in qspi_gen_ts_clocks()
952 int mec_hal_qspi_ldma(struct mec_qspi_regs *base, const uint8_t *txb,  in mec_hal_qspi_ldma()  argument
959     if (!base) {  in mec_hal_qspi_ldma()
967     qspi_ldma_init(base);  in mec_hal_qspi_ldma()
970         base->EXE = MEC_BIT(MEC_QSPI_EXE_CLRF_Pos);  in mec_hal_qspi_ldma()
971     } else if (base->BCNT_STS) { /* data left in TX and/or RX FIFO */  in mec_hal_qspi_ldma()
975     base->STATUS = UINT32_MAX;  in mec_hal_qspi_ldma()
977     base->CTRL |= MEC_BIT(MEC_QSPI_CTRL_DESCR_MODE_Pos);  in mec_hal_qspi_ldma()
981         return qspi_gen_ts_clocks(base, lenb, flags);  in mec_hal_qspi_ldma()
983         descr_init = descr_ldma_init(txb, base->CTRL & MEC_QSPI_CTRL_IFM_Msk);  in mec_hal_qspi_ldma()
986     descr_init = descr_ldma_init(txb, base->CTRL & MEC_QSPI_CTRL_IFM_Msk);  in mec_hal_qspi_ldma()
1003         base->DESCR[didx] = descr;  in mec_hal_qspi_ldma()
1004         base->LDMA_RXEN |= MEC_BIT(didx);  in mec_hal_qspi_ldma()
1006             base->LDMA_TXEN |= MEC_BIT(didx);  in mec_hal_qspi_ldma()
1012     descr = base->DESCR[didx - 1u] | MEC_BIT(MEC_QSPI_DESCR_LAST_Pos);  in mec_hal_qspi_ldma()
1016     base->DESCR[didx - 1u] = descr;  in mec_hal_qspi_ldma()
1022     qspi_ldma_cfg1(base, txb, rxb, lenb);  in mec_hal_qspi_ldma()
1024     base->MODE |= (MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos) | MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos));  in mec_hal_qspi_ldma()
1030     qspi_intr_ctrl(base, ien);  in mec_hal_qspi_ldma()
1034         base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos);  in mec_hal_qspi_ldma()