113 int mec_hal_espi_iobar_cfg(struct mec_espi_io_regs *base, uint8_t ldn,  in mec_hal_espi_iobar_cfg()  argument
120     if (!base || !ldi) {  in mec_hal_espi_iobar_cfg()
131     base->HOST_BAR[idx] = bar_val;  in mec_hal_espi_iobar_cfg()
134         base->HOST_BAR[idx] |= MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos);  in mec_hal_espi_iobar_cfg()
140 int mec_hal_espi_iobar_enable(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t enable)  in mec_hal_espi_iobar_enable()  argument
145     if (!base || !ldi) {  in mec_hal_espi_iobar_enable()
156         base->HOST_BAR[idx] |= MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos);  in mec_hal_espi_iobar_enable()
158         base->HOST_BAR[idx] &= (uint32_t)~MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos);  in mec_hal_espi_iobar_enable()
164 int mec_hal_espi_iobar_is_enabled(struct mec_espi_io_regs *base, uint8_t ldn)  in mec_hal_espi_iobar_is_enabled()  argument
169     if (!base || !ldi) {  in mec_hal_espi_iobar_is_enabled()
178     if (base->HOST_BAR[idx] & MEC_BIT(MEC_ESPI_IO_HOST_BAR_VALID_Pos)) {  in mec_hal_espi_iobar_is_enabled()
185 uint32_t mec_hal_espi_iobar_mask(struct mec_espi_io_regs *base, uint8_t ldn)  in mec_hal_espi_iobar_mask()  argument
190     if (!base || !ldi) {  in mec_hal_espi_iobar_mask()
200     return (base->EC_LDN_MSK[idx] & 0xffu);  in mec_hal_espi_iobar_mask()
208 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask)  in mec_hal_espi_iobar_mask_set()  argument
212     if (!base || !ldi) {  in mec_hal_espi_iobar_mask_set()
221     uint32_t temp = base->EC_LDN_MSK[idx];  in mec_hal_espi_iobar_mask_set()
226     *((volatile uint32_t *)&base->EC_LDN_MSK[idx]) = temp;  in mec_hal_espi_iobar_mask_set()
239 int mec_hal_espi_mbar_cfg(struct mec_espi_mem_regs *base, uint8_t ldn,  in mec_hal_espi_mbar_cfg()  argument
245     if (!base || !ldi) {  in mec_hal_espi_mbar_cfg()
255     volatile struct mec_espi_mem_host_mem_bar_regs *mbar = &base->HOST_MEM_BAR[idx];  in mec_hal_espi_mbar_cfg()
268 int mec_hal_espi_sram_bar_cfg(struct mec_espi_mem_regs *base,  in mec_hal_espi_sram_bar_cfg()  argument
274     if (!base || !barcfg || (sram_bar_id >= MEC_ESPI_SRAM_BAR_MAX)  in mec_hal_espi_sram_bar_cfg()
280     base->EC_SRAM_BAR[sram_bar_id].VASZ = 0; /* disable before modification */  in mec_hal_espi_sram_bar_cfg()
286     base->EC_SRAM_BAR[sram_bar_id].VASZ = (uint16_t)temp;  in mec_hal_espi_sram_bar_cfg()
288     base->EC_SRAM_BAR[sram_bar_id].EC_SRAM_ADDR_15_0 = barcfg->maddr & 0xffffu;  in mec_hal_espi_sram_bar_cfg()
289     base->EC_SRAM_BAR[sram_bar_id].EC_SRAM_ADDR_31_16 = (uint16_t)(barcfg->maddr >> 16);  in mec_hal_espi_sram_bar_cfg()
291     base->HOST_SRAM_BAR[sram_bar_id].HOST_ADDR_15_0 = barcfg->haddr & 0xffffu;  in mec_hal_espi_sram_bar_cfg()
292     base->HOST_SRAM_BAR[sram_bar_id].HOST_ADDR_31_16 = (uint16_t)(barcfg->haddr >> 16);  in mec_hal_espi_sram_bar_cfg()
295         base->EC_SRAM_BAR[sram_bar_id].VASZ |= MEC_BIT(MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID_Pos);  in mec_hal_espi_sram_bar_cfg()
306 int mec_hal_espi_mbar_extended_addr_set(struct mec_espi_mem_regs *base, uint32_t extended_addr)  in mec_hal_espi_mbar_extended_addr_set()  argument
308     if (!base) {  in mec_hal_espi_mbar_extended_addr_set()
312     base->MBAR_HOST_EXTEND = extended_addr;  in mec_hal_espi_mbar_extended_addr_set()
317 int mec_hal_espi_sram_bar_extended_addr_set(struct mec_espi_mem_regs *base,  in mec_hal_espi_sram_bar_extended_addr_set()  argument
320     if (!base) {  in mec_hal_espi_sram_bar_extended_addr_set()
324     base->SRAM_BAR_HOST_EXTEND = extended_addr;  in mec_hal_espi_sram_bar_extended_addr_set()
329 int mec_hal_espi_mbar_enable(struct mec_espi_mem_regs *base, uint8_t ldn, uint8_t enable)  in mec_hal_espi_mbar_enable()  argument
334     if (!base || !ldi) {  in mec_hal_espi_mbar_enable()
344     volatile struct mec_espi_mem_host_mem_bar_regs *mbar = &base->HOST_MEM_BAR[idx];  in mec_hal_espi_mbar_enable()
355 int mec_hal_espi_mbar_is_enabled(struct mec_espi_mem_regs *base, uint8_t ldn)  in mec_hal_espi_mbar_is_enabled()  argument
360     if (!base || !ldi) {  in mec_hal_espi_mbar_is_enabled()
370     volatile struct mec_espi_mem_host_mem_bar_regs *mbar = &base->HOST_MEM_BAR[idx];  in mec_hal_espi_mbar_is_enabled()
380 int mec_hal_espi_bar_inhibit(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t inhibit)  in mec_hal_espi_bar_inhibit()  argument
384     if (!base || !ldi) {  in mec_hal_espi_bar_inhibit()
394             base->PCBINH[0] |= MEC_BIT(ldn);  in mec_hal_espi_bar_inhibit()
396             base->PCBINH[0] &= (uint32_t)~MEC_BIT(ldn);  in mec_hal_espi_bar_inhibit()
401             base->PCBINH[1] |= MEC_BIT(ldn);  in mec_hal_espi_bar_inhibit()
403             base->PCBINH[1] &= (uint32_t)~MEC_BIT(ldn);  in mec_hal_espi_bar_inhibit()
410 int mec_hal_espi_bar_inhibit_msk(struct mec_espi_io_regs *base, uint8_t inhibit,  in mec_hal_espi_bar_inhibit_msk()  argument
413     if (!base) {  in mec_hal_espi_bar_inhibit_msk()
418         base->PCBINH[0] |= msklo;  in mec_hal_espi_bar_inhibit_msk()
419         base->PCBINH[1] |= mskhi;  in mec_hal_espi_bar_inhibit_msk()
421         base->PCBINH[0] &= ~msklo;  in mec_hal_espi_bar_inhibit_msk()
422         base->PCBINH[1] &= ~mskhi;  in mec_hal_espi_bar_inhibit_msk()