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Searched refs:CTRL (Results 1 – 25 of 53) sorted by relevance

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/hal_microchip-latest/mec5/drivers/
Dmec_btimer.c110 regs->CTRL = MEC_BIT(MEC_BTMR_CTRL_RESET_Pos); in mec_hal_btimer_init()
111 regs->CTRL = ((freq_div - 1u) & MEC5_BTMR_PRESCALE_MSK0) << MEC_BTMR_CTRL_PRESCALE_Pos; in mec_hal_btimer_init()
117 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos); in mec_hal_btimer_init()
120 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_RESTART_Pos); in mec_hal_btimer_init()
124 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_CNT_DIR_Pos); in mec_hal_btimer_init()
132 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_START_Pos); in mec_hal_btimer_init()
167 ctrl = regs->CTRL; in mec_hal_btimer_reset()
168 regs->CTRL = MEC_BIT(MEC_BTMR_CTRL_RESET_Pos); in mec_hal_btimer_reset()
172 regs->CTRL = (regs->CTRL & (uint32_t)~msk) | (ctrl & msk); in mec_hal_btimer_reset()
180 if (regs->CTRL & MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos)) { in mec_hal_btimer_is_enabled()
[all …]
Dmec_peci.c31 regs->CTRL = (MEC_BIT(MEC_PECI_CTRL_RST_Pos) | MEC_BIT(MEC_PECI_CTRL_FRST_Pos) in peci_reset()
37 regs->CTRL = MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in peci_reset()
103 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_MIEN_Pos); in mec_hal_peci_init()
107 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_init()
122 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_enable()
124 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_enable()
139 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_RST_Pos); in mec_hal_peci_ctrl_reset()
141 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_RST_Pos); in mec_hal_peci_ctrl_reset()
156 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_FRST_Pos); in mec_hal_peci_fifo_reset()
158 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_FRST_Pos); in mec_hal_peci_fifo_reset()
[all …]
Dmec_rtimer_api.h54 regs->CTRL |= MEC_BIT(MEC_RTMR_CTRL_AUTO_RELOAD_Pos); in mec_hal_rtimer_auto_reload()
56 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_RTMR_CTRL_AUTO_RELOAD_Pos); in mec_hal_rtimer_auto_reload()
62 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_RTMR_CTRL_START_Pos); in mec_hal_rtimer_stop()
67 regs->CTRL |= MEC_BIT(MEC_RTMR_CTRL_START_Pos); in mec_hal_rtimer_start()
72 return (regs->CTRL & MEC_BIT(MEC_RTMR_CTRL_START_Pos)) ? true : false; in mec_hal_rtimer_is_started()
96 regs->CTRL |= MEC_BIT(MEC_RTMR_CTRL_FW_HALT_Pos); in mec_hal_rtimer_halt()
101 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_RTMR_CTRL_FW_HALT_Pos); in mec_hal_rtimer_unhalt()
116 regs->CTRL = 0U; in mec_hal_rtimer_stop_and_load()
117 regs->CTRL = MEC_BIT(MEC_RTMR_CTRL_ENABLE_Pos); in mec_hal_rtimer_stop_and_load()
119 regs->CTRL = start_val; in mec_hal_rtimer_stop_and_load()
Dmec_wdt.c46 regs->CTRL = ctrl; in mec_hal_wdt_init()
73 regs->CTRL = ctrl; in mec_hal_wdt_init()
80 if (regs->CTRL & MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos)) { in mec_hal_wdt_is_enabled()
89 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_enable()
94 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_disable()
100 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_RST_MODE_INTR_Pos); in mec_hal_wdt_intr_ctrl()
104 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_WDT_CTRL_RST_MODE_INTR_Pos); in mec_hal_wdt_intr_ctrl()
131 regs->CTRL &= (uint32_t)~(MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos) in mec_hal_wdt_intr_helper()
142 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_intr_helper()
161 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_STALL_JTAG_Pos); in mec_hal_wdt_debug_stall()
[all …]
Dmec_adc.c53 regs->CTRL = 0; in mec_hal_adc_init()
59 regs->CTRL = MEC_BIT(MEC_ADC_CTRL_SRST_Pos); in mec_hal_adc_init()
61 if (!(regs->CTRL & MEC_BIT(MEC_ADC_CTRL_SRST_Pos))) { in mec_hal_adc_init()
65 regs->CTRL = 0; in mec_hal_adc_init()
69 regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos); in mec_hal_adc_init()
71 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos); in mec_hal_adc_init()
105 regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_ACTV_Pos); in mec_hal_adc_init()
119 ctrl = regs->CTRL & ~msk; in mec_hal_adc_activate()
126 regs->CTRL = ctrl; in mec_hal_adc_activate()
299 regs->CTRL |= ctrl_val; in mec_hal_adc_status_clear()
[all …]
Dmec_btimer_api.h106 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos); in mec_hal_btimer_enable()
111 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos); in mec_hal_btimer_disable()
116 regs->CTRL |= (MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos) | MEC_BIT(MEC_BTMR_CTRL_START_Pos)); in mec_hal_btimer_start()
121 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_BTMR_CTRL_START_Pos); in mec_hal_btimer_stop()
126 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_HALT_Pos); in mec_hal_btimer_halt()
131 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_BTMR_CTRL_HALT_Pos); in mec_hal_btimer_unhalt()
136 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_RELOAD_Pos); in mec_hal_btimer_reload()
Dmec_tach.c65 regs->CTRL = 0u; in mec_hal_tach_init()
114 regs->CTRL = ctrl; in mec_hal_tach_init()
122 regs->CTRL |= MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos); in mec_hal_tach_enable()
124 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos); in mec_hal_tach_enable()
134 return (regs->CTRL & MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos)) ? true : false; in mec_hal_tach_is_enabled()
150 return (regs->CTRL & MEC_TACH_CTRL_COUNT_Msk) >> MEC_TACH_CTRL_COUNT_Pos; in mec_hal_tach_counter()
185 regs->CTRL |= msk; in mec_hal_tach_intr_enable()
187 regs->CTRL &= (uint32_t)~msk; in mec_hal_tach_intr_enable()
Dmec_dmac.c266 regs->CTRL = 0; in mec_hal_dma_chan_init()
350 ctrl = regs->CTRL; in mec_hal_dma_chan_start()
370 regs->CTRL = ctrl | MEC_BIT(start_pos); in mec_hal_dma_chan_start()
384 if (base->CHAN[chan].CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) { in mec_hal_dma_chan_is_busy()
403 regs->CTRL &= ~halt; in mec_hal_dma_chan_halt()
421 if (regs->CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) { in mec_hal_dma_chan_stop()
422 regs->CTRL |= MEC_BIT(MEC_DMA_CHAN_CTRL_ABORT_Pos); in mec_hal_dma_chan_stop()
424 while (regs->CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) { in mec_hal_dma_chan_stop()
433 regs->CTRL &= (uint32_t)~(MEC_BIT(MEC_DMA_CHAN_CTRL_HFC_RUN_Pos) in mec_hal_dma_chan_stop()
452 ctrl = regs->CTRL & (uint32_t)~(MEC_DMA_CHAN_CTRL_HFC_DEV_Msk); in mec_hal_dma_chan_hwfc_set()
[all …]
Dmec_rtimer.c32 regs->CTRL = 0; in mec_hal_rtimer_init()
58 regs->CTRL = ctrl; in mec_hal_rtimer_init()
110 uint32_t ctrl = regs->CTRL; in mec_hal_rtimer_restart()
112 regs->CTRL = 0; in mec_hal_rtimer_restart()
120 regs->CTRL = ctrl; in mec_hal_rtimer_restart()
Dmec_gpio.c315 if (MEC_GPIO->CTRL[pin] & (MEC_GPIO_CTRL_DIR_OUTPUT << MEC_GPIO_CTRL_DIR_Pos)) { in mec_hal_gpio_is_output()
330 MEC_GPIO->CTRL[pin] |= MEC_BIT(MEC_GPIO_CTRL_INPD_Pos); in mec_hal_gpio_disable_input_pad()
343 MEC_GPIO->CTRL[pin] &= ~MEC_BIT(MEC_GPIO_CTRL_INPD_Pos); in mec_hal_gpio_enable_input_pad()
378 *config = MEC_GPIO->CTRL[pin] & 0xffffu; in mec_hal_gpio_get_config()
391 MEC_MMCR16_WR(&MEC_GPIO->CTRL[pin], cfg & 0xffffu); in mec_hal_gpio_set_config()
404 uint16_t pin_cfg = MEC_MMCR16_RD(&MEC_GPIO->CTRL[pin]) & (uint16_t)~mask; in mec_hal_gpio_set_config_mask()
407 MEC_MMCR16_WR(&MEC_GPIO->CTRL[pin], pin_cfg); in mec_hal_gpio_set_config_mask()
452 uintptr_t regaddr = (uintptr_t)&MEC_GPIO->CTRL[pin]; in mec_hal_gpio_get_property()
479 uintptr_t regaddr = (uintptr_t)&MEC_GPIO->CTRL[pin]; in mec_hal_gpio_set_property()
515 uint32_t ctrl = MEC_GPIO->CTRL[pin]; in mec_hal_gpio_set_props()
[all …]
Dmec_ps2.c94 if (regs->CTRL & MEC_BIT(MEC_PS2_CTRL_ENABLE_Pos)) { in ps2_is_enabled()
117 regs->CTRL = 0u; in mec_hal_ps2_init()
134 regs->CTRL = ctrl; in mec_hal_ps2_init()
151 regs->CTRL = (regs->CTRL & (uint8_t)~(opmask & 0x03u)) | (operand & 0x03u); in mec_hal_ps2_control()
262 regs->CTRL |= MEC_BIT(MEC_PS2_CTRL_TREN_Pos); in mec_hal_ps2_direction()
264 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PS2_CTRL_TREN_Pos); in mec_hal_ps2_direction()
Dmec_qspi.c161 uint32_t iom = (base->CTRL & MEC_QSPI_CTRL_IFM_Msk) >> MEC_QSPI_CTRL_IFM_Pos; in qspi_byte_time_ns()
453 base->CTRL = (base->CTRL & (uint32_t)~MEC_QSPI_CTRL_IFM_Msk) | qspi_ifm(io); in qspi_io()
822 base->RX_LDMA_CHAN[0].CTRL = 0; in qspi_ldma_init()
823 base->RX_LDMA_CHAN[1].CTRL = 0; in qspi_ldma_init()
824 base->RX_LDMA_CHAN[2].CTRL = 0; in qspi_ldma_init()
825 base->TX_LDMA_CHAN[0].CTRL = 0; in qspi_ldma_init()
826 base->TX_LDMA_CHAN[1].CTRL = 0; in qspi_ldma_init()
827 base->TX_LDMA_CHAN[2].CTRL = 0; in qspi_ldma_init()
861 base->RX_LDMA_CHAN[0].CTRL = rctrl; in qspi_ldma_cfg1()
866 base->TX_LDMA_CHAN[0].CTRL = wctrl | MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_INCRA_Pos); in qspi_ldma_cfg1()
[all …]
Dmec_htimer.c53 regs->CTRL = 0; in mec_hal_htimer_init()
58 regs->CTRL |= MEC_BIT(MEC_HTMR_CTRL_RES_Pos); in mec_hal_htimer_init()
Dmec_wktimer.c93 regs->CTRL = 0; /* disable */ in mec_hal_wktimer_init()
117 regs->CTRL = ctrl; in mec_hal_wktimer_init()
Dmec_i2c.c176 base->CTRL = control; in i2c_config()
198 base->CTRL = control; in i2c_config()
435 base->CTRL = ctrl; in mec_hal_i2c_smb_ctrl_set()
466 base->CTRL = ctrl; in mec_hal_i2c_cmd_ack_ctrl()
495 base->CTRL = ctr; in mec_hal_i2c_smb_auto_ack_enable()
514 base->CTRL = ctr; in mec_hal_i2c_smb_auto_ack_disable()
555 regs->CTRL = ctx->i2c_ctrl_cached; in mec_hal_i2c_smb_intr_ctrl()
727 base->CTRL = ctr; in mec_hal_i2c_smb_start_gen()
730 base->CTRL = ctr; in mec_hal_i2c_smb_start_gen()
754 base->CTRL = control; in mec_hal_i2c_smb_stop_gen()
/hal_microchip-latest/mpfs/drivers/mss/mss_i2c/
Dmss_i2c.c131 this_i2c->hw_reg->CTRL |= (uint8_t)((((clock_speed >> 2u) & 0x01u) << CR2) in MSS_I2C_init()
134 this_i2c->hw_reg->CTRL |= (uint8_t)((((clock_speed >> 1u) & 0x01u) << CR1) in MSS_I2C_init()
137 this_i2c->hw_reg->CTRL |= (uint8_t)(((clock_speed & (uint8_t)0x01u) << CR0) in MSS_I2C_init()
142 this_i2c->hw_reg->CTRL |= ENS1_MASK; /* Set enable bit */ in MSS_I2C_init()
201 this_i2c->hw_reg->CTRL |= STA_MASK; in MSS_I2C_write()
211 this_i2c->hw_reg->CTRL &= ~SI_MASK; in MSS_I2C_write()
274 this_i2c->hw_reg->CTRL |= STA_MASK; in MSS_I2C_read()
284 this_i2c->hw_reg->CTRL &= ~SI_MASK; in MSS_I2C_read()
360 this_i2c->hw_reg->CTRL |= STA_MASK; in MSS_I2C_write_read()
370 this_i2c->hw_reg->CTRL &= ~SI_MASK; in MSS_I2C_write_read()
[all …]
/hal_microchip-latest/mec/mec1501/component/
Dtimer.h173 __IOM uint32_t CTRL; /*!< (@ 0x00000010) BTMR Control */ member
236 __IOM uint16_t CTRL; /*!< (@ 0x00000004) HTMR Control */ member
315 __IOM uint32_t CTRL; /*!< (@ 0x00000000) CCT Control */ member
379 __IOM uint8_t CTRL; /*!< (@ 0x00000008) RTMR Control */ member
477 __IOM uint32_t CTRL; /*! (@ 0x00000000) WKTMR control */ member
Dtfdp.h85 __IOM uint32_t CTRL; /*!< (@ 0x0004) Control register */ member
/hal_microchip-latest/mec5/devices/common/
Dmec5_htmr_v1.h19 …__IOM uint32_t CTRL; /*!< (@ 0x00000004) Hibernation timer control … member
Dmec5_rtmr_v1.h20 …__IOM uint32_t CTRL; /*!< (@ 0x00000008) RTOS timer control … member
Dmec5_rcid_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) RC ID control … member
Dmec5_tfdp_v1.h20 …__IOM uint8_t CTRL; /*!< (@ 0x00000004) TFDP control … member
Dmec5_wdt_v2.h19 …__IOM uint32_t CTRL; /*!< (@ 0x00000004) WDT Control … member
Dmec5_tach_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) Tachometer control … member
/hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/
Dccl_component_fixup_pic32cxsg.h61 __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ member

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