Lines Matching refs:CTRL
31 regs->CTRL = (MEC_BIT(MEC_PECI_CTRL_RST_Pos) | MEC_BIT(MEC_PECI_CTRL_FRST_Pos) in peci_reset()
37 regs->CTRL = MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in peci_reset()
103 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_MIEN_Pos); in mec_hal_peci_init()
107 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_init()
122 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_enable()
124 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_enable()
139 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_RST_Pos); in mec_hal_peci_ctrl_reset()
141 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_RST_Pos); in mec_hal_peci_ctrl_reset()
156 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_FRST_Pos); in mec_hal_peci_fifo_reset()
158 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_FRST_Pos); in mec_hal_peci_fifo_reset()
176 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_MIEN_Pos); in mec_hal_peci_global_ien()
178 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_MIEN_Pos); in mec_hal_peci_global_ien()
218 uint8_t ctrl = regs->CTRL; in mec_hal_peci_set_opt_bit_time()
220 regs->CTRL = ctrl | MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_set_opt_bit_time()
223 regs->CTRL = ctrl; in mec_hal_peci_set_opt_bit_time()
240 regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_TXEN_Pos); in mec_hal_peci_tx_enable()
242 regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_TXEN_Pos); in mec_hal_peci_tx_enable()
347 peci_pm_save_buf[0] = MEC_PECI0->CTRL; in mec_hal_peci_pm_save_disable()
348 MEC_PECI0->CTRL |= MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in mec_hal_peci_pm_save_disable()
363 MEC_PECI0->CTRL = peci_pm_save_buf[0]; in mec_hal_peci_pm_save_restore()