Searched refs:CMD (Results 1 – 12 of 12) sorted by relevance
54 while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/ in MSS_AXISW_write_qos_val()58 AXISW->CMD = (AXISW_CMD_RW_MASK | in MSS_AXISW_write_qos_val()63 while(AXISW->CMD & AXISW_CMD_EN_MASK); /*Wait for command to complete*/ in MSS_AXISW_write_qos_val()65 return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/ in MSS_AXISW_write_qos_val()84 while(AXISW->CMD & AXISW_CMD_EN_MASK); in MSS_AXISW_read_qos_val()86 AXISW->CMD &= ~(AXISW_CMD_RW_MASK); /*Clear read/write bit*/ in MSS_AXISW_read_qos_val()88 AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) | (MSS_AXISW_QOS_VAL) | AXISW_CMD_EN_MASK); in MSS_AXISW_read_qos_val()90 while(AXISW->CMD & AXISW_CMD_EN_MASK); in MSS_AXISW_read_qos_val()94 return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/ in MSS_AXISW_read_qos_val()110 while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/ in MSS_AXISW_write_rate()[all …]
147 __IO uint32_t CMD; member
55 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ member68 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ member
53 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ member67 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ member
33 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ member
51 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ member65 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ member
96 uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ member
195 uint32_t CMD:2; /*!< bit: 16..17 Command */ member213 uint32_t CMD:2; /*!< bit: 16..17 Command */ member
20 …__IOM uint32_t CMD; /*!< (@ 0x0000000C) Command register … member
1292 regs->CMD = cmd; in _i3c_command_write()
7908 …__I uint8_t CMD : 1; /*!< [3..3] This bit is set when the OS2EC Data EC Byt… member7978 …__I uint8_t CMD : 1; /*!< [3..3] This bit is set when the OS2EC Data EC B… member
