54     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_qos_val()
58     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_qos_val()
63     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_qos_val()
65     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_qos_val()
84     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
86     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write bit*/  in MSS_AXISW_read_qos_val()
88     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) | (MSS_AXISW_QOS_VAL) | AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
90     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
94     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_qos_val()
110     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_rate()
113     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_rate()
118     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_rate()
120     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_rate()
135     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_rate()
137     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write and command EN bit*/  in MSS_AXISW_read_rate()
139     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_rate()
143     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_rate()
150     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_rate()
167     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_burstiness()
182     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_burstiness()
187     while(AXISW->CMD & AXISW_CMD_EN_MASK);      /*Wait for command to complete*/  in MSS_AXISW_write_burstiness()
189     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_burstiness()
202     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_burstiness()
204     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write and command EN bit*/  in MSS_AXISW_read_burstiness()
206     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_burstiness()
210     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_burstiness()
214     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_burstiness()
220     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_slave_ready()
224     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_slave_ready()
229     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_slave_ready()
231     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_slave_ready()
247     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_slave_ready()
249     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write bit*/  in MSS_AXISW_read_slave_ready()
251     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_slave_ready()
255     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_slave_ready()
259     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_slave_ready()