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Searched refs:TIMER_CTL1 (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_timer.c605 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
607 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
784 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
786 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
803 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
805 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
872 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
874 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
876 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
878 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_timer.c469 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
471 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
648 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
650 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
667 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
669 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
736 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
738 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
740 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
742 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_timer.c601 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
603 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
780 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
782 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
799 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
801 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
868 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
870 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
872 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
874 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_timer.c442 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
444 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
620 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
622 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
639 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
641 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
707 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
709 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
711 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
713 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_timer.c474 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
476 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
653 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
655 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
672 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
674 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
741 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
743 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
745 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
747 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_timer.c475 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
477 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
653 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
655 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
672 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
674 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
740 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
742 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
744 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
746 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_timer.c395 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; in timer_channel_control_shadow_config()
397 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); in timer_channel_control_shadow_config()
414 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); in timer_channel_control_shadow_update_config()
416 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; in timer_channel_control_shadow_update_config()
483 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
485 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
738 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); in timer_channel_output_config()
740 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; in timer_channel_output_config()
743 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); in timer_channel_output_config()
745 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; in timer_channel_output_config()
[all …]
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_timer.c403 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
405 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; in timer_channel_dma_request_source_select()
1297 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1299 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1350 ctl = TIMER_CTL1(timer_periph); in timer_master_output_trigger_source_select()
1353 TIMER_CTL1(timer_periph) = ctl; in timer_master_output_trigger_source_select()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_timer.h50 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_timer.h61 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_timer.h52 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_timer.h60 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_timer.h58 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_timer.h56 #define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control r… macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_timer.h61 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_timer.h51 #define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER cont… macro