1 /*!
2 \file gd32vf103_timer.c
3 \brief TIMER driver
4
5 \version 2019-06-05, V1.0.1, firmware for GD32VF103
6 \version 2020-08-04, V1.1.0, firmware for GD32VF103
7 */
8
9 /*
10 Copyright (c) 2020, GigaDevice Semiconductor Inc.
11
12 Redistribution and use in source and binary forms, with or without modification,
13 are permitted provided that the following conditions are met:
14
15 1. Redistributions of source code must retain the above copyright notice, this
16 list of conditions and the following disclaimer.
17 2. Redistributions in binary form must reproduce the above copyright notice,
18 this list of conditions and the following disclaimer in the documentation
19 and/or other materials provided with the distribution.
20 3. Neither the name of the copyright holder nor the names of its contributors
21 may be used to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 OF SUCH DAMAGE.
34 */
35 #include "gd32vf103_timer.h"
36
37 /* TIMER init parameter mask */
38 #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */
39 #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */
40 #define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */
41
42 /*!
43 \brief deinit a timer
44 \param[in] timer_periph: TIMERx(x=0..6)
45 \param[out] none
46 \retval none
47 */
timer_deinit(uint32_t timer_periph)48 void timer_deinit(uint32_t timer_periph)
49 {
50 switch(timer_periph){
51 case TIMER0:
52 /* reset TIMER0 */
53 rcu_periph_reset_enable(RCU_TIMER0RST);
54 rcu_periph_reset_disable(RCU_TIMER0RST);
55 break;
56 case TIMER1:
57 /* reset TIMER1 */
58 rcu_periph_reset_enable(RCU_TIMER1RST);
59 rcu_periph_reset_disable(RCU_TIMER1RST);
60 break;
61 case TIMER2:
62 /* reset TIMER2 */
63 rcu_periph_reset_enable(RCU_TIMER2RST);
64 rcu_periph_reset_disable(RCU_TIMER2RST);
65 break;
66 case TIMER3:
67 /* reset TIMER3 */
68 rcu_periph_reset_enable(RCU_TIMER3RST);
69 rcu_periph_reset_disable(RCU_TIMER3RST);
70 break;
71 case TIMER4:
72 /* reset TIMER4 */
73 rcu_periph_reset_enable(RCU_TIMER4RST);
74 rcu_periph_reset_disable(RCU_TIMER4RST);
75 break;
76 case TIMER5:
77 /* reset TIMER5 */
78 rcu_periph_reset_enable(RCU_TIMER5RST);
79 rcu_periph_reset_disable(RCU_TIMER5RST);
80 break;
81 case TIMER6:
82 /* reset TIMER6 */
83 rcu_periph_reset_enable(RCU_TIMER6RST);
84 rcu_periph_reset_disable(RCU_TIMER6RST);
85 break;
86
87 default:
88 break;
89 }
90 }
91
92 /*!
93 \brief initialize TIMER init parameter struct with a default value
94 \param[in] initpara: init parameter struct
95 \param[out] none
96 \retval none
97 */
timer_struct_para_init(timer_parameter_struct * initpara)98 void timer_struct_para_init(timer_parameter_struct* initpara)
99 {
100 /* initialize the init parameter struct member with the default value */
101 initpara->prescaler = 0U;
102 initpara->alignedmode = TIMER_COUNTER_EDGE;
103 initpara->counterdirection = TIMER_COUNTER_UP;
104 initpara->period = 65535U;
105 initpara->clockdivision = TIMER_CKDIV_DIV1;
106 initpara->repetitioncounter = 0U;
107 }
108
109 /*!
110 \brief initialize TIMER counter
111 \param[in] timer_periph: TIMERx(x=0..6)
112 \param[in] initpara: init parameter struct
113 prescaler: prescaler value of the counter clock, 0~65535
114 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP,
115 TIMER_COUNTER_CENTER_BOTH
116 counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
117 period: counter auto reload value, 0~65535
118 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
119 repetitioncounter: counter repetition value, 0~255
120 \param[out] none
121 \retval none
122 */
gd32_timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)123 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
124 {
125 /* configure the counter prescaler value */
126 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
127
128 /* configure the counter direction and aligned mode */
129 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
130 || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){
131 TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
132 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
133 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
134 }else{
135 TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
136 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
137 }
138
139 /* configure the autoreload value */
140 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
141
142 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
143 /* reset the CKDIV bit */
144 TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
145 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
146 }
147
148 if (TIMER0 == timer_periph) {
149 /* configure the repetition counter value */
150 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
151 }
152
153 /* generate an update event */
154 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
155 }
156
157 /*!
158 \brief enable a timer
159 \param[in] timer_periph: TIMERx(x=0..6)
160 \param[out] none
161 \retval none
162 */
timer_enable(uint32_t timer_periph)163 void timer_enable(uint32_t timer_periph)
164 {
165 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
166 }
167
168 /*!
169 \brief disable a timer
170 \param[in] timer_periph: TIMERx(x=0..6)
171 \param[out] none
172 \retval none
173 */
timer_disable(uint32_t timer_periph)174 void timer_disable(uint32_t timer_periph)
175 {
176 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
177 }
178
179 /*!
180 \brief enable the auto reload shadow function
181 \param[in] timer_periph: TIMERx(x=0..6)
182 \param[out] none
183 \retval none
184 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)185 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
186 {
187 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
188 }
189
190 /*!
191 \brief disable the auto reload shadow function
192 \param[in] timer_periph: TIMERx(x=0..6)
193 \param[out] none
194 \retval none
195 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)196 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
197 {
198 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
199 }
200
201 /*!
202 \brief enable the update event
203 \param[in] timer_periph: TIMERx(x=0..6)
204 \param[out] none
205 \retval none
206 */
timer_update_event_enable(uint32_t timer_periph)207 void timer_update_event_enable(uint32_t timer_periph)
208 {
209 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
210 }
211
212 /*!
213 \brief disable the update event
214 \param[in] timer_periph: TIMERx(x=0..6)
215 \param[out] none
216 \retval none
217 */
timer_update_event_disable(uint32_t timer_periph)218 void timer_update_event_disable(uint32_t timer_periph)
219 {
220 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
221 }
222
223 /*!
224 \brief set TIMER counter alignment mode
225 \param[in] timer_periph: TIMERx(x=0..4)
226 \param[in] aligned:
227 only one parameter can be selected which is shown as below:
228 \arg TIMER_COUNTER_EDGE: edge-aligned mode
229 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
230 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
231 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
232 \param[out] none
233 \retval none
234 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)235 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
236 {
237 TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
238 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
239 }
240
241 /*!
242 \brief set TIMER counter up direction
243 \param[in] timer_periph: TIMERx(x=0..4)
244 \param[out] none
245 \retval none
246 */
timer_counter_up_direction(uint32_t timer_periph)247 void timer_counter_up_direction(uint32_t timer_periph)
248 {
249 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
250 }
251
252 /*!
253 \brief set TIMER counter down direction
254 \param[in] timer_periph: TIMERx(x=0..4)
255 \param[out] none
256 \retval none
257 */
timer_counter_down_direction(uint32_t timer_periph)258 void timer_counter_down_direction(uint32_t timer_periph)
259 {
260 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
261 }
262
263 /*!
264 \brief configure TIMER prescaler
265 \param[in] timer_periph: TIMERx(x=0..6)
266 \param[in] prescaler: prescaler value
267 \param[in] pscreload: prescaler reload mode
268 only one parameter can be selected which is shown as below:
269 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
270 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
271 \param[out] none
272 \retval none
273 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint32_t pscreload)274 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
275 {
276 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
277
278 if(TIMER_PSC_RELOAD_NOW == pscreload){
279 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
280 }
281 }
282
283 /*!
284 \brief configure TIMER repetition register value
285 \param[in] timer_periph: TIMERx(x=0)
286 \param[in] repetition: the counter repetition value, 0~255
287 \param[out] none
288 \retval none
289 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)290 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
291 {
292 TIMER_CREP(timer_periph) = (uint32_t)repetition;
293 }
294
295 /*!
296 \brief configure TIMER autoreload register value
297 \param[in] timer_periph: TIMERx(x=0..6)
298 \param[in] autoreload: the counter auto-reload value
299 \param[out] none
300 \retval none
301 */
timer_autoreload_value_config(uint32_t timer_periph,uint16_t autoreload)302 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
303 {
304 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
305 }
306
307 /*!
308 \brief configure TIMER counter register value
309 \param[in] timer_periph: TIMERx(x=0..6)
310 \param[in] counter: the counter value
311 \param[out] none
312 \retval none
313 */
timer_counter_value_config(uint32_t timer_periph,uint16_t counter)314 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
315 {
316 TIMER_CNT(timer_periph) = (uint32_t)counter;
317 }
318
319 /*!
320 \brief read TIMER counter value
321 \param[in] timer_periph: TIMERx(x=0..6)
322 \param[out] none
323 \retval counter value
324 */
timer_counter_read(uint32_t timer_periph)325 uint32_t timer_counter_read(uint32_t timer_periph)
326 {
327 uint32_t count_value = 0U;
328 count_value = TIMER_CNT(timer_periph);
329 return (count_value);
330 }
331
332 /*!
333 \brief read TIMER prescaler value
334 \param[in] timer_periph: TIMERx(x=0..6)
335 \param[out] none
336 \retval prescaler register value
337 */
timer_prescaler_read(uint32_t timer_periph)338 uint16_t timer_prescaler_read(uint32_t timer_periph)
339 {
340 uint16_t prescaler_value = 0U;
341 prescaler_value = (uint16_t) (TIMER_PSC(timer_periph));
342 return (prescaler_value);
343 }
344
345 /*!
346 \brief configure TIMER single pulse mode
347 \param[in] timer_periph: TIMERx(x=0..6)
348 \param[in] spmode:
349 only one parameter can be selected which is shown as below:
350 \arg TIMER_SP_MODE_SINGLE: single pulse mode
351 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
352 \param[out] none
353 \retval none
354 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)355 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
356 {
357 if(TIMER_SP_MODE_SINGLE == spmode){
358 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
359 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
360 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
361 }else{
362 /* illegal parameters */
363 }
364 }
365
366 /*!
367 \brief configure TIMER update source
368 \param[in] timer_periph: TIMERx(x=0..6)
369 \param[in] update:
370 only one parameter can be selected which is shown as below:
371 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,
372 or the slave mode controller trigger
373 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
374 \param[out] none
375 \retval none
376 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)377 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
378 {
379 if(TIMER_UPDATE_SRC_REGULAR == update){
380 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
381 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
382 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
383 }else{
384 /* illegal parameters */
385 }
386 }
387
388
389 /*!
390 \brief enable the TIMER DMA
391 \param[in] timer_periph: TIMERx(x=0..6)
392 \param[in] dma: specify which DMA to enable
393 one or more parameters can be selected which are shown as below:
394 \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6)
395 \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
396 \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
397 \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
398 \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
399 \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
400 \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4)
401 \param[out] none
402 \retval none
403 */
timer_dma_enable(uint32_t timer_periph,uint16_t dma)404 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
405 {
406 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
407 }
408
409 /*!
410 \brief disable the TIMER DMA
411 \param[in] timer_periph: TIMERxTIMERx(x=0..6)
412 \param[in] dma: specify which DMA to disbale
413 one or more parameters can be selected which are shown as below:
414 \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6)
415 \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
416 \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
417 \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
418 \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
419 \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
420 \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7)
421 \param[out] none
422 \retval none
423 */
timer_dma_disable(uint32_t timer_periph,uint16_t dma)424 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
425 {
426 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
427 }
428
429 /*!
430 \brief channel DMA request source selection
431 \param[in] timer_periph: TIMERx(x=0..4)
432 \param[in] dma_request: channel DMA request source selection
433 only one parameter can be selected which is shown as below:
434 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs
435 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs
436 \param[out] none
437 \retval none
438 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint32_t dma_request)439 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
440 {
441 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
442 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
443 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
444 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
445 }else{
446 /* illegal parameters */
447 }
448 }
449
450 /*!
451 \brief configure the TIMER DMA transfer
452 \param[in] timer_periph: TIMERx(x=0..4)
453 \param[in] dma_baseaddr:
454 only one parameter can be selected which is shown as below:
455 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4)
456 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4)
457 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4)
458 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4)
459 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4)
460 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4)
461 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4)
462 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4)
463 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4)
464 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4)
465 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4)
466 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4)
467 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0)
468 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4)
469 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4)
470 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4)
471 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4)
472 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0)
473 \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4)
474 \param[in] dma_lenth:
475 only one parameter can be selected which is shown as below:
476 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time
477 \param[out] none
478 \retval none
479 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth)480 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
481 {
482 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
483 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
484 }
485
486 /*!
487 \brief software generate events
488 \param[in] timer_periph: TIMERx(x=0..4)
489 \param[in] event: the timer software event generation sources
490 one or more parameters can be selected which are shown as below:
491 \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6)
492 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4)
493 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4)
494 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4)
495 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4)
496 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0)
497 \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4)
498 \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0)
499 \param[out] none
500 \retval none
501 */
timer_event_software_generate(uint32_t timer_periph,uint16_t event)502 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
503 {
504 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
505 }
506
507 /*!
508 \brief initialize TIMER break parameter struct with a default value
509 \param[in] breakpara: TIMER break parameter struct
510 \param[out] none
511 \retval none
512 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)513 void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
514 {
515 /* initialize the break parameter struct member with the default value */
516 breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
517 breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
518 breakpara->deadtime = 0U;
519 breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
520 breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
521 breakpara->protectmode = TIMER_CCHP_PROT_OFF;
522 breakpara->breakstate = TIMER_BREAK_DISABLE;
523 }
524
525 /*!
526 \brief configure TIMER break function
527 \param[in] timer_periph: TIMERx(x=0)
528 \param[in] breakpara: TIMER break parameter struct
529 runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE
530 ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE
531 deadtime: 0~255
532 breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH
533 outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE
534 protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2
535 breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE
536 \param[out] none
537 \retval none
538 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)539 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
540 {
541 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
542 ((uint32_t)(breakpara->ideloffstate))|
543 ((uint32_t)(breakpara->deadtime)) |
544 ((uint32_t)(breakpara->breakpolarity)) |
545 ((uint32_t)(breakpara->outputautostate)) |
546 ((uint32_t)(breakpara->protectmode)) |
547 ((uint32_t)(breakpara->breakstate)));
548 }
549
550 /*!
551 \brief enable TIMER break function
552 \param[in] timer_periph: TIMERx(x=0)
553 \param[out] none
554 \retval none
555 */
timer_break_enable(uint32_t timer_periph)556 void timer_break_enable(uint32_t timer_periph)
557 {
558 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
559 }
560
561 /*!
562 \brief disable TIMER break function
563 \param[in] timer_periph: TIMERx(x=0)
564 \param[out] none
565 \retval none
566 */
timer_break_disable(uint32_t timer_periph)567 void timer_break_disable(uint32_t timer_periph)
568 {
569 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
570 }
571
572 /*!
573 \brief enable TIMER output automatic function
574 \param[in] timer_periph: TIMERx(x=0)
575 \param[out] none
576 \retval none
577 */
timer_automatic_output_enable(uint32_t timer_periph)578 void timer_automatic_output_enable(uint32_t timer_periph)
579 {
580 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
581 }
582
583 /*!
584 \brief disable TIMER output automatic function
585 \param[in] timer_periph: TIMERx(x=0)
586 \param[out] none
587 \retval none
588 */
timer_automatic_output_disable(uint32_t timer_periph)589 void timer_automatic_output_disable(uint32_t timer_periph)
590 {
591 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
592 }
593
594 /*!
595 \brief enable or disable TIMER primary output function
596 \param[in] timer_periph: TIMERx(x=0)
597 \param[in] newvalue: ENABLE or DISABLE
598 \param[out] none
599 \retval none
600 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)601 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
602 {
603 if(ENABLE == newvalue){
604 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
605 }else{
606 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
607 }
608 }
609
610 /*!
611 \brief enable or disable channel capture/compare control shadow register
612 \param[in] timer_periph: TIMERx(x=0)
613 \param[in] newvalue: ENABLE or DISABLE
614 \param[out] none
615 \retval none
616 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)617 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
618 {
619 if(ENABLE == newvalue){
620 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
621 }else{
622 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
623 }
624 }
625
626 /*!
627 \brief configure TIMER channel control shadow register update control
628 \param[in] timer_periph: TIMERx(x=0)
629 \param[in] ccuctl: channel control shadow register update control
630 only one parameter can be selected which is shown as below:
631 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
632 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
633 \param[out] none
634 \retval none
635 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint32_t ccuctl)636 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
637 {
638 if(TIMER_UPDATECTL_CCU == ccuctl){
639 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
640 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
641 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
642 }else{
643 /* illegal parameters */
644 }
645 }
646
647 /*!
648 \brief initialize TIMER channel output parameter struct with a default value
649 \param[in] ocpara: TIMER channel n output parameter struct
650 \param[out] none
651 \retval none
652 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)653 void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
654 {
655 /* initialize the channel output parameter struct member with the default value */
656 ocpara->outputstate = TIMER_CCX_DISABLE;
657 ocpara->outputnstate = TIMER_CCXN_DISABLE;
658 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
659 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
660 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
661 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
662 }
663
664 /*!
665 \brief configure TIMER channel output function
666 \param[in] timer_periph: TIMERx(x=0..4)
667 \param[in] channel:
668 only one parameter can be selected which is shown as below:
669 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
670 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
671 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
672 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
673 \param[in] ocpara: TIMER channeln output parameter struct
674 outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE
675 outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE
676 ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW
677 ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW
678 ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH
679 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH
680 \param[out] none
681 \retval none
682 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)683 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
684 {
685 switch(channel){
686 /* configure TIMER_CH_0 */
687 case TIMER_CH_0:
688 /* reset the CH0EN bit */
689 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
690 /* set the CH0EN bit */
691 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
692 /* reset the CH0P bit */
693 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
694 /* set the CH0P bit */
695 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
696
697 if (TIMER0 == timer_periph) {
698 /* reset the CH0NEN bit */
699 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
700 /* set the CH0NEN bit */
701 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
702 /* reset the CH0NP bit */
703 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
704 /* set the CH0NP bit */
705 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
706 /* reset the ISO0 bit */
707 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
708 /* set the ISO0 bit */
709 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
710 /* reset the ISO0N bit */
711 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
712 /* set the ISO0N bit */
713 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
714 }
715 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
716 break;
717 /* configure TIMER_CH_1 */
718 case TIMER_CH_1:
719 /* reset the CH1EN bit */
720 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
721 /* set the CH1EN bit */
722 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
723 /* reset the CH1P bit */
724 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
725 /* set the CH1P bit */
726 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
727
728 if (TIMER0 == timer_periph) {
729 /* reset the CH1NEN bit */
730 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
731 /* set the CH1NEN bit */
732 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
733 /* reset the CH1NP bit */
734 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
735 /* set the CH1NP bit */
736 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
737 /* reset the ISO1 bit */
738 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
739 /* set the ISO1 bit */
740 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
741 /* reset the ISO1N bit */
742 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
743 /* set the ISO1N bit */
744 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
745 }
746 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
747 break;
748 /* configure TIMER_CH_2 */
749 case TIMER_CH_2:
750 /* reset the CH2EN bit */
751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
752 /* set the CH2EN bit */
753 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
754 /* reset the CH2P bit */
755 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
756 /* set the CH2P bit */
757 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
758
759 if (TIMER0 == timer_periph) {
760 /* reset the CH2NEN bit */
761 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
762 /* set the CH2NEN bit */
763 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
764 /* reset the CH2NP bit */
765 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
766 /* set the CH2NP bit */
767 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
768 /* reset the ISO2 bit */
769 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
770 /* set the ISO2 bit */
771 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
772 /* reset the ISO2N bit */
773 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
774 /* set the ISO2N bit */
775 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
776 }
777 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
778 break;
779 /* configure TIMER_CH_3 */
780 case TIMER_CH_3:
781 /* reset the CH3EN bit */
782 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
783 /* set the CH3EN bit */
784 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
785 /* reset the CH3P bit */
786 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
787 /* set the CH3P bit */
788 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
789
790 if (TIMER0 == timer_periph) {
791 /* reset the ISO3 bit */
792 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
793 /* set the ISO3 bit */
794 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
795 }
796 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
797 break;
798 default:
799 break;
800 }
801 }
802
803 /*!
804 \brief configure TIMER channel output compare mode
805 \param[in] timer_periph: TIMERx(x=0..4)
806 \param[in] channel:
807 only one parameter can be selected which is shown as below:
808 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
809 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
810 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
811 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
812 \param[in] ocmode: channel output compare mode
813 only one parameter can be selected which is shown as below:
814 \arg TIMER_OC_MODE_TIMING: timing mode
815 \arg TIMER_OC_MODE_ACTIVE: active mode
816 \arg TIMER_OC_MODE_INACTIVE: inactive mode
817 \arg TIMER_OC_MODE_TOGGLE: toggle mode
818 \arg TIMER_OC_MODE_LOW: force low mode
819 \arg TIMER_OC_MODE_HIGH: force high mode
820 \arg TIMER_OC_MODE_PWM0: PWM mode 0
821 \arg TIMER_OC_MODE_PWM1: PWM mode 1
822 \param[out] none
823 \retval none
824 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)825 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
826 {
827 switch(channel){
828 /* configure TIMER_CH_0 */
829 case TIMER_CH_0:
830 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
831 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
832 break;
833 /* configure TIMER_CH_1 */
834 case TIMER_CH_1:
835 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
836 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
837 break;
838 /* configure TIMER_CH_2 */
839 case TIMER_CH_2:
840 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
841 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
842 break;
843 /* configure TIMER_CH_3 */
844 case TIMER_CH_3:
845 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
846 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
847 break;
848 default:
849 break;
850 }
851 }
852
853 /*!
854 \brief configure TIMER channel output pulse value
855 \param[in] timer_periph: TIMERx(x=0..4)
856 \param[in] channel:
857 only one parameter can be selected which is shown as below:
858 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
859 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
860 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
861 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
862 \param[in] pulse: channel output pulse value
863 \param[out] none
864 \retval none
865 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)866 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
867 {
868 switch(channel){
869 /* configure TIMER_CH_0 */
870 case TIMER_CH_0:
871 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
872 break;
873 /* configure TIMER_CH_1 */
874 case TIMER_CH_1:
875 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
876 break;
877 /* configure TIMER_CH_2 */
878 case TIMER_CH_2:
879 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
880 break;
881 /* configure TIMER_CH_3 */
882 case TIMER_CH_3:
883 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
884 break;
885 default:
886 break;
887 }
888 }
889
890 /*!
891 \brief configure TIMER channel output shadow function
892 \param[in] timer_periph: TIMERx(x=0..4)
893 \param[in] channel:
894 only one parameter can be selected which is shown as below:
895 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
896 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
897 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
898 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
899 \param[in] ocshadow: channel output shadow state
900 only one parameter can be selected which is shown as below:
901 \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
902 \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
903 \param[out] none
904 \retval none
905 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)906 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
907 {
908 switch(channel){
909 /* configure TIMER_CH_0 */
910 case TIMER_CH_0:
911 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
912 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
913 break;
914 /* configure TIMER_CH_1 */
915 case TIMER_CH_1:
916 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
917 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
918 break;
919 /* configure TIMER_CH_2 */
920 case TIMER_CH_2:
921 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
922 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
923 break;
924 /* configure TIMER_CH_3 */
925 case TIMER_CH_3:
926 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
927 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
928 break;
929 default:
930 break;
931 }
932 }
933
934 /*!
935 \brief configure TIMER channel output fast function
936 \param[in] timer_periph: TIMERx(x=0..4)
937 \param[in] channel:
938 only one parameter can be selected which is shown as below:
939 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
940 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
941 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
942 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
943 \param[in] ocfast: channel output fast function
944 only one parameter can be selected which is shown as below:
945 \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
946 \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
947 \param[out] none
948 \retval none
949 */
timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast)950 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
951 {
952 switch(channel){
953 /* configure TIMER_CH_0 */
954 case TIMER_CH_0:
955 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
956 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
957 break;
958 /* configure TIMER_CH_1 */
959 case TIMER_CH_1:
960 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
961 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
962 break;
963 /* configure TIMER_CH_2 */
964 case TIMER_CH_2:
965 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
966 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
967 break;
968 /* configure TIMER_CH_3 */
969 case TIMER_CH_3:
970 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
971 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
972 break;
973 default:
974 break;
975 }
976 }
977
978 /*!
979 \brief configure TIMER channel output clear function
980 \param[in] timer_periph: TIMERx(x=0..4)
981 \param[in] channel:
982 only one parameter can be selected which is shown as below:
983 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
984 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
985 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
986 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
987 \param[in] occlear: channel output clear function
988 only one parameter can be selected which is shown as below:
989 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
990 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
991 \param[out] none
992 \retval none
993 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)994 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
995 {
996 switch(channel){
997 /* configure TIMER_CH_0 */
998 case TIMER_CH_0:
999 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1000 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1001 break;
1002 /* configure TIMER_CH_1 */
1003 case TIMER_CH_1:
1004 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1005 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1006 break;
1007 /* configure TIMER_CH_2 */
1008 case TIMER_CH_2:
1009 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1010 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1011 break;
1012 /* configure TIMER_CH_3 */
1013 case TIMER_CH_3:
1014 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1015 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1016 break;
1017 default:
1018 break;
1019 }
1020 }
1021
1022 /*!
1023 \brief configure TIMER channel output polarity
1024 \param[in] timer_periph: TIMERx(x=0..4)
1025 \param[in] channel:
1026 only one parameter can be selected which is shown as below:
1027 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1028 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1029 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1030 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1031 \param[in] ocpolarity: channel output polarity
1032 only one parameter can be selected which is shown as below:
1033 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1034 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1035 \param[out] none
1036 \retval none
1037 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1038 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1039 {
1040 switch(channel){
1041 /* configure TIMER_CH_0 */
1042 case TIMER_CH_0:
1043 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1044 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1045 break;
1046 /* configure TIMER_CH_1 */
1047 case TIMER_CH_1:
1048 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1049 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1050 break;
1051 /* configure TIMER_CH_2 */
1052 case TIMER_CH_2:
1053 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1054 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1055 break;
1056 /* configure TIMER_CH_3 */
1057 case TIMER_CH_3:
1058 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1059 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1060 break;
1061 default:
1062 break;
1063 }
1064 }
1065
1066 /*!
1067 \brief configure TIMER channel complementary output polarity
1068 \param[in] timer_periph: TIMERx(x=0)
1069 \param[in] channel:
1070 only one parameter can be selected which is shown as below:
1071 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0))
1072 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0))
1073 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0))
1074 \param[in] ocnpolarity: channel complementary output polarity
1075 only one parameter can be selected which is shown as below:
1076 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1077 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1078 \param[out] none
1079 \retval none
1080 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1081 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1082 {
1083 switch(channel){
1084 /* configure TIMER_CH_0 */
1085 case TIMER_CH_0:
1086 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1087 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1088 break;
1089 /* configure TIMER_CH_1 */
1090 case TIMER_CH_1:
1091 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1092 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1093 break;
1094 /* configure TIMER_CH_2 */
1095 case TIMER_CH_2:
1096 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1097 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1098 break;
1099 default:
1100 break;
1101 }
1102 }
1103
1104 /*!
1105 \brief configure TIMER channel enable state
1106 \param[in] timer_periph: TIMERx(x=0..4)
1107 \param[in] channel:
1108 only one parameter can be selected which is shown as below:
1109 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1110 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1111 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1112 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1113 \param[in] state: TIMER channel enable state
1114 only one parameter can be selected which is shown as below:
1115 \arg TIMER_CCX_ENABLE: channel enable
1116 \arg TIMER_CCX_DISABLE: channel disable
1117 \param[out] none
1118 \retval none
1119 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1120 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1121 {
1122 switch(channel){
1123 /* configure TIMER_CH_0 */
1124 case TIMER_CH_0:
1125 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1126 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1127 break;
1128 /* configure TIMER_CH_1 */
1129 case TIMER_CH_1:
1130 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1131 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1132 break;
1133 /* configure TIMER_CH_2 */
1134 case TIMER_CH_2:
1135 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1136 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1137 break;
1138 /* configure TIMER_CH_3 */
1139 case TIMER_CH_3:
1140 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1141 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1142 break;
1143 default:
1144 break;
1145 }
1146 }
1147
1148 /*!
1149 \brief configure TIMER channel complementary output enable state
1150 \param[in] timer_periph: TIMERx(x=0)
1151 \param[in] channel:
1152 only one parameter can be selected which is shown as below:
1153 \arg TIMER_CH_0: TIMER channel 0
1154 \arg TIMER_CH_1: TIMER channel 1
1155 \arg TIMER_CH_2: TIMER channel 2
1156 \param[in] ocnstate: TIMER channel complementary output enable state
1157 only one parameter can be selected which is shown as below:
1158 \arg TIMER_CCXN_ENABLE: channel complementary enable
1159 \arg TIMER_CCXN_DISABLE: channel complementary disable
1160 \param[out] none
1161 \retval none
1162 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1163 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1164 {
1165 switch(channel){
1166 /* configure TIMER_CH_0 */
1167 case TIMER_CH_0:
1168 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1169 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1170 break;
1171 /* configure TIMER_CH_1 */
1172 case TIMER_CH_1:
1173 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1174 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1175 break;
1176 /* configure TIMER_CH_2 */
1177 case TIMER_CH_2:
1178 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1179 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1180 break;
1181 default:
1182 break;
1183 }
1184 }
1185
1186 /*!
1187 \brief initialize TIMER channel input parameter struct with a default value
1188 \param[in] icpara: TIMER channel intput parameter struct
1189 \param[out] none
1190 \retval none
1191 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1192 void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
1193 {
1194 /* initialize the channel input parameter struct member with the default value */
1195 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1196 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1197 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1198 icpara->icfilter = 0U;
1199 }
1200
1201 /*!
1202 \brief configure TIMER input capture parameter
1203 \param[in] timer_periph: TIMERx(x=0..4)
1204 \param[in] channel:
1205 only one parameter can be selected which is shown as below:
1206 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1207 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1208 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1209 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1210 \param[in] icpara: TIMER channel intput parameter struct
1211 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING,
1212 TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8)
1213 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI,
1214 TIMER_IC_SELECTION_ITS
1215 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
1216 TIMER_IC_PSC_DIV8
1217 icfilter: 0~15
1218 \param[out] none
1219 \retval none
1220 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1221 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
1222 {
1223 switch(channel){
1224 /* configure TIMER_CH_0 */
1225 case TIMER_CH_0:
1226 /* reset the CH0EN bit */
1227 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1228
1229 /* reset the CH0P and CH0NP bits */
1230 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1231 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1232 /* reset the CH0MS bit */
1233 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1234 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1235 /* reset the CH0CAPFLT bit */
1236 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1237 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1238
1239 /* set the CH0EN bit */
1240 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1241 break;
1242
1243 /* configure TIMER_CH_1 */
1244 case TIMER_CH_1:
1245 /* reset the CH1EN bit */
1246 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1247
1248 /* reset the CH1P and CH1NP bits */
1249 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1250 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1251 /* reset the CH1MS bit */
1252 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1253 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1254 /* reset the CH1CAPFLT bit */
1255 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1256 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1257
1258 /* set the CH1EN bit */
1259 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1260 break;
1261 /* configure TIMER_CH_2 */
1262 case TIMER_CH_2:
1263 /* reset the CH2EN bit */
1264 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1265
1266 /* reset the CH2P and CH2NP bits */
1267 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
1268 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1269
1270 /* reset the CH2MS bit */
1271 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1272 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1273
1274 /* reset the CH2CAPFLT bit */
1275 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1276 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1277
1278 /* set the CH2EN bit */
1279 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1280 break;
1281 /* configure TIMER_CH_3 */
1282 case TIMER_CH_3:
1283 /* reset the CH3EN bit */
1284 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1285
1286 /* reset the CH3P bits */
1287 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1288 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1289
1290 /* reset the CH3MS bit */
1291 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1292 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1293
1294 /* reset the CH3CAPFLT bit */
1295 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1296 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1297
1298 /* set the CH3EN bit */
1299 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1300 break;
1301 default:
1302 break;
1303 }
1304 /* configure TIMER channel input capture prescaler value */
1305 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1306 }
1307
1308 /*!
1309 \brief configure TIMER channel input capture prescaler value
1310 \param[in] timer_periph: TIMERx(x=0..4)
1311 \param[in] channel:
1312 only one parameter can be selected which is shown as below:
1313 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1314 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1315 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1316 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1317 \param[in] prescaler: channel input capture prescaler value
1318 only one parameter can be selected which is shown as below:
1319 \arg TIMER_IC_PSC_DIV1: no prescaler
1320 \arg TIMER_IC_PSC_DIV2: divided by 2
1321 \arg TIMER_IC_PSC_DIV4: divided by 4
1322 \arg TIMER_IC_PSC_DIV8: divided by 8
1323 \param[out] none
1324 \retval none
1325 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1326 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1327 {
1328 switch(channel){
1329 /* configure TIMER_CH_0 */
1330 case TIMER_CH_0:
1331 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1332 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1333 break;
1334 /* configure TIMER_CH_1 */
1335 case TIMER_CH_1:
1336 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1337 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1338 break;
1339 /* configure TIMER_CH_2 */
1340 case TIMER_CH_2:
1341 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1342 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1343 break;
1344 /* configure TIMER_CH_3 */
1345 case TIMER_CH_3:
1346 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1347 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1348 break;
1349 default:
1350 break;
1351 }
1352 }
1353
1354 /*!
1355 \brief read TIMER channel capture compare register value
1356 \param[in] timer_periph: please refer to the following parameters
1357 \param[in] channel:
1358 only one parameter can be selected which is shown as below:
1359 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1360 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1361 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1362 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1363 \param[out] none
1364 \retval channel capture compare register value
1365 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1366 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1367 {
1368 uint32_t count_value = 0U;
1369
1370 switch(channel){
1371 case TIMER_CH_0:
1372 /* read TIMER channel 0 capture compare register value */
1373 count_value = TIMER_CH0CV(timer_periph);
1374 break;
1375 case TIMER_CH_1:
1376 /* read TIMER channel 1 capture compare register value */
1377 count_value = TIMER_CH1CV(timer_periph);
1378 break;
1379 case TIMER_CH_2:
1380 /* read TIMER channel 2 capture compare register value */
1381 count_value = TIMER_CH2CV(timer_periph);
1382 break;
1383 case TIMER_CH_3:
1384 /* read TIMER channel 3 capture compare register value */
1385 count_value = TIMER_CH3CV(timer_periph);
1386 break;
1387 default:
1388 break;
1389 }
1390 return (count_value);
1391 }
1392
1393 /*!
1394 \brief configure TIMER input pwm capture function
1395 \param[in] timer_periph: TIMERx(x=0..4)
1396 \param[in] channel:
1397 only one parameter can be selected which is shown as below:
1398 \arg TIMER_CH_0: TIMER channel 0
1399 \arg TIMER_CH_1: TIMER channel 1
1400 \param[in] icpwm: TIMER channel intput pwm parameter struct
1401 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING
1402 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI
1403 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
1404 TIMER_IC_PSC_DIV8
1405 icfilter: 0~15
1406 \param[out] none
1407 \retval none
1408 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1409 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1410 {
1411 uint16_t icpolarity = 0x0U;
1412 uint16_t icselection = 0x0U;
1413
1414 /* Set channel input polarity */
1415 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1416 icpolarity = TIMER_IC_POLARITY_FALLING;
1417 }else{
1418 icpolarity = TIMER_IC_POLARITY_RISING;
1419 }
1420 /* Set channel input mode selection */
1421 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1422 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1423 }else{
1424 icselection = TIMER_IC_SELECTION_DIRECTTI;
1425 }
1426
1427 if(TIMER_CH_0 == channel){
1428 /* reset the CH0EN bit */
1429 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1430 /* reset the CH0P and CH0NP bits */
1431 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1432 /* set the CH0P and CH0NP bits */
1433 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1434 /* reset the CH0MS bit */
1435 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1436 /* set the CH0MS bit */
1437 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1438 /* reset the CH0CAPFLT bit */
1439 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1440 /* set the CH0CAPFLT bit */
1441 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1442 /* set the CH0EN bit */
1443 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1444 /* configure TIMER channel input capture prescaler value */
1445 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1446
1447 /* reset the CH1EN bit */
1448 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1449 /* reset the CH1P and CH1NP bits */
1450 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1451 /* set the CH1P and CH1NP bits */
1452 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1453 /* reset the CH1MS bit */
1454 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1455 /* set the CH1MS bit */
1456 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1457 /* reset the CH1CAPFLT bit */
1458 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1459 /* set the CH1CAPFLT bit */
1460 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1461 /* set the CH1EN bit */
1462 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1463 /* configure TIMER channel input capture prescaler value */
1464 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1465 }else{
1466 /* reset the CH1EN bit */
1467 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1468 /* reset the CH1P and CH1NP bits */
1469 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1470 /* set the CH1P and CH1NP bits */
1471 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1472 /* reset the CH1MS bit */
1473 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1474 /* set the CH1MS bit */
1475 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1476 /* reset the CH1CAPFLT bit */
1477 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1478 /* set the CH1CAPFLT bit */
1479 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1480 /* set the CH1EN bit */
1481 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1482 /* configure TIMER channel input capture prescaler value */
1483 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1484
1485 /* reset the CH0EN bit */
1486 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1487 /* reset the CH0P and CH0NP bits */
1488 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1489 /* set the CH0P and CH0NP bits */
1490 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1491 /* reset the CH0MS bit */
1492 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1493 /* set the CH0MS bit */
1494 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1495 /* reset the CH0CAPFLT bit */
1496 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1497 /* set the CH0CAPFLT bit */
1498 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1499 /* set the CH0EN bit */
1500 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1501 /* configure TIMER channel input capture prescaler value */
1502 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1503 }
1504 }
1505
1506 /*!
1507 \brief configure TIMER hall sensor mode
1508 \param[in] timer_periph: TIMERx(x=0..4)
1509 \param[in] hallmode:
1510 only one parameter can be selected which is shown as below:
1511 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1512 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1513 \param[out] none
1514 \retval none
1515 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1516 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1517 {
1518 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1519 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1520 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1521 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1522 }else{
1523 /* illegal parameters */
1524 }
1525 }
1526
1527 /*!
1528 \brief select TIMER input trigger source
1529 \param[in] timer_periph: TIMERx(x=0..4)
1530 \param[in] intrigger:
1531 only one parameter can be selected which is shown as below:
1532 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4))
1533 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4))
1534 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4))
1535 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4))
1536 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4))
1537 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4))
1538 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4))
1539 \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4))
1540 \param[out] none
1541 \retval none
1542 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)1543 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1544 {
1545 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1546 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1547 }
1548
1549 /*!
1550 \brief select TIMER master mode output trigger source
1551 \param[in] timer_periph: TIMERx(x=0..6)
1552 \param[in] outrigger:
1553 only one parameter can be selected which is shown as below:
1554 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6))
1555 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6))
1556 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6))
1557 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4))
1558 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4))
1559 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4))
1560 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4))
1561 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4))
1562 \param[out] none
1563 \retval none
1564 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)1565 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1566 {
1567 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1568 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1569 }
1570
1571 /*!
1572 \brief select TIMER slave mode
1573 \param[in] timer_periph: TIMERx(x=0..4)
1574 \param[in] slavemode:
1575 only one parameter can be selected which is shown as below:
1576 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
1577 \arg TIMER_ENCODER_MODE0: encoder mode 0
1578 \arg TIMER_ENCODER_MODE1: encoder mode 1
1579 \arg TIMER_ENCODER_MODE2: encoder mode 2
1580 \arg TIMER_SLAVE_MODE_RESTART: restart mode
1581 \arg TIMER_SLAVE_MODE_PAUSE: pause mode
1582 \arg TIMER_SLAVE_MODE_EVENT: event mode
1583 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0
1584 \param[out] none
1585 \retval none
1586 */
1587
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)1588 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1589 {
1590 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1591 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1592 }
1593
1594 /*!
1595 \brief configure TIMER master slave mode
1596 \param[in] timer_periph: TIMERx(x=0..4)
1597 \param[in] masterslave:
1598 only one parameter can be selected which is shown as below:
1599 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
1600 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
1601 \param[out] none
1602 \retval none
1603 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)1604 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
1605 {
1606 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1607 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1608 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1609 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1610 }else{
1611 /* illegal parameters */
1612 }
1613 }
1614
1615 /*!
1616 \brief configure TIMER external trigger input
1617 \param[in] timer_periph: TIMERx(x=0..4)
1618 \param[in] extprescaler:
1619 only one parameter can be selected which is shown as below:
1620 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1621 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1622 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1623 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1624 \param[in] extpolarity:
1625 only one parameter can be selected which is shown as below:
1626 \arg TIMER_ETP_FALLING: active low or falling edge active
1627 \arg TIMER_ETP_RISING: active high or rising edge active
1628 \param[in] extfilter: a value between 0 and 15
1629 \param[out] none
1630 \retval none
1631 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1632 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1633 {
1634 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1635 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
1636 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1637 }
1638
1639 /*!
1640 \brief configure TIMER quadrature decoder mode
1641 \param[in] timer_periph: TIMERx(x=0..4)
1642 \param[in] decomode:
1643 only one parameter can be selected which is shown as below:
1644 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
1645 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
1646 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
1647 \param[in] ic0polarity:
1648 only one parameter can be selected which is shown as below:
1649 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1650 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1651 \param[in] ic1polarity:
1652 only one parameter can be selected which is shown as below:
1653 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1654 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1655 \param[out] none
1656 \retval none
1657 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)1658 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
1659 {
1660 /* configure the quadrature decoder mode */
1661 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1662 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1663 /* configure input capture selection */
1664 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1665 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1666 /* configure channel input capture polarity */
1667 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1668 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1669 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
1670 }
1671
1672 /*!
1673 \brief configure TIMER internal clock mode
1674 \param[in] timer_periph: TIMERx(x=0..4)
1675 \param[out] none
1676 \retval none
1677 */
timer_internal_clock_config(uint32_t timer_periph)1678 void timer_internal_clock_config(uint32_t timer_periph)
1679 {
1680 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1681 }
1682
1683 /*!
1684 \brief configure TIMER the internal trigger as external clock input
1685 \param[in] timer_periph: TIMERx(x=0..4)
1686 \param[in] intrigger:
1687 only one parameter can be selected which is shown as below:
1688 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1689 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1690 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1691 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1692 \param[out] none
1693 \retval none
1694 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)1695 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1696 {
1697 timer_input_trigger_source_select(timer_periph, intrigger);
1698 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1699 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1700 }
1701
1702 /*!
1703 \brief configure TIMER the external trigger as external clock input
1704 \param[in] timer_periph: TIMERx(x=0..4)
1705 \param[in] extrigger:
1706 only one parameter can be selected which is shown as below:
1707 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1708 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1709 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1710 \param[in] extpolarity:
1711 only one parameter can be selected which is shown as below:
1712 \arg TIMER_IC_POLARITY_RISING: active low or falling edge active
1713 \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active
1714 \param[in] extfilter: a value between 0 and 15
1715 \param[out] none
1716 \retval none
1717 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)1718 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
1719 {
1720 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1721 /* reset the CH1EN bit */
1722 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1723 /* reset the CH1NP bit */
1724 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1725 /* set the CH1NP bit */
1726 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
1727 /* reset the CH1MS bit */
1728 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1729 /* set the CH1MS bit */
1730 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1731 /* reset the CH1CAPFLT bit */
1732 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1733 /* set the CH1CAPFLT bit */
1734 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
1735 /* set the CH1EN bit */
1736 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1737 }else{
1738 /* reset the CH0EN bit */
1739 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1740 /* reset the CH0P and CH0NP bits */
1741 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1742 /* set the CH0P and CH0NP bits */
1743 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
1744 /* reset the CH0MS bit */
1745 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1746 /* set the CH0MS bit */
1747 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1748 /* reset the CH0CAPFLT bit */
1749 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1750 /* reset the CH0CAPFLT bit */
1751 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
1752 /* set the CH0EN bit */
1753 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1754 }
1755 /* select TIMER input trigger source */
1756 timer_input_trigger_source_select(timer_periph, extrigger);
1757 /* reset the SMC bit */
1758 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1759 /* set the SMC bit */
1760 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1761 }
1762
1763 /*!
1764 \brief configure TIMER the external clock mode0
1765 \param[in] timer_periph: TIMERx(x=0..4)
1766 \param[in] extprescaler:
1767 only one parameter can be selected which is shown as below:
1768 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1769 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1770 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1771 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1772 \param[in] extpolarity:
1773 only one parameter can be selected which is shown as below:
1774 \arg TIMER_ETP_FALLING: active low or falling edge active
1775 \arg TIMER_ETP_RISING: active high or rising edge active
1776 \param[in] extfilter: a value between 0 and 15
1777 \param[out] none
1778 \retval none
1779 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1780 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1781 {
1782 /* configure TIMER external trigger input */
1783 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1784 /* reset the SMC bit,TRGS bit */
1785 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1786 /* set the SMC bit,TRGS bit */
1787 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1788 }
1789
1790 /*!
1791 \brief configure TIMER the external clock mode1
1792 \param[in] timer_periph: TIMERx(x=0..4)
1793 \param[in] extprescaler:
1794 only one parameter can be selected which is shown as below:
1795 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1796 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1797 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1798 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1799 \param[in] extpolarity:
1800 only one parameter can be selected which is shown as below:
1801 \arg TIMER_ETP_FALLING: active low or falling edge active
1802 \arg TIMER_ETP_RISING: active high or rising edge active
1803 \param[in] extfilter: a value between 0 and 15
1804 \param[out] none
1805 \retval none
1806 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1807 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1808 {
1809 /* configure TIMER external trigger input */
1810 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1811 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1812 }
1813
1814 /*!
1815 \brief disable TIMER the external clock mode1
1816 \param[in] timer_periph: TIMERx(x=0..4)
1817 \param[out] none
1818 \retval none
1819 */
timer_external_clock_mode1_disable(uint32_t timer_periph)1820 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1821 {
1822 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1823 }
1824
1825 /*!
1826 \brief enable the TIMER interrupt
1827 \param[in] timer_periph: please refer to the following parameters
1828 \param[in] interrupt: specify which interrupt to enable
1829 one or more parameters can be selected which are shown as below:
1830 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
1831 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
1832 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
1833 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
1834 \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4)
1835 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
1836 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
1837 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
1838 \param[out] none
1839 \retval none
1840 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)1841 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
1842 {
1843 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
1844 }
1845
1846 /*!
1847 \brief disable the TIMER interrupt
1848 \param[in] timer_periph: TIMERx(x=0..6)
1849 \param[in] interrupt: specify which interrupt to disbale
1850 one or more parameters can be selected which are shown as below:
1851 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
1852 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
1853 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
1854 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
1855 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4)
1856 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
1857 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
1858 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
1859 \param[out] none
1860 \retval none
1861 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)1862 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
1863 {
1864 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
1865 }
1866
1867 /*!
1868 \brief get timer interrupt flag
1869 \param[in] timer_periph: TIMERx(x=0..6)
1870 \param[in] interrupt: the timer interrupt bits
1871 only one parameter can be selected which is shown as below:
1872 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
1873 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
1874 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
1875 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
1876 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
1877 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0)
1878 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
1879 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
1880 \param[out] none
1881 \retval FlagStatus: SET or RESET
1882 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt)1883 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
1884 {
1885 uint32_t val;
1886 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
1887 if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){
1888 return SET;
1889 }else{
1890 return RESET;
1891 }
1892 }
1893
1894 /*!
1895 \brief clear TIMER interrupt flag
1896 \param[in] timer_periph: TIMERx(x=0..6)
1897 \param[in] interrupt: the timer interrupt bits
1898 one or more parameters can be selected which are shown as below:
1899 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
1900 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
1901 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
1902 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
1903 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
1904 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0)
1905 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..4)
1906 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
1907 \param[out] none
1908 \retval none
1909 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt)1910 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
1911 {
1912 TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
1913 }
1914
1915 /*!
1916 \brief get TIMER flags
1917 \param[in] timer_periph: TIMERx(x=0..6)
1918 \param[in] flag: the timer interrupt flags
1919 only one parameter can be selected which is shown as below:
1920 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
1921 \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
1922 \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
1923 \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
1924 \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
1925 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
1926 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4)
1927 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
1928 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
1929 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
1930 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
1931 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
1932 \param[out] none
1933 \retval FlagStatus: SET or RESET
1934 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)1935 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
1936 {
1937 if(RESET != (TIMER_INTF(timer_periph) & flag)){
1938 return SET;
1939 }else{
1940 return RESET;
1941 }
1942 }
1943
1944 /*!
1945 \brief clear TIMER flags
1946 \param[in] timer_periph: TIMERx(x=0..6)
1947 \param[in] flag: the timer interrupt flags
1948 one or more parameters can be selected which are shown as below:
1949 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
1950 \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
1951 \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
1952 \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
1953 \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
1954 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
1955 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4)
1956 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
1957 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
1958 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
1959 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
1960 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
1961 \param[out] none
1962 \retval none
1963 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)1964 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
1965 {
1966 TIMER_INTF(timer_periph) = (~(uint32_t)flag);
1967 }
1968
