1 /*!
2 \file gd32f403_timer.c
3 \brief TIMER driver
4
5 \version 2017-02-10, V1.0.0, firmware for GD32F403
6 \version 2018-12-12, V2.0.0, firmware for GD32F403
7 \version 2020-09-30, V2.1.0, firmware for GD32F403
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f403_timer.h"
38
39 /*!
40 \brief deinit a TIMER
41 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
42 \param[out] none
43 \retval none
44 */
timer_deinit(uint32_t timer_periph)45 void timer_deinit(uint32_t timer_periph)
46 {
47 switch(timer_periph){
48 case TIMER0:
49 /* reset TIMER0 */
50 rcu_periph_reset_enable(RCU_TIMER0RST);
51 rcu_periph_reset_disable(RCU_TIMER0RST);
52 break;
53 case TIMER2:
54 /* reset TIMER2 */
55 rcu_periph_reset_enable(RCU_TIMER2RST);
56 rcu_periph_reset_disable(RCU_TIMER2RST);
57 break;
58 case TIMER3:
59 /* reset TIMER3 */
60 rcu_periph_reset_enable(RCU_TIMER3RST);
61 rcu_periph_reset_disable(RCU_TIMER3RST);
62 break;
63 case TIMER5:
64 /* reset TIMER5 */
65 rcu_periph_reset_enable(RCU_TIMER5RST);
66 rcu_periph_reset_disable(RCU_TIMER5RST);
67 break;
68 case TIMER6:
69 /* reset TIMER6 */
70 rcu_periph_reset_enable(RCU_TIMER6RST);
71 rcu_periph_reset_disable(RCU_TIMER6RST);
72 break;
73 case TIMER7:
74 /* reset TIMER7 */
75 rcu_periph_reset_enable(RCU_TIMER7RST);
76 rcu_periph_reset_disable(RCU_TIMER7RST);
77 break;
78 case TIMER8:
79 /* reset TIMER8 */
80 rcu_periph_reset_enable(RCU_TIMER8RST);
81 rcu_periph_reset_disable(RCU_TIMER8RST);
82 break;
83 case TIMER9:
84 /* reset TIMER9 */
85 rcu_periph_reset_enable(RCU_TIMER9RST);
86 rcu_periph_reset_disable(RCU_TIMER9RST);
87 break;
88 case TIMER10:
89 /* reset TIMER10 */
90 rcu_periph_reset_enable(RCU_TIMER10RST);
91 rcu_periph_reset_disable(RCU_TIMER10RST);
92 break;
93 case TIMER11:
94 /* reset TIMER11 */
95 rcu_periph_reset_enable(RCU_TIMER11RST);
96 rcu_periph_reset_disable(RCU_TIMER11RST);
97 break;
98 case TIMER12:
99 /* reset TIMER12 */
100 rcu_periph_reset_enable(RCU_TIMER12RST);
101 rcu_periph_reset_disable(RCU_TIMER12RST);
102 break;
103 case TIMER13:
104 /* reset TIMER13 */
105 rcu_periph_reset_enable(RCU_TIMER13RST);
106 rcu_periph_reset_disable(RCU_TIMER13RST);
107 break;
108 default:
109 break;
110 }
111 }
112
113 /*!
114 \brief initialize TIMER init parameter struct with a default value
115 \param[in] initpara: init parameter struct
116 \param[out] none
117 \retval none
118 */
timer_struct_para_init(timer_parameter_struct * initpara)119 void timer_struct_para_init(timer_parameter_struct* initpara)
120 {
121 /* initialize the init parameter struct member with the default value */
122 initpara->prescaler = 0U;
123 initpara->alignedmode = TIMER_COUNTER_EDGE;
124 initpara->counterdirection = TIMER_COUNTER_UP;
125 initpara->period = 65535U;
126 initpara->clockdivision = TIMER_CKDIV_DIV1;
127 initpara->repetitioncounter = 0U;
128 }
129
130 /*!
131 \brief initialize TIMER counter
132 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
133 \param[in] initpara: init parameter struct
134 prescaler: prescaler value of the counter clock, 0~65535
135 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH
136 counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
137 period: counter auto reload value, 0~65535
138 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
139 repetitioncounter: counter repetition value, 0~255
140 \param[out] none
141 \retval none
142 */
gd32_timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)143 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
144 {
145 /* configure the counter prescaler value */
146 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
147
148 /* configure the counter direction and aligned mode */
149 if((TIMER0 == timer_periph) || (TIMER2 == timer_periph)
150 || (TIMER3 == timer_periph) || (TIMER7 == timer_periph)){
151 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM);
152 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
153 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
154 }
155
156 /* configure the autoreload value */
157 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
158
159 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
160 /* reset the CKDIV bit */
161 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
162 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
163 }
164
165 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
166 /* configure the repetition counter value */
167 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
168 }
169
170 /* generate an update event */
171 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
172 }
173
174 /*!
175 \brief enable a TIMER
176 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
177 \param[out] none
178 \retval none
179 */
timer_enable(uint32_t timer_periph)180 void timer_enable(uint32_t timer_periph)
181 {
182 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
183 }
184
185 /*!
186 \brief disable a TIMER
187 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
188 \param[out] none
189 \retval none
190 */
timer_disable(uint32_t timer_periph)191 void timer_disable(uint32_t timer_periph)
192 {
193 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
194 }
195
196 /*!
197 \brief enable the auto reload shadow function
198 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
199 \param[out] none
200 \retval none
201 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)202 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
203 {
204 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
205 }
206
207 /*!
208 \brief disable the auto reload shadow function
209 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
210 \param[out] none
211 \retval none
212 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)213 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
214 {
215 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
216 }
217
218 /*!
219 \brief enable the update event
220 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
221 \param[out] none
222 \retval none
223 */
timer_update_event_enable(uint32_t timer_periph)224 void timer_update_event_enable(uint32_t timer_periph)
225 {
226 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
227 }
228
229 /*!
230 \brief disable the update event
231 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
232 \param[out] none
233 \retval none
234 */
timer_update_event_disable(uint32_t timer_periph)235 void timer_update_event_disable(uint32_t timer_periph)
236 {
237 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
238 }
239
240 /*!
241 \brief set TIMER counter alignment mode
242 \param[in] timer_periph: TIMERx(x=0,2,3,7)
243 \param[in] aligned:
244 only one parameter can be selected which is shown as below:
245 \arg TIMER_COUNTER_EDGE: edge-aligned mode
246 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
247 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
248 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
249 \param[out] none
250 \retval none
251 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)252 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
253 {
254 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
255 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
256 }
257
258 /*!
259 \brief set TIMER counter up direction
260 \param[in] timer_periph: TIMERx(x=0,2,3,7)
261 \param[out] none
262 \retval none
263 */
timer_counter_up_direction(uint32_t timer_periph)264 void timer_counter_up_direction(uint32_t timer_periph)
265 {
266 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
267 }
268
269 /*!
270 \brief set TIMER counter down direction
271 \param[in] timer_periph: TIMERx(x=0,2,3,7)
272 \param[out] none
273 \retval none
274 */
timer_counter_down_direction(uint32_t timer_periph)275 void timer_counter_down_direction(uint32_t timer_periph)
276 {
277 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
278 }
279
280 /*!
281 \brief configure TIMER prescaler
282 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
283 \param[in] prescaler: prescaler value,0~65535
284 \param[in] pscreload: prescaler reload mode
285 only one parameter can be selected which is shown as below:
286 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
287 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
288 \param[out] none
289 \retval none
290 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint8_t pscreload)291 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
292 {
293 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
294
295 if(TIMER_PSC_RELOAD_NOW == pscreload){
296 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
297 }
298 }
299
300 /*!
301 \brief configure TIMER repetition register value
302 \param[in] timer_periph: TIMERx(x=0,7)
303 \param[in] repetition: the counter repetition value,0~255
304 \param[out] none
305 \retval none
306 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)307 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
308 {
309 TIMER_CREP(timer_periph) = (uint32_t)repetition;
310 }
311
312 /*!
313 \brief configure TIMER autoreload register value
314 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
315 \param[in] autoreload: the counter auto-reload value,0~65535
316 \param[out] none
317 \retval none
318 */
timer_autoreload_value_config(uint32_t timer_periph,uint16_t autoreload)319 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
320 {
321 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
322 }
323
324 /*!
325 \brief configure TIMER counter register value
326 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
327 \param[in] counter: the counter value,0~65535
328 \param[out] none
329 \retval none
330 */
timer_counter_value_config(uint32_t timer_periph,uint16_t counter)331 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
332 {
333 TIMER_CNT(timer_periph) = (uint32_t)counter;
334 }
335
336 /*!
337 \brief read TIMER counter value
338 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
339 \param[out] none
340 \retval counter value
341 */
timer_counter_read(uint32_t timer_periph)342 uint32_t timer_counter_read(uint32_t timer_periph)
343 {
344 uint32_t count_value = 0U;
345 count_value = TIMER_CNT(timer_periph);
346 return (count_value);
347 }
348
349 /*!
350 \brief read TIMER prescaler value
351 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
352 \param[out] none
353 \retval prescaler register value
354 */
timer_prescaler_read(uint32_t timer_periph)355 uint16_t timer_prescaler_read(uint32_t timer_periph)
356 {
357 uint16_t prescaler_value = 0U;
358 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
359 return (prescaler_value);
360 }
361
362 /*!
363 \brief configure TIMER single pulse mode
364 \param[in] timer_periph: TIMERx(x=0,2,3,5..8,11)
365 \param[in] spmode:
366 only one parameter can be selected which is shown as below:
367 \arg TIMER_SP_MODE_SINGLE: single pulse mode
368 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
369 \param[out] none
370 \retval none
371 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)372 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
373 {
374 if(TIMER_SP_MODE_SINGLE == spmode){
375 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
376 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
377 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
378 }else{
379 /* illegal parameters */
380 }
381 }
382
383 /*!
384 \brief configure TIMER update source
385 \param[in] timer_periph: TIMERx(x=0,2,3,5..13)
386 \param[in] update:
387 only one parameter can be selected which is shown as below:
388 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
389 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
390 \param[out] none
391 \retval none
392 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)393 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
394 {
395 if(TIMER_UPDATE_SRC_REGULAR == update){
396 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
397 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
398 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
399 }else{
400 /* illegal parameters */
401 }
402 }
403
404 /*!
405 \brief enable the TIMER interrupt
406 \param[in] timer_periph: please refer to the following parameters
407 \param[in] interrupt: timer interrupt enable source
408 only one parameter can be selected which is shown as below:
409 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,3,5..13)
410 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,3,7..13)
411 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,3,7,8,11)
412 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2,3,7)
413 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2,3,7)
414 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
415 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,3,7,8,11)
416 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
417 \param[out] none
418 \retval none
419 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)420 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
421 {
422 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
423 }
424
425 /*!
426 \brief disable the TIMER interrupt
427 \param[in] timer_periph: please refer to the following parameters
428 \param[in] interrupt: timer interrupt source enable
429 only one parameter can be selected which is shown as below:
430 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,3,5..13)
431 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,3,7..13)
432 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,3,7,8,11)
433 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2,3,7)
434 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2,3,7)
435 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
436 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,3,7,8,11)
437 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
438 \param[out] none
439 \retval none
440 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)441 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
442 {
443 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
444 }
445
446 /*!
447 \brief get timer interrupt flag
448 \param[in] timer_periph: please refer to the following parameters
449 \param[in] interrupt: the timer interrupt bits
450 only one parameter can be selected which is shown as below:
451 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,3,5..13)
452 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,3,7..13)
453 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,3,7,8,11)
454 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2,3,7)
455 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2,3,7)
456 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
457 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
458 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
459 \param[out] none
460 \retval FlagStatus: SET or RESET
461 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt)462 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
463 {
464 uint32_t val;
465 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
466 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
467 return SET;
468 }else{
469 return RESET;
470 }
471 }
472
473 /*!
474 \brief clear TIMER interrupt flag
475 \param[in] timer_periph: please refer to the following parameters
476 \param[in] interrupt: the timer interrupt bits
477 only one parameter can be selected which is shown as below:
478 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,3,5..13)
479 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,3,7..13)
480 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,3,7,8,11)
481 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2,3,7)
482 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2,3,7)
483 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
484 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
485 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
486 \param[out] none
487 \retval none
488 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt)489 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
490 {
491 TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
492 }
493
494 /*!
495 \brief get TIMER flags
496 \param[in] timer_periph: please refer to the following parameters
497 \param[in] flag: the timer interrupt flags
498 only one parameter can be selected which is shown as below:
499 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0,2,3,5..13)
500 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0,2,3,7..13)
501 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0,2,3,7,8,11)
502 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0,2,3,7)
503 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0,2,3,7)
504 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
505 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
506 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
507 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0,2,3,7..11)
508 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0,2,3,7,8,11)
509 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0,2,3,7)
510 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0,2,3,7)
511 \param[out] none
512 \retval FlagStatus: SET or RESET
513 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)514 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
515 {
516 if(RESET != (TIMER_INTF(timer_periph) & flag)){
517 return SET;
518 }else{
519 return RESET;
520 }
521 }
522
523 /*!
524 \brief clear TIMER flags
525 \param[in] timer_periph: please refer to the following parameters
526 \param[in] flag: the timer interrupt flags
527 only one parameter can be selected which is shown as below:
528 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0,2,3,5..13)
529 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0,2,3,7..13)
530 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0,2,3,7,8,11)
531 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0,2,3,7)
532 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0,2,3,7)
533 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
534 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
535 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
536 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0,2,3,7..11)
537 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0,2,3,7,8,11)
538 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0,2,3,7)
539 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0,2,3,7)
540 \param[out] none
541 \retval none
542 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)543 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
544 {
545 TIMER_INTF(timer_periph) = (~(uint32_t)flag);
546 }
547
548 /*!
549 \brief enable the TIMER DMA
550 \param[in] timer_periph: please refer to the following parameters
551 \param[in] dma: specify which DMA to enable
552 one or more parameters can be selected which is shown as below:
553 \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0,2,3,5..7)
554 \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0,2,3,7)
555 \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0,2,3,7)
556 \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0,2,3,7)
557 \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0,2,3,7)
558 \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7)
559 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,2,3,7)
560 \param[out] none
561 \retval none
562 */
timer_dma_enable(uint32_t timer_periph,uint16_t dma)563 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
564 {
565 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
566 }
567
568 /*!
569 \brief disable the TIMER DMA
570 \param[in] timer_periph: please refer to the following parameters
571 \param[in] dma: specify which DMA to enable
572 one or more parameters can be selected which are shown as below:
573 \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0,2,3,5..7)
574 \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0,2,3,7)
575 \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0,2,3,7)
576 \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0,2,3,7)
577 \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0,2,3,7)
578 \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7)
579 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,2,3,7)
580 \param[out] none
581 \retval none
582 */
timer_dma_disable(uint32_t timer_periph,uint16_t dma)583 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
584 {
585 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
586 }
587
588 /*!
589 \brief channel DMA request source selection
590 \param[in] timer_periph: TIMERx(x=0,2,3,7)
591 \param[in] dma_request: channel DMA request source selection
592 only one parameter can be selected which is shown as below:
593 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
594 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
595 \param[out] none
596 \retval none
597 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request)598 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
599 {
600 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
601 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
602 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
603 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
604 }else{
605 /* illegal parameters */
606 }
607 }
608
609 /*!
610 \brief configure the TIMER DMA transfer
611 \param[in] timer_periph: please refer to the following parameters
612 \param[in] dma_baseaddr:
613 only one parameter can be selected which is shown as below:
614 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0,2,3,7)
615 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0,2,3,7)
616 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0,2,3,7)
617 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0,2,3,7)
618 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0,2,3,7)
619 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0,2,3,7)
620 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0,2,3,7)
621 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0,2,3,7)
622 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0,2,3,7)
623 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0,2,3,7)
624 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0,2,3,7)
625 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0,2,3,7)
626 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
627 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0,2,3,7)
628 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0,2,3,7)
629 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0,2,3,7)
630 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0,2,3,7)
631 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7)
632 \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0,2,3,7)
633 \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0,2,3,7)
634 \param[in] dma_lenth:
635 only one parameter can be selected which is shown as below:
636 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
637 \param[out] none
638 \retval none
639 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth)640 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
641 {
642 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
643 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
644 }
645
646 /*!
647 \brief software generate events
648 \param[in] timer_periph: please refer to the following parameters
649 \param[in] event: the timer software event generation sources
650 one or more parameters can be selected which are shown as below:
651 \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13)
652 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0,2,3,7..13)
653 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0,2,3,7,8,11)
654 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0,2,3,7)
655 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0,2,3,7)
656 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7)
657 \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0,2,3,7,8,11)
658 \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7)
659 \param[out] none
660 \retval none
661 */
timer_event_software_generate(uint32_t timer_periph,uint16_t event)662 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
663 {
664 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
665 }
666
667 /*!
668 \brief initialize TIMER break parameter struct with a default value
669 \param[in] breakpara: TIMER break parameter struct
670 \param[out] none
671 \retval none
672 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)673 void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
674 {
675 /* initialize the break parameter struct member with the default value */
676 breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
677 breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
678 breakpara->deadtime = 0U;
679 breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
680 breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
681 breakpara->protectmode = TIMER_CCHP_PROT_OFF;
682 breakpara->breakstate = TIMER_BREAK_DISABLE;
683 }
684
685 /*!
686 \brief configure TIMER break function
687 \param[in] timer_periph: TIMERx(x=0,7)
688 \param[in] breakpara: TIMER break parameter struct
689 runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
690 ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
691 deadtime: 0~255
692 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
693 outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
694 protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
695 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
696 \param[out] none
697 \retval none
698 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)699 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
700 {
701 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
702 ((uint32_t)(breakpara->ideloffstate))|
703 ((uint32_t)(breakpara->deadtime))|
704 ((uint32_t)(breakpara->breakpolarity))|
705 ((uint32_t)(breakpara->outputautostate)) |
706 ((uint32_t)(breakpara->protectmode))|
707 ((uint32_t)(breakpara->breakstate))) ;
708 }
709
710 /*!
711 \brief enable TIMER break function
712 \param[in] timer_periph: TIMERx(x=0,7)
713 \param[out] none
714 \retval none
715 */
timer_break_enable(uint32_t timer_periph)716 void timer_break_enable(uint32_t timer_periph)
717 {
718 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
719 }
720
721 /*!
722 \brief disable TIMER break function
723 \param[in] timer_periph: TIMERx(x=0,7)
724 \param[out] none
725 \retval none
726 */
timer_break_disable(uint32_t timer_periph)727 void timer_break_disable(uint32_t timer_periph)
728 {
729 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
730 }
731
732 /*!
733 \brief enable TIMER output automatic function
734 \param[in] timer_periph: TIMERx(x=0,7)
735 \param[out] none
736 \retval none
737 */
timer_automatic_output_enable(uint32_t timer_periph)738 void timer_automatic_output_enable(uint32_t timer_periph)
739 {
740 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
741 }
742
743 /*!
744 \brief disable TIMER output automatic function
745 \param[in] timer_periph: TIMERx(x=0,7)
746 \param[out] none
747 \retval none
748 */
timer_automatic_output_disable(uint32_t timer_periph)749 void timer_automatic_output_disable(uint32_t timer_periph)
750 {
751 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
752 }
753
754 /*!
755 \brief configure TIMER primary output function
756 \param[in] timer_periph: TIMERx(x=0,7)
757 \param[in] newvalue: ENABLE or DISABLE
758 \param[out] none
759 \retval none
760 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)761 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
762 {
763 if(ENABLE == newvalue){
764 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
765 }else{
766 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
767 }
768 }
769
770 /*!
771 \brief enable or disable channel capture/compare control shadow register
772 \param[in] timer_periph: TIMERx(x=0,7)
773 \param[in] newvalue: ENABLE or DISABLE
774 \param[out] none
775 \retval none
776 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)777 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
778 {
779 if(ENABLE == newvalue){
780 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
781 }else{
782 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
783 }
784 }
785
786 /*!
787 \brief configure TIMER channel control shadow register update control
788 \param[in] timer_periph: TIMERx(x=0,7)
789 \param[in] ccuctl: channel control shadow register update control
790 only one parameter can be selected which is shown as below:
791 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
792 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
793 \param[out] none
794 \retval none
795 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ccuctl)796 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
797 {
798 if(TIMER_UPDATECTL_CCU == ccuctl){
799 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
800 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
801 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
802 }else{
803 /* illegal parameters */
804 }
805 }
806
807 /*!
808 \brief initialize TIMER channel output parameter struct with a default value
809 \param[in] ocpara: TIMER channel n output parameter struct
810 \param[out] none
811 \retval none
812 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)813 void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
814 {
815 /* initialize the channel output parameter struct member with the default value */
816 ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE;
817 ocpara->outputnstate = TIMER_CCXN_DISABLE;
818 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
819 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
820 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
821 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
822 }
823
824 /*!
825 \brief configure TIMER channel output function
826 \param[in] timer_periph: please refer to the following parameters
827 \param[in] channel:
828 only one parameter can be selected which is shown as below:
829 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,2,3,7..13))
830 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,2,3,7,8,11))
831 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,2,3,7))
832 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,2,3,7))
833 \param[in] ocpara: TIMER channeln output parameter struct
834 outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
835 outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
836 ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
837 ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
838 ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
839 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
840 \param[out] none
841 \retval none
842 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)843 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
844 {
845 switch(channel){
846 /* configure TIMER_CH_0 */
847 case TIMER_CH_0:
848 /* reset the CH0EN bit */
849 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
850 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
851 /* set the CH0EN bit */
852 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
853 /* reset the CH0P bit */
854 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
855 /* set the CH0P bit */
856 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
857
858 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
859 /* reset the CH0NEN bit */
860 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
861 /* set the CH0NEN bit */
862 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
863 /* reset the CH0NP bit */
864 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
865 /* set the CH0NP bit */
866 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
867 /* reset the ISO0 bit */
868 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
869 /* set the ISO0 bit */
870 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
871 /* reset the ISO0N bit */
872 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
873 /* set the ISO0N bit */
874 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
875 }
876 break;
877 /* configure TIMER_CH_1 */
878 case TIMER_CH_1:
879 /* reset the CH1EN bit */
880 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
881 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
882 /* set the CH1EN bit */
883 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U);
884 /* reset the CH1P bit */
885 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
886 /* set the CH1P bit */
887 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
888
889 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
890 /* reset the CH1NEN bit */
891 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
892 /* set the CH1NEN bit */
893 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
894 /* reset the CH1NP bit */
895 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
896 /* set the CH1NP bit */
897 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
898 /* reset the ISO1 bit */
899 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
900 /* set the ISO1 bit */
901 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
902 /* reset the ISO1N bit */
903 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
904 /* set the ISO1N bit */
905 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
906 }
907 break;
908 /* configure TIMER_CH_2 */
909 case TIMER_CH_2:
910 /* reset the CH2EN bit */
911 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
912 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
913 /* set the CH2EN bit */
914 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U);
915 /* reset the CH2P bit */
916 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
917 /* set the CH2P bit */
918 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
919
920 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
921 /* reset the CH2NEN bit */
922 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
923 /* set the CH2NEN bit */
924 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
925 /* reset the CH2NP bit */
926 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
927 /* set the CH2NP bit */
928 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
929 /* reset the ISO2 bit */
930 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
931 /* set the ISO2 bit */
932 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
933 /* reset the ISO2N bit */
934 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
935 /* set the ISO2N bit */
936 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
937 }
938 break;
939 /* configure TIMER_CH_3 */
940 case TIMER_CH_3:
941 /* reset the CH3EN bit */
942 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
943 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
944 /* set the CH3EN bit */
945 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U);
946 /* reset the CH3P bit */
947 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
948 /* set the CH3P bit */
949 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
950
951 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
952 /* reset the ISO3 bit */
953 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
954 /* set the ISO3 bit */
955 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
956 }
957 break;
958 default:
959 break;
960 }
961 }
962
963 /*!
964 \brief configure TIMER channel output compare mode
965 \param[in] timer_periph: please refer to the following parameters
966 \param[in] channel:
967 only one parameter can be selected which is shown as below:
968 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
969 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
970 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
971 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
972 \param[in] ocmode: channel output compare mode
973 only one parameter can be selected which is shown as below:
974 \arg TIMER_OC_MODE_TIMING: timing mode
975 \arg TIMER_OC_MODE_ACTIVE: active mode
976 \arg TIMER_OC_MODE_INACTIVE: inactive mode
977 \arg TIMER_OC_MODE_TOGGLE: toggle mode
978 \arg TIMER_OC_MODE_LOW: force low mode
979 \arg TIMER_OC_MODE_HIGH: force high mode
980 \arg TIMER_OC_MODE_PWM0: PWM0 mode
981 \arg TIMER_OC_MODE_PWM1: PWM1 mode
982 \param[out] none
983 \retval none
984 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)985 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
986 {
987 switch(channel){
988 /* configure TIMER_CH_0 */
989 case TIMER_CH_0:
990 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
991 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
992 break;
993 /* configure TIMER_CH_1 */
994 case TIMER_CH_1:
995 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
996 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
997 break;
998 /* configure TIMER_CH_2 */
999 case TIMER_CH_2:
1000 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
1001 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
1002 break;
1003 /* configure TIMER_CH_3 */
1004 case TIMER_CH_3:
1005 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
1006 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
1007 break;
1008 default:
1009 break;
1010 }
1011 }
1012
1013 /*!
1014 \brief configure TIMER channel output pulse value
1015 \param[in] timer_periph: please refer to the following parameters
1016 \param[in] channel:
1017 only one parameter can be selected which is shown as below:
1018 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1019 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1020 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1021 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1022 \param[in] pulse: channel output pulse value,0~65535
1023 \param[out] none
1024 \retval none
1025 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)1026 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
1027 {
1028 switch(channel){
1029 /* configure TIMER_CH_0 */
1030 case TIMER_CH_0:
1031 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
1032 break;
1033 /* configure TIMER_CH_1 */
1034 case TIMER_CH_1:
1035 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
1036 break;
1037 /* configure TIMER_CH_2 */
1038 case TIMER_CH_2:
1039 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
1040 break;
1041 /* configure TIMER_CH_3 */
1042 case TIMER_CH_3:
1043 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049
1050 /*!
1051 \brief configure TIMER channel output shadow function
1052 \param[in] timer_periph: please refer to the following parameters
1053 \param[in] channel:
1054 only one parameter can be selected which is shown as below:
1055 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1056 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1057 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1058 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1059 \param[in] ocshadow: channel output shadow state
1060 only one parameter can be selected which is shown as below:
1061 \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
1062 \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
1063 \param[out] none
1064 \retval none
1065 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)1066 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
1067 {
1068 switch(channel){
1069 /* configure TIMER_CH_0 */
1070 case TIMER_CH_0:
1071 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
1072 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
1073 break;
1074 /* configure TIMER_CH_1 */
1075 case TIMER_CH_1:
1076 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
1077 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1078 break;
1079 /* configure TIMER_CH_2 */
1080 case TIMER_CH_2:
1081 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
1082 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
1083 break;
1084 /* configure TIMER_CH_3 */
1085 case TIMER_CH_3:
1086 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
1087 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1088 break;
1089 default:
1090 break;
1091 }
1092 }
1093
1094 /*!
1095 \brief configure TIMER channel output fast function
1096 \param[in] timer_periph: please refer to the following parameters
1097 \param[in] channel:
1098 only one parameter can be selected which is shown as below:
1099 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1100 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1101 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1102 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1103 \param[in] ocfast: channel output fast function
1104 only one parameter can be selected which is shown as below:
1105 \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
1106 \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
1107 \param[out] none
1108 \retval none
1109 */
timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast)1110 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
1111 {
1112 switch(channel){
1113 /* configure TIMER_CH_0 */
1114 case TIMER_CH_0:
1115 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1116 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1117 break;
1118 /* configure TIMER_CH_1 */
1119 case TIMER_CH_1:
1120 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1121 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1122 break;
1123 /* configure TIMER_CH_2 */
1124 case TIMER_CH_2:
1125 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1126 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1127 break;
1128 /* configure TIMER_CH_3 */
1129 case TIMER_CH_3:
1130 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1131 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1132 break;
1133 default:
1134 break;
1135 }
1136 }
1137
1138 /*!
1139 \brief configure TIMER channel output clear function
1140 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1141 \param[in] channel:
1142 only one parameter can be selected which is shown as below:
1143 \arg TIMER_CH_0: TIMER channel0
1144 \arg TIMER_CH_1: TIMER channel1
1145 \arg TIMER_CH_2: TIMER channel2
1146 \arg TIMER_CH_3: TIMER channel3
1147 \param[in] occlear: channel output clear function
1148 only one parameter can be selected which is shown as below:
1149 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
1150 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
1151 \param[out] none
1152 \retval none
1153 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)1154 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1155 {
1156 switch(channel){
1157 /* configure TIMER_CH_0 */
1158 case TIMER_CH_0:
1159 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1160 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1161 break;
1162 /* configure TIMER_CH_1 */
1163 case TIMER_CH_1:
1164 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1165 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1166 break;
1167 /* configure TIMER_CH_2 */
1168 case TIMER_CH_2:
1169 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1170 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1171 break;
1172 /* configure TIMER_CH_3 */
1173 case TIMER_CH_3:
1174 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1175 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1176 break;
1177 default:
1178 break;
1179 }
1180 }
1181
1182 /*!
1183 \brief configure TIMER channel output polarity
1184 \param[in] timer_periph: please refer to the following parameters
1185 \param[in] channel:
1186 only one parameter can be selected which is shown as below:
1187 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1188 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1189 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1190 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1191 \param[in] ocpolarity: channel output polarity
1192 only one parameter can be selected which is shown as below:
1193 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1194 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1195 \param[out] none
1196 \retval none
1197 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1198 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1199 {
1200 switch(channel){
1201 /* configure TIMER_CH_0 */
1202 case TIMER_CH_0:
1203 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1204 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1205 break;
1206 /* configure TIMER_CH_1 */
1207 case TIMER_CH_1:
1208 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1209 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1210 break;
1211 /* configure TIMER_CH_2 */
1212 case TIMER_CH_2:
1213 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1214 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1215 break;
1216 /* configure TIMER_CH_3 */
1217 case TIMER_CH_3:
1218 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1219 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1220 break;
1221 default:
1222 break;
1223 }
1224 }
1225
1226 /*!
1227 \brief configure TIMER channel complementary output polarity
1228 \param[in] timer_periph: please refer to the following parameters
1229 \param[in] channel:
1230 only one parameter can be selected which is shown as below:
1231 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7))
1232 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7))
1233 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7))
1234 \param[in] ocnpolarity: channel complementary output polarity
1235 only one parameter can be selected which is shown as below:
1236 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1237 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1238 \param[out] none
1239 \retval none
1240 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1241 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1242 {
1243 switch(channel){
1244 /* configure TIMER_CH_0 */
1245 case TIMER_CH_0:
1246 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1247 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1248 break;
1249 /* configure TIMER_CH_1 */
1250 case TIMER_CH_1:
1251 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1252 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1253 break;
1254 /* configure TIMER_CH_2 */
1255 case TIMER_CH_2:
1256 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1257 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1258 break;
1259 default:
1260 break;
1261 }
1262 }
1263
1264 /*!
1265 \brief configure TIMER channel enable state
1266 \param[in] timer_periph: please refer to the following parameters
1267 \param[in] channel:
1268 only one parameter can be selected which is shown as below:
1269 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1270 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1271 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1272 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1273 \param[in] state: TIMER channel enable state
1274 only one parameter can be selected which is shown as below:
1275 \arg TIMER_CCX_ENABLE: channel enable
1276 \arg TIMER_CCX_DISABLE: channel disable
1277 \param[out] none
1278 \retval none
1279 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1280 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1281 {
1282 switch(channel){
1283 /* configure TIMER_CH_0 */
1284 case TIMER_CH_0:
1285 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1286 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1287 break;
1288 /* configure TIMER_CH_1 */
1289 case TIMER_CH_1:
1290 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1291 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1292 break;
1293 /* configure TIMER_CH_2 */
1294 case TIMER_CH_2:
1295 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1296 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1297 break;
1298 /* configure TIMER_CH_3 */
1299 case TIMER_CH_3:
1300 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1301 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1302 break;
1303 default:
1304 break;
1305 }
1306 }
1307
1308 /*!
1309 \brief configure TIMER channel complementary output enable state
1310 \param[in] timer_periph: please refer to the following parameters
1311 \param[in] channel:
1312 only one parameter can be selected which is shown as below:
1313 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7))
1314 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7))
1315 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7))
1316 \param[in] ocnstate: TIMER channel complementary output enable state
1317 only one parameter can be selected which is shown as below:
1318 \arg TIMER_CCXN_ENABLE: channel complementary enable
1319 \arg TIMER_CCXN_DISABLE: channel complementary disable
1320 \param[out] none
1321 \retval none
1322 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1323 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1324 {
1325 switch(channel){
1326 /* configure TIMER_CH_0 */
1327 case TIMER_CH_0:
1328 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1329 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1330 break;
1331 /* configure TIMER_CH_1 */
1332 case TIMER_CH_1:
1333 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1334 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1335 break;
1336 /* configure TIMER_CH_2 */
1337 case TIMER_CH_2:
1338 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1339 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1340 break;
1341 default:
1342 break;
1343 }
1344 }
1345
1346 /*!
1347 \brief initialize TIMER channel input parameter struct with a default value
1348 \param[in] icpara: TIMER channel intput parameter struct
1349 \param[out] none
1350 \retval none
1351 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1352 void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
1353 {
1354 /* initialize the channel input parameter struct member with the default value */
1355 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1356 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1357 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1358 icpara->icfilter = 0U;
1359 }
1360
1361 /*!
1362 \brief configure TIMER input capture parameter
1363 \param[in] timer_periph: please refer to the following parameters
1364 \param[in] channel:
1365 only one parameter can be selected which is shown as below:
1366 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1367 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1368 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1369 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1370 \param[in] icpara: TIMER channel intput parameter struct
1371 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
1372 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
1373 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1374 icfilter: 0~15
1375 \param[out] none
1376 \retval none
1377 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1378 void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara)
1379 {
1380 switch(channel){
1381 /* configure TIMER_CH_0 */
1382 case TIMER_CH_0:
1383 /* reset the CH0EN bit */
1384 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1385
1386 /* reset the CH0P and CH0NP bits */
1387 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1388 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1389 /* reset the CH0MS bit */
1390 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1391 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1392 /* reset the CH0CAPFLT bit */
1393 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1394 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1395
1396 /* set the CH0EN bit */
1397 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1398 break;
1399
1400 /* configure TIMER_CH_1 */
1401 case TIMER_CH_1:
1402 /* reset the CH1EN bit */
1403 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1404
1405 /* reset the CH1P and CH1NP bits */
1406 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1407 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1408 /* reset the CH1MS bit */
1409 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1410 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1411 /* reset the CH1CAPFLT bit */
1412 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1413 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1414
1415 /* set the CH1EN bit */
1416 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1417 break;
1418 /* configure TIMER_CH_2 */
1419 case TIMER_CH_2:
1420 /* reset the CH2EN bit */
1421 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1422
1423 /* reset the CH2P and CH2NP bits */
1424 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1425 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1426
1427 /* reset the CH2MS bit */
1428 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1429 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1430
1431 /* reset the CH2CAPFLT bit */
1432 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1433 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1434
1435 /* set the CH2EN bit */
1436 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1437 break;
1438 /* configure TIMER_CH_3 */
1439 case TIMER_CH_3:
1440 /* reset the CH3EN bit */
1441 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1442
1443 /* reset the CH3P bits */
1444 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1445 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1446
1447 /* reset the CH3MS bit */
1448 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1449 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1450
1451 /* reset the CH3CAPFLT bit */
1452 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1453 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1454
1455 /* set the CH3EN bit */
1456 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1457 break;
1458 default:
1459 break;
1460 }
1461 /* configure TIMER channel input capture prescaler value */
1462 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1463 }
1464
1465 /*!
1466 \brief configure TIMER channel input capture prescaler value
1467 \param[in] timer_periph: please refer to the following parameters
1468 \param[in] channel:
1469 only one parameter can be selected which is shown as below:
1470 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1471 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1472 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1473 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1474 \param[in] prescaler: channel input capture prescaler value
1475 only one parameter can be selected which is shown as below:
1476 \arg TIMER_IC_PSC_DIV1: no prescaler
1477 \arg TIMER_IC_PSC_DIV2: divided by 2
1478 \arg TIMER_IC_PSC_DIV4: divided by 4
1479 \arg TIMER_IC_PSC_DIV8: divided by 8
1480 \param[out] none
1481 \retval none
1482 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1483 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1484 {
1485 switch(channel){
1486 /* configure TIMER_CH_0 */
1487 case TIMER_CH_0:
1488 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1489 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1490 break;
1491 /* configure TIMER_CH_1 */
1492 case TIMER_CH_1:
1493 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1494 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1495 break;
1496 /* configure TIMER_CH_2 */
1497 case TIMER_CH_2:
1498 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1499 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1500 break;
1501 /* configure TIMER_CH_3 */
1502 case TIMER_CH_3:
1503 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1504 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1505 break;
1506 default:
1507 break;
1508 }
1509 }
1510
1511 /*!
1512 \brief read TIMER channel capture compare register value
1513 \param[in] timer_periph: please refer to the following parameters
1514 \param[in] channel:
1515 only one parameter can be selected which is shown as below:
1516 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,3,7..13))
1517 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,3,7,8,11))
1518 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2,3,7))
1519 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2,3,7))
1520 \param[out] none
1521 \retval channel capture compare register value
1522 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1523 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1524 {
1525 uint32_t count_value = 0U;
1526
1527 switch(channel){
1528 /* read TIMER channel 0 capture compare register value */
1529 case TIMER_CH_0:
1530 count_value = TIMER_CH0CV(timer_periph);
1531 break;
1532 /* read TIMER channel 1 capture compare register value */
1533 case TIMER_CH_1:
1534 count_value = TIMER_CH1CV(timer_periph);
1535 break;
1536 /* read TIMER channel 2 capture compare register value */
1537 case TIMER_CH_2:
1538 count_value = TIMER_CH2CV(timer_periph);
1539 break;
1540 /* read TIMER channel 3 capture compare register value */
1541 case TIMER_CH_3:
1542 count_value = TIMER_CH3CV(timer_periph);
1543 break;
1544 default:
1545 break;
1546 }
1547 return (count_value);
1548 }
1549
1550 /*!
1551 \brief configure TIMER input pwm capture function
1552 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1553 \param[in] channel:
1554 only one parameter can be selected which is shown as below:
1555 \arg TIMER_CH_0: TIMER channel0
1556 \arg TIMER_CH_1: TIMER channel1
1557 \param[in] icpwm:TIMER channel intput pwm parameter struct
1558 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
1559 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
1560 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1561 icfilter: 0~15
1562 \param[out] none
1563 \retval none
1564 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1565 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1566 {
1567 uint16_t icpolarity = 0x0U;
1568 uint16_t icselection = 0x0U;
1569
1570 /* Set channel input polarity */
1571 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1572 icpolarity = TIMER_IC_POLARITY_FALLING;
1573 }else{
1574 icpolarity = TIMER_IC_POLARITY_RISING;
1575 }
1576
1577 /* Set channel input mode selection */
1578 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1579 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1580 }else{
1581 icselection = TIMER_IC_SELECTION_DIRECTTI;
1582 }
1583
1584 if(TIMER_CH_0 == channel){
1585 /* reset the CH0EN bit */
1586 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1587 /* reset the CH0P and CH0NP bits */
1588 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1589 /* set the CH0P and CH0NP bits */
1590 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1591 /* reset the CH0MS bit */
1592 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1593 /* set the CH0MS bit */
1594 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1595 /* reset the CH0CAPFLT bit */
1596 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1597 /* set the CH0CAPFLT bit */
1598 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1599 /* set the CH0EN bit */
1600 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1601 /* configure TIMER channel input capture prescaler value */
1602 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1603
1604 /* reset the CH1EN bit */
1605 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1606 /* reset the CH1P and CH1NP bits */
1607 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1608 /* set the CH1P and CH1NP bits */
1609 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1610 /* reset the CH1MS bit */
1611 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1612 /* set the CH1MS bit */
1613 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1614 /* reset the CH1CAPFLT bit */
1615 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1616 /* set the CH1CAPFLT bit */
1617 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1618 /* set the CH1EN bit */
1619 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1620 /* configure TIMER channel input capture prescaler value */
1621 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1622 }else{
1623 /* reset the CH1EN bit */
1624 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1625 /* reset the CH1P and CH1NP bits */
1626 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1627 /* set the CH1P and CH1NP bits */
1628 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1629 /* reset the CH1MS bit */
1630 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1631 /* set the CH1MS bit */
1632 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1633 /* reset the CH1CAPFLT bit */
1634 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1635 /* set the CH1CAPFLT bit */
1636 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1637 /* set the CH1EN bit */
1638 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1639 /* configure TIMER channel input capture prescaler value */
1640 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1641
1642 /* reset the CH0EN bit */
1643 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1644 /* reset the CH0P and CH0NP bits */
1645 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1646 /* set the CH0P and CH0NP bits */
1647 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1648 /* reset the CH0MS bit */
1649 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1650 /* set the CH0MS bit */
1651 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1652 /* reset the CH0CAPFLT bit */
1653 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1654 /* set the CH0CAPFLT bit */
1655 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1656 /* set the CH0EN bit */
1657 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1658 /* configure TIMER channel input capture prescaler value */
1659 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1660 }
1661 }
1662
1663 /*!
1664 \brief configure TIMER hall sensor mode
1665 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1666 \param[in] hallmode:
1667 only one parameter can be selected which is shown as below:
1668 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1669 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1670 \param[out] none
1671 \retval none
1672 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1673 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1674 {
1675 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1676 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1677 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1678 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1679 }else{
1680 /* illegal parameters */
1681 }
1682 }
1683
1684 /*!
1685 \brief select TIMER input trigger source
1686 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1687 \param[in] intrigger:
1688 only one parameter can be selected which is shown as below:
1689 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1690 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1691 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1692 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1693 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1694 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1695 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1696 \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(x=0,2,3,7)
1697 \param[out] none
1698 \retval none
1699 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)1700 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1701 {
1702 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1703 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1704 }
1705
1706 /*!
1707 \brief select TIMER master mode output trigger source
1708 \param[in] timer_periph: TIMERx(x=0,2,3,5..7)
1709 \param[in] outrigger:
1710 only one parameter can be selected which is shown as below:
1711 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
1712 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
1713 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
1714 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
1715 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
1716 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
1717 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
1718 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
1719 \param[out] none
1720 \retval none
1721 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)1722 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1723 {
1724 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1725 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1726 }
1727
1728 /*!
1729 \brief select TIMER slave mode
1730 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1731 \param[in] slavemode:
1732 only one parameter can be selected which is shown as below:
1733 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0,2,3,7,8,11))
1734 \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0,2,3,7))
1735 \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0,2,3,7))
1736 \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0,2,3,7))
1737 \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0,2,3,7,8,11))
1738 \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0,2,3,7,8,11))
1739 \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0,2,3,7,8,11))
1740 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
1741 \param[out] none
1742 \retval none
1743 */
1744
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)1745 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1746 {
1747 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1748
1749 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1750 }
1751
1752 /*!
1753 \brief configure TIMER master slave mode
1754 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1755 \param[in] masterslave:
1756 only one parameter can be selected which is shown as below:
1757 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
1758 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
1759 \param[out] none
1760 \retval none
1761 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)1762 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
1763 {
1764 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1765 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1766 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1767 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1768 }else{
1769 /* illegal parameters */
1770 }
1771 }
1772
1773 /*!
1774 \brief configure TIMER external trigger input
1775 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1776 \param[in] extprescaler:
1777 only one parameter can be selected which is shown as below:
1778 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1779 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1780 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1781 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1782 \param[in] extpolarity:
1783 only one parameter can be selected which is shown as below:
1784 \arg TIMER_ETP_FALLING: active low or falling edge active
1785 \arg TIMER_ETP_RISING: active high or rising edge active
1786 \param[in] extfilter: a value between 0 and 15
1787 \param[out] none
1788 \retval none
1789 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1790 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
1791 uint32_t extpolarity, uint32_t extfilter)
1792 {
1793 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1794 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
1795 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1796 }
1797
1798 /*!
1799 \brief configure TIMER quadrature decoder mode
1800 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1801 \param[in] decomode:
1802 only one parameter can be selected which is shown as below:
1803 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
1804 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
1805 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
1806 \param[in] ic0polarity:
1807 only one parameter can be selected which is shown as below:
1808 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1809 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1810 \param[in] ic1polarity:
1811 only one parameter can be selected which is shown as below:
1812 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1813 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1814 \param[out] none
1815 \retval none
1816 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)1817 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode,
1818 uint16_t ic0polarity, uint16_t ic1polarity)
1819 {
1820 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1821 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1822
1823 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1824 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1825
1826 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1827 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1828 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U));
1829 }
1830
1831 /*!
1832 \brief configure TIMER internal clock mode
1833 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1834 \param[out] none
1835 \retval none
1836 */
timer_internal_clock_config(uint32_t timer_periph)1837 void timer_internal_clock_config(uint32_t timer_periph)
1838 {
1839 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1840 }
1841
1842 /*!
1843 \brief configure TIMER the internal trigger as external clock input
1844 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1845 \param[in] intrigger:
1846 only one parameter can be selected which is shown as below:
1847 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1848 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1849 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1850 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1851 \param[out] none
1852 \retval none
1853 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)1854 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1855 {
1856 timer_input_trigger_source_select(timer_periph, intrigger);
1857 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1858 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1859 }
1860
1861 /*!
1862 \brief configure TIMER the external trigger as external clock input
1863 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1864 \param[in] extrigger:
1865 only one parameter can be selected which is shown as below:
1866 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1867 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1868 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1869 \param[in] extpolarity:
1870 only one parameter can be selected which is shown as below:
1871 \arg TIMER_IC_POLARITY_RISING: active high or rising edge active
1872 \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active
1873 \param[in] extfilter: a value between 0 and 15
1874 \param[out] none
1875 \retval none
1876 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)1877 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger,
1878 uint16_t extpolarity, uint32_t extfilter)
1879 {
1880 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1881 /* reset the CH1EN bit */
1882 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1883 /* reset the CH1NP bit */
1884 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1885 /* set the CH1NP bit */
1886 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
1887 /* reset the CH1MS bit */
1888 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1889 /* set the CH1MS bit */
1890 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1891 /* reset the CH1CAPFLT bit */
1892 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1893 /* set the CH1CAPFLT bit */
1894 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
1895 /* set the CH1EN bit */
1896 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1897 }else{
1898 /* reset the CH0EN bit */
1899 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1900 /* reset the CH0P and CH0NP bits */
1901 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1902 /* set the CH0P and CH0NP bits */
1903 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
1904 /* reset the CH0MS bit */
1905 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1906 /* set the CH0MS bit */
1907 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1908 /* reset the CH0CAPFLT bit */
1909 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1910 /* reset the CH0CAPFLT bit */
1911 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
1912 /* set the CH0EN bit */
1913 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1914 }
1915 /* select TIMER input trigger source */
1916 timer_input_trigger_source_select(timer_periph,extrigger);
1917 /* reset the SMC bit */
1918 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1919 /* set the SMC bit */
1920 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1921 }
1922
1923 /*!
1924 \brief configure TIMER the external clock mode0
1925 \param[in] timer_periph: TIMERx(x=0,2,3,7,8,11)
1926 \param[in] extprescaler:
1927 only one parameter can be selected which is shown as below:
1928 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1929 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1930 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1931 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1932 \param[in] extpolarity:
1933 only one parameter can be selected which is shown as below:
1934 \arg TIMER_ETP_FALLING: active low or falling edge active
1935 \arg TIMER_ETP_RISING: active high or rising edge active
1936 \param[in] extfilter: a value between 0 and 15
1937 \param[out] none
1938 \retval none
1939 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1940 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler,
1941 uint32_t extpolarity, uint32_t extfilter)
1942 {
1943 /* configure TIMER external trigger input */
1944 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1945
1946 /* reset the SMC bit,TRGS bit */
1947 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1948 /* set the SMC bit,TRGS bit */
1949 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1950 }
1951
1952 /*!
1953 \brief configure TIMER the external clock mode1
1954 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1955 \param[in] extprescaler:
1956 only one parameter can be selected which is shown as below:
1957 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1958 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1959 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1960 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1961 \param[in] extpolarity:
1962 only one parameter can be selected which is shown as below:
1963 \arg TIMER_ETP_FALLING: active low or falling edge active
1964 \arg TIMER_ETP_RISING: active high or rising edge active
1965 \param[in] extfilter: a value between 0 and 15
1966 \param[out] none
1967 \retval none
1968 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1969 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
1970 uint32_t extpolarity, uint32_t extfilter)
1971 {
1972 /* configure TIMER external trigger input */
1973 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1974
1975 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1976 }
1977
1978 /*!
1979 \brief disable TIMER the external clock mode1
1980 \param[in] timer_periph: TIMERx(x=0,2,3,7)
1981 \param[out] none
1982 \retval none
1983 */
timer_external_clock_mode1_disable(uint32_t timer_periph)1984 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1985 {
1986 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1987 }
1988
1989 /*!
1990 \brief configure TIMER write CHxVAL register selection
1991 \param[in] timer_periph: TIMERx(x=0,2,3,7..13)
1992 \param[in] ccsel:
1993 only one parameter can be selected which is shown as below:
1994 \arg TIMER_CHVSEL_DISABLE: no effect
1995 \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
1996 \param[out] none
1997 \retval none
1998 */
timer_write_chxval_register_config(uint32_t timer_periph,uint16_t ccsel)1999 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel)
2000 {
2001 if(TIMER_CHVSEL_ENABLE == ccsel){
2002 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
2003 }else if(TIMER_CHVSEL_DISABLE == ccsel){
2004 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
2005 }else{
2006 /* illegal parameters */
2007 }
2008 }
2009
2010 /*!
2011 \brief configure TIMER output value selection
2012 \param[in] timer_periph: TIMERx(x=0,7)
2013 \param[in] outsel:
2014 only one parameter can be selected which is shown as below:
2015 \arg TIMER_OUTSEL_DISABLE: no effect
2016 \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
2017 \param[out] none
2018 \retval none
2019 */
timer_output_value_selection_config(uint32_t timer_periph,uint16_t outsel)2020 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
2021 {
2022 if(TIMER_OUTSEL_ENABLE == outsel){
2023 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
2024 }else if(TIMER_OUTSEL_DISABLE == outsel){
2025 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
2026 }else{
2027 /* illegal parameters */
2028 }
2029 }
2030
