| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | gdma_ll.h | 71 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status() argument
73 return dev->channel[channel].in.int_st.val; in gdma_ll_rx_get_interrupt_status()
79 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo… in gdma_ll_rx_enable_interrupt() argument
82 dev->channel[channel].in.int_ena.val |= mask; in gdma_ll_rx_enable_interrupt()
84 dev->channel[channel].in.int_ena.val &= ~mask; in gdma_ll_rx_enable_interrupt()
92 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma… in gdma_ll_rx_clear_interrupt_status() argument
94 dev->channel[channel].in.int_clr.val = mask; in gdma_ll_rx_clear_interrupt_status()
100 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status_reg() argument
102 return (volatile void *)(&dev->channel[channel].in.int_st); in gdma_ll_rx_get_interrupt_status_reg()
108 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) in gdma_ll_rx_enable_owner_check() argument
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| D | rmt_ll.h | 25 #define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) argument
26 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) argument
27 #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) argument
28 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) argument
29 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 16)) argument
30 #define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 24)) argument
31 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 20)) argument
32 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
33 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
110 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
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| D | sdm_ll.h | 38 static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) in sdm_ll_set_pulse_density() argument
40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
50 static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) in sdm_ll_set_prescale() argument
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | gdma_ll.h | 58 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status() argument
60 return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; in gdma_ll_rx_get_interrupt_status()
66 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo… in gdma_ll_rx_enable_interrupt() argument
69 dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
71 dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
79 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma… in gdma_ll_rx_clear_interrupt_status() argument
81 dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_clear_interrupt_status()
87 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status_reg() argument
89 return (volatile void *)(&dev->intr[channel].st); in gdma_ll_rx_get_interrupt_status_reg()
95 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) in gdma_ll_rx_enable_owner_check() argument
[all …]
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | gdma_ll.h | 58 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status() argument
60 return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; in gdma_ll_rx_get_interrupt_status()
66 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo… in gdma_ll_rx_enable_interrupt() argument
69 dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
71 dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
79 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma… in gdma_ll_rx_clear_interrupt_status() argument
81 dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_clear_interrupt_status()
87 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status_reg() argument
89 return (volatile void *)(&dev->intr[channel].st); in gdma_ll_rx_get_interrupt_status_reg()
95 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) in gdma_ll_rx_enable_owner_check() argument
[all …]
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| D | rmt_ll.h | 25 #define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) argument
26 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) argument
27 #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) argument
28 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) argument
29 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2)) argument
30 #define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10)) argument
31 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6)) argument
32 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
33 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
110 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
[all …]
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| D | sdm_ll.h | 38 static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) in sdm_ll_set_pulse_density() argument
40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
50 static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) in sdm_ll_set_prescale() argument
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | gdma_ll.h | 105 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status() argument
107 return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; in gdma_ll_rx_get_interrupt_status()
113 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo… in gdma_ll_rx_enable_interrupt() argument
116 dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
118 dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
126 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma… in gdma_ll_rx_clear_interrupt_status() argument
128 dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_clear_interrupt_status()
134 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status_reg() argument
136 return (volatile void *)(&dev->in_intr[channel].st); in gdma_ll_rx_get_interrupt_status_reg()
142 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) in gdma_ll_rx_enable_owner_check() argument
[all …]
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| D | rmt_ll.h | 26 #define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) argument
27 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) argument
28 #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) argument
29 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) argument
30 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2)) argument
31 #define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10)) argument
32 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6)) argument
33 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
34 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
111 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
[all …]
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| D | sdm_ll.h | 38 static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) in sdm_ll_set_pulse_density() argument
40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
50 static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) in sdm_ll_set_prescale() argument
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | gdma_ll.h | 105 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status() argument
107 return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; in gdma_ll_rx_get_interrupt_status()
113 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo… in gdma_ll_rx_enable_interrupt() argument
116 dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
118 dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_enable_interrupt()
126 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma… in gdma_ll_rx_clear_interrupt_status() argument
128 dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); in gdma_ll_rx_clear_interrupt_status()
134 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) in gdma_ll_rx_get_interrupt_status_reg() argument
136 return (volatile void *)(&dev->in_intr[channel].st); in gdma_ll_rx_get_interrupt_status_reg()
142 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) in gdma_ll_rx_enable_owner_check() argument
[all …]
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| D | rmt_ll.h | 26 #define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) argument
27 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) argument
28 #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) argument
29 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) argument
30 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2)) argument
31 #define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10)) argument
32 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6)) argument
33 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
34 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
111 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
[all …]
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| /hal_espressif-latest/components/driver/deprecated/ |
| D | rmt_legacy.c | 56 #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START) argument
57 #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END) argument
79 rmt_channel_t channel; member
146 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt) in rmt_set_clk_div() argument
148 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); in rmt_set_clk_div()
150 if (RMT_IS_RX_CHANNEL(channel)) { in rmt_set_clk_div()
151 … rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); in rmt_set_clk_div()
153 rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt); in rmt_set_clk_div()
159 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt) in rmt_get_clk_div() argument
161 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); in rmt_get_clk_div()
[all …]
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| D | dac_common_legacy.c | 29 esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num) in dac_pad_get_io_num() argument
31 ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error"); in dac_pad_get_io_num()
33 *gpio_num = (gpio_num_t)dac_periph_signal.dac_channel_io_num[channel]; in dac_pad_get_io_num()
38 static esp_err_t dac_rtc_pad_init(dac_channel_t channel) in dac_rtc_pad_init() argument
40 ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error"); in dac_rtc_pad_init()
43 dac_pad_get_io_num(channel, &gpio_num); in dac_rtc_pad_init()
52 esp_err_t dac_output_enable(dac_channel_t channel) in dac_output_enable() argument
54 ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error"); in dac_output_enable()
56 dac_rtc_pad_init(channel); in dac_output_enable()
58 dac_ll_power_on(channel); in dac_output_enable()
[all …]
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| D | adc_legacy.c | 43 #define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel]) argument
106 static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src_freq_hz, int *out_…
111 esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num) in adc1_pad_get_io_num() argument
113 …ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "inva… in adc1_pad_get_io_num()
115 int io = ADC_GET_IO_NUM(ADC_UNIT_1, channel); in adc1_pad_get_io_num()
126 esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num) in adc2_pad_get_io_num() argument
128 …ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "inva… in adc2_pad_get_io_num()
130 int io = ADC_GET_IO_NUM(ADC_UNIT_2, channel); in adc2_pad_get_io_num()
173 esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel) in adc_common_gpio_init() argument
175 …ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(adc_unit), ESP_ERR_INVALID_ARG, ADC_TAG, "invali… in adc_common_gpio_init()
[all …]
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| D | sigma_delta_legacy.c | 34 … _sigmadelta_set_duty(sigmadelta_port_t sigmadelta_port, sigmadelta_channel_t channel, int8_t duty) in _sigmadelta_set_duty() argument
38 sdm_ll_set_pulse_density(p_sigmadelta_obj[sigmadelta_port]->hal.dev, channel, duty); in _sigmadelta_set_duty()
42 …lta_set_prescale(sigmadelta_port_t sigmadelta_port, sigmadelta_channel_t channel, uint8_t prescale) in _sigmadelta_set_prescale() argument
46 sdm_ll_set_prescale(p_sigmadelta_obj[sigmadelta_port]->hal.dev, channel, prescale + 1); in _sigmadelta_set_prescale()
50 …gmadelta_set_pin(sigmadelta_port_t sigmadelta_port, sigmadelta_channel_t channel, gpio_num_t gpio_… in _sigmadelta_set_pin() argument
56 …esp_rom_gpio_connect_out_signal(gpio_num, sigma_delta_periph_signals.channels[channel].sd_sig, 0, … in _sigmadelta_set_pin()
64 _sigmadelta_set_duty(sigmadelta_port, config->channel, config->sigmadelta_duty); in _sigmadelta_config()
65 _sigmadelta_set_prescale(sigmadelta_port, config->channel, config->sigmadelta_prescale); in _sigmadelta_config()
66 _sigmadelta_set_pin(sigmadelta_port, config->channel, config->sigmadelta_gpio); in _sigmadelta_config()
98 esp_err_t sigmadelta_set_duty(sigmadelta_channel_t channel, int8_t duty) in sigmadelta_set_duty() argument
[all …]
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | rmt_ll.h | 26 #define RMT_LL_EVENT_TX_DONE(channel) (1 << ((channel) * 3)) argument
27 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 12)) argument
28 #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 16)) argument
29 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) * 3 + 2)) argument
30 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) * 3 + 1)) argument
31 #define RMT_LL_EVENT_RX_THRES(channel) (0) // esp32s2 doesn't support rx wrap argument
32 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) * 3 + 2)) argument
33 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
34 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
111 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
[all …]
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| D | dac_ll.h | 40 static inline void dac_ll_power_on(dac_channel_t channel) in dac_ll_power_on() argument
43 RTCIO.pad_dac[channel].dac_xpd_force = 1; in dac_ll_power_on()
44 RTCIO.pad_dac[channel].xpd_dac = 1; in dac_ll_power_on()
52 static inline void dac_ll_power_down(dac_channel_t channel) in dac_ll_power_down() argument
54 RTCIO.pad_dac[channel].dac_xpd_force = 0; in dac_ll_power_down()
55 RTCIO.pad_dac[channel].xpd_dac = 0; in dac_ll_power_down()
72 static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value) in dac_ll_update_output_value() argument
74 if (channel == DAC_CHAN_0) { in dac_ll_update_output_value()
76 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
77 } else if (channel == DAC_CHAN_1) { in dac_ll_update_output_value()
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| D | dedic_gpio_ll.h | 48 static inline void dedic_gpio_ll_set_channel(dedic_dev_t *dev, uint32_t channel) in dedic_gpio_ll_set_channel() argument
50 dev->gpio_out_idv.val = 1 << (2 * channel); in dedic_gpio_ll_set_channel()
53 static inline void dedic_gpio_ll_clear_channel(dedic_dev_t *dev, uint32_t channel) in dedic_gpio_ll_clear_channel() argument
55 dev->gpio_out_idv.val = 2 << (2 * channel); in dedic_gpio_ll_clear_channel()
58 static inline void dedic_gpio_ll_toggle_channel(dedic_dev_t *dev, uint32_t channel) in dedic_gpio_ll_toggle_channel() argument
60 dev->gpio_out_idv.val = 3 << (2 * channel); in dedic_gpio_ll_toggle_channel()
73 static inline void dedic_gpio_ll_set_input_delay(dedic_dev_t *dev, uint32_t channel, uint32_t delay… in dedic_gpio_ll_set_input_delay() argument
75 dev->gpio_in_dly.val &= ~(3 << (2 * channel)); in dedic_gpio_ll_set_input_delay()
76 dev->gpio_in_dly.val |= (delay_cpu_clks & 0x03) << (2 * channel); in dedic_gpio_ll_set_input_delay()
79 static inline uint32_t dedic_gpio_ll_get_input_delay(dedic_dev_t *dev, uint32_t channel) in dedic_gpio_ll_get_input_delay() argument
[all …]
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| D | sdm_ll.h | 38 static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) in sdm_ll_set_pulse_density() argument
40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
50 static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) in sdm_ll_set_prescale() argument
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
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| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | rmt_ll.h | 25 #define RMT_LL_EVENT_TX_DONE(channel) (1 << ((channel) * 3)) argument
26 #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 24)) argument
27 #define RMT_LL_EVENT_TX_LOOP_END(channel) (0) // esp32 doesn't support tx loop count argument
28 #define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) * 3 + 2)) argument
29 #define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) * 3 + 1)) argument
30 #define RMT_LL_EVENT_RX_THRES(channel) (0) // esp32 doesn't support rx wrap argument
31 #define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) * 3 + 2)) argument
32 …RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) … argument
33 #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(ch… argument
105 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t … in rmt_ll_set_group_clock_src() argument
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| D | dac_ll.h | 35 static inline void dac_ll_power_on(dac_channel_t channel) in dac_ll_power_on() argument
37 RTCIO.pad_dac[channel].dac_xpd_force = 1; in dac_ll_power_on()
38 RTCIO.pad_dac[channel].xpd_dac = 1; in dac_ll_power_on()
46 static inline void dac_ll_power_down(dac_channel_t channel) in dac_ll_power_down() argument
48 RTCIO.pad_dac[channel].dac_xpd_force = 0; in dac_ll_power_down()
49 RTCIO.pad_dac[channel].xpd_dac = 0; in dac_ll_power_down()
60 static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value) in dac_ll_update_output_value() argument
62 if (channel == DAC_CHAN_0) { in dac_ll_update_output_value()
64 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
65 } else if (channel == DAC_CHAN_1) { in dac_ll_update_output_value()
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| D | sdm_ll.h | 38 static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) in sdm_ll_set_pulse_density() argument
40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
50 static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) in sdm_ll_set_prescale() argument
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
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| /hal_espressif-latest/components/driver/deprecated/driver/ |
| D | rmt.h | 35 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt);
47 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt);
63 esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh);
79 esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh);
106 esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num);
118 esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num);
138 esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t …
152 esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en);
164 esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en);
177 esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst);
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| /hal_espressif-latest/components/hal/ |
| D | rmt_hal.c | 32 void rmt_hal_tx_channel_reset(rmt_hal_context_t *hal, uint32_t channel) in rmt_hal_tx_channel_reset() argument
34 rmt_ll_tx_reset_channels_clock_div(hal->regs, 1 << channel); in rmt_hal_tx_channel_reset()
35 rmt_ll_tx_reset_pointer(hal->regs, channel); in rmt_hal_tx_channel_reset()
37 rmt_ll_tx_reset_loop_count(hal->regs, channel); in rmt_hal_tx_channel_reset()
39 rmt_ll_enable_interrupt(hal->regs, RMT_LL_EVENT_TX_MASK(channel), false); in rmt_hal_tx_channel_reset()
40 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_MASK(channel)); in rmt_hal_tx_channel_reset()
43 void rmt_hal_rx_channel_reset(rmt_hal_context_t *hal, uint32_t channel) in rmt_hal_rx_channel_reset() argument
45 rmt_ll_rx_reset_channels_clock_div(hal->regs, 1 << channel); in rmt_hal_rx_channel_reset()
46 rmt_ll_rx_reset_pointer(hal->regs, channel); in rmt_hal_rx_channel_reset()
47 rmt_ll_enable_interrupt(hal->regs, RMT_LL_EVENT_RX_MASK(channel), false); in rmt_hal_rx_channel_reset()
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