58 static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_get_interrupt_status()  argument
60     return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;  in gdma_ll_rx_get_interrupt_status()
66 static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo…  in gdma_ll_rx_enable_interrupt()  argument
69         dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);  in gdma_ll_rx_enable_interrupt()
71         dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);  in gdma_ll_rx_enable_interrupt()
79 static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma…  in gdma_ll_rx_clear_interrupt_status()  argument
81     dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);  in gdma_ll_rx_clear_interrupt_status()
87 static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_get_interrupt_status_reg()  argument
89     return (volatile void *)(&dev->intr[channel].st);  in gdma_ll_rx_get_interrupt_status_reg()
95 static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_rx_enable_owner_check()  argument
97     dev->channel[channel].in.in_conf1.in_check_owner = enable;  in gdma_ll_rx_enable_owner_check()
103 static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_rx_enable_data_burst()  argument
105     dev->channel[channel].in.in_conf0.in_data_burst_en = enable;  in gdma_ll_rx_enable_data_burst()
111 static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enabl…  in gdma_ll_rx_enable_descriptor_burst()  argument
113     dev->channel[channel].in.in_conf0.indscr_burst_en = enable;  in gdma_ll_rx_enable_descriptor_burst()
120 static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_reset_channel()  argument
122     dev->channel[channel].in.in_conf0.in_rst = 1;  in gdma_ll_rx_reset_channel()
123     dev->channel[channel].in.in_conf0.in_rst = 0;  in gdma_ll_rx_reset_channel()
130 static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)  in gdma_ll_rx_is_fifo_full()  argument
132     return dev->channel[channel].in.infifo_status.val & 0x01;  in gdma_ll_rx_is_fifo_full()
139 static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)  in gdma_ll_rx_is_fifo_empty()  argument
141     return dev->channel[channel].in.infifo_status.val & 0x02;  in gdma_ll_rx_is_fifo_empty()
148 static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_l…  in gdma_ll_rx_get_fifo_bytes()  argument
150     return dev->channel[channel].in.infifo_status.infifo_cnt;  in gdma_ll_rx_get_fifo_bytes()
156 static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_pop_data()  argument
158     dev->channel[channel].in.in_pop.infifo_pop = 1;  in gdma_ll_rx_pop_data()
159     return dev->channel[channel].in.in_pop.infifo_rdata;  in gdma_ll_rx_pop_data()
166 static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)  in gdma_ll_rx_set_desc_addr()  argument
168     dev->channel[channel].in.in_link.addr = addr;  in gdma_ll_rx_set_desc_addr()
175 static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_start()  argument
177     dev->channel[channel].in.in_link.start = 1;  in gdma_ll_rx_start()
184 static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_stop()  argument
186     dev->channel[channel].in.in_link.stop = 1;  in gdma_ll_rx_stop()
193 static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_restart()  argument
195     dev->channel[channel].in.in_link.restart = 1;  in gdma_ll_rx_restart()
201 static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_rx_enable_auto_return()  argument
203     dev->channel[channel].in.in_link.auto_ret = enable;  in gdma_ll_rx_enable_auto_return()
209 static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_is_fsm_idle()  argument
211     return dev->channel[channel].in.in_link.park;  in gdma_ll_rx_is_fsm_idle()
218 static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_get_success_eof_desc_addr()  argument
220     return dev->channel[channel].in.in_suc_eof_des_addr;  in gdma_ll_rx_get_success_eof_desc_addr()
227 static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_get_error_eof_desc_addr()  argument
229     return dev->channel[channel].in.in_err_eof_des_addr;  in gdma_ll_rx_get_error_eof_desc_addr()
236 static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_get_current_desc_addr()  argument
238     return dev->channel[channel].in.in_dscr;  in gdma_ll_rx_get_current_desc_addr()
244 static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)  in gdma_ll_rx_set_priority()  argument
246     dev->channel[channel].in.in_pri.rx_pri = prio;  in gdma_ll_rx_set_priority()
252 static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_per…  in gdma_ll_rx_connect_to_periph()  argument
254     dev->channel[channel].in.in_peri_sel.sel = periph_id;  in gdma_ll_rx_connect_to_periph()
255     dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);  in gdma_ll_rx_connect_to_periph()
261 static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_rx_disconnect_from_periph()  argument
263     dev->channel[channel].in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;  in gdma_ll_rx_disconnect_from_periph()
264     dev->channel[channel].in.in_conf0.mem_trans_en = false;  in gdma_ll_rx_disconnect_from_periph()
272 static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_get_interrupt_status()  argument
274     return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;  in gdma_ll_tx_get_interrupt_status()
280 static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bo…  in gdma_ll_tx_enable_interrupt()  argument
283         dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);  in gdma_ll_tx_enable_interrupt()
285         dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);  in gdma_ll_tx_enable_interrupt()
293 static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t ma…  in gdma_ll_tx_clear_interrupt_status()  argument
295     dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);  in gdma_ll_tx_clear_interrupt_status()
301 static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_get_interrupt_status_reg()  argument
303     return (volatile void *)(&dev->intr[channel].st);  in gdma_ll_tx_get_interrupt_status_reg()
309 static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_tx_enable_owner_check()  argument
311     dev->channel[channel].out.out_conf1.out_check_owner = enable;  in gdma_ll_tx_enable_owner_check()
317 static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_tx_enable_data_burst()  argument
319     dev->channel[channel].out.out_conf0.out_data_burst_en = enable;  in gdma_ll_tx_enable_data_burst()
325 static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enabl…  in gdma_ll_tx_enable_descriptor_burst()  argument
327     dev->channel[channel].out.out_conf0.outdscr_burst_en = enable;  in gdma_ll_tx_enable_descriptor_burst()
333 static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)  in gdma_ll_tx_set_eof_mode()  argument
335     dev->channel[channel].out.out_conf0.out_eof_mode = mode;  in gdma_ll_tx_set_eof_mode()
341 static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)  in gdma_ll_tx_enable_auto_write_back()  argument
343     dev->channel[channel].out.out_conf0.out_auto_wrback = enable;  in gdma_ll_tx_enable_auto_write_back()
350 static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_reset_channel()  argument
352     dev->channel[channel].out.out_conf0.out_rst = 1;  in gdma_ll_tx_reset_channel()
353     dev->channel[channel].out.out_conf0.out_rst = 0;  in gdma_ll_tx_reset_channel()
360 static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)  in gdma_ll_tx_is_fifo_full()  argument
362     return dev->channel[channel].out.outfifo_status.val & 0x01;  in gdma_ll_tx_is_fifo_full()
369 static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)  in gdma_ll_tx_is_fifo_empty()  argument
371     return dev->channel[channel].out.outfifo_status.val & 0x02;  in gdma_ll_tx_is_fifo_empty()
378 static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_l…  in gdma_ll_tx_get_fifo_bytes()  argument
380     return dev->channel[channel].out.outfifo_status.outfifo_cnt;  in gdma_ll_tx_get_fifo_bytes()
386 static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)  in gdma_ll_tx_push_data()  argument
388     dev->channel[channel].out.out_push.outfifo_wdata = data;  in gdma_ll_tx_push_data()
389     dev->channel[channel].out.out_push.outfifo_push = 1;  in gdma_ll_tx_push_data()
396 static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)  in gdma_ll_tx_set_desc_addr()  argument
398     dev->channel[channel].out.out_link.addr = addr;  in gdma_ll_tx_set_desc_addr()
405 static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_start()  argument
407     dev->channel[channel].out.out_link.start = 1;  in gdma_ll_tx_start()
414 static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_stop()  argument
416     dev->channel[channel].out.out_link.stop = 1;  in gdma_ll_tx_stop()
423 static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_restart()  argument
425     dev->channel[channel].out.out_link.restart = 1;  in gdma_ll_tx_restart()
431 static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_is_fsm_idle()  argument
433     return dev->channel[channel].out.out_link.park;  in gdma_ll_tx_is_fsm_idle()
440 static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_get_eof_desc_addr()  argument
442     return dev->channel[channel].out.out_eof_des_addr;  in gdma_ll_tx_get_eof_desc_addr()
449 static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_get_current_desc_addr()  argument
451     return dev->channel[channel].out.out_dscr;  in gdma_ll_tx_get_current_desc_addr()
457 static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)  in gdma_ll_tx_set_priority()  argument
459     dev->channel[channel].out.out_pri.tx_pri = prio;  in gdma_ll_tx_set_priority()
465 static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_per…  in gdma_ll_tx_connect_to_periph()  argument
468     dev->channel[channel].out.out_peri_sel.sel = periph_id;  in gdma_ll_tx_connect_to_periph()
474 static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)  in gdma_ll_tx_disconnect_from_periph()  argument
476     dev->channel[channel].out.out_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;  in gdma_ll_tx_disconnect_from_periph()