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Searched refs:SPI_MEM_SRAM_DWR_CMD_REG (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32s3/
Desp_psram_impl_quad.c401 …SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CA… in config_psram_spi_phases()
402 …SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRI… in config_psram_spi_phases()
Desp_psram_impl_octal.c353 …SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, OCT_PSRAM_WR_… in s_config_psram_spi_phases()
354 …SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, OPI_PSRAM_SYNC… in s_config_psram_spi_phases()
/hal_espressif-latest/components/esp_psram/esp32s2/
Desp_psram_impl_quad.c522 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, in psram_cache_init()
524 …SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRI… in psram_cache_init()
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_mem_reg.h832 #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x04C) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_mem_reg.h842 #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dspi_mem_reg.h1001 #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dspi_mem_reg.h996 #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) macro