1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** SPI_MEM_CMD_REG register 16 * SPI0 FSM status register 17 * SPI1 memory command register 18 */ 19 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) 20 /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ 21 /*description: Read flash enable. Read flash operation will be triggered when the bit is set. T 22 he bit will be cleared once the operation done. 1: enable 0: disable..*/ 23 #define SPI_MEM_FLASH_READ (BIT(31)) 24 #define SPI_MEM_FLASH_READ_M (BIT(31)) 25 #define SPI_MEM_FLASH_READ_V 0x1 26 #define SPI_MEM_FLASH_READ_S 31 27 /* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ 28 /*description: Write flash enable. Write enable command will be sent when the bit is set. The 29 bit will be cleared once the operation done. 1: enable 0: disable..*/ 30 #define SPI_MEM_FLASH_WREN (BIT(30)) 31 #define SPI_MEM_FLASH_WREN_M (BIT(30)) 32 #define SPI_MEM_FLASH_WREN_V 0x1 33 #define SPI_MEM_FLASH_WREN_S 30 34 /* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ 35 /*description: Write flash disable. Write disable command will be sent when the bit is set. The 36 bit will be cleared once the operation done. 1: enable 0: disable..*/ 37 #define SPI_MEM_FLASH_WRDI (BIT(29)) 38 #define SPI_MEM_FLASH_WRDI_M (BIT(29)) 39 #define SPI_MEM_FLASH_WRDI_V 0x1 40 #define SPI_MEM_FLASH_WRDI_S 29 41 /* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ 42 /*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b 43 e cleared once the operation done. 1: enable 0: disable..*/ 44 #define SPI_MEM_FLASH_RDID (BIT(28)) 45 #define SPI_MEM_FLASH_RDID_M (BIT(28)) 46 #define SPI_MEM_FLASH_RDID_V 0x1 47 #define SPI_MEM_FLASH_RDID_S 28 48 /* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ 49 /*description: Read status register-1. Read status operation will be triggered when the bit is 50 set. The bit will be cleared once the operation done.1: enable 0: disable..*/ 51 #define SPI_MEM_FLASH_RDSR (BIT(27)) 52 #define SPI_MEM_FLASH_RDSR_M (BIT(27)) 53 #define SPI_MEM_FLASH_RDSR_V 0x1 54 #define SPI_MEM_FLASH_RDSR_S 27 55 /* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ 56 /*description: Write status register enable. Write status operation will be triggered when t 57 he bit is set. The bit will be cleared once the operation done.1: enable 0: disa 58 ble..*/ 59 #define SPI_MEM_FLASH_WRSR (BIT(26)) 60 #define SPI_MEM_FLASH_WRSR_M (BIT(26)) 61 #define SPI_MEM_FLASH_WRSR_V 0x1 62 #define SPI_MEM_FLASH_WRSR_S 26 63 /* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ 64 /*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera 65 tion will be triggered when the bit is set. The bit will be cleared once the op 66 eration done .1: enable 0: disable..*/ 67 #define SPI_MEM_FLASH_PP (BIT(25)) 68 #define SPI_MEM_FLASH_PP_M (BIT(25)) 69 #define SPI_MEM_FLASH_PP_V 0x1 70 #define SPI_MEM_FLASH_PP_S 25 71 /* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ 72 /*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit 73 is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ 74 #define SPI_MEM_FLASH_SE (BIT(24)) 75 #define SPI_MEM_FLASH_SE_M (BIT(24)) 76 #define SPI_MEM_FLASH_SE_V 0x1 77 #define SPI_MEM_FLASH_SE_S 24 78 /* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ 79 /*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit 80 is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ 81 #define SPI_MEM_FLASH_BE (BIT(23)) 82 #define SPI_MEM_FLASH_BE_M (BIT(23)) 83 #define SPI_MEM_FLASH_BE_V 0x1 84 #define SPI_MEM_FLASH_BE_S 23 85 /* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ 86 /*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T 87 he bit will be cleared once the operation done.1: enable 0: disable..*/ 88 #define SPI_MEM_FLASH_CE (BIT(22)) 89 #define SPI_MEM_FLASH_CE_M (BIT(22)) 90 #define SPI_MEM_FLASH_CE_V 0x1 91 #define SPI_MEM_FLASH_CE_S 22 92 /* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ 93 /*description: Drive Flash into power down. An operation will be triggered when the bit is set 94 . The bit will be cleared once the operation done.1: enable 0: disable..*/ 95 #define SPI_MEM_FLASH_DP (BIT(21)) 96 #define SPI_MEM_FLASH_DP_M (BIT(21)) 97 #define SPI_MEM_FLASH_DP_V 0x1 98 #define SPI_MEM_FLASH_DP_S 21 99 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ 100 /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat 101 e or high performance mode and obtains the devices ID. The bit will be cleared o 102 nce the operation done.1: enable 0: disable..*/ 103 #define SPI_MEM_FLASH_RES (BIT(20)) 104 #define SPI_MEM_FLASH_RES_M (BIT(20)) 105 #define SPI_MEM_FLASH_RES_V 0x1 106 #define SPI_MEM_FLASH_RES_S 20 107 /* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ 108 /*description: Drive Flash into high performance mode. The bit will be cleared once the operat 109 ion done.1: enable 0: disable..*/ 110 #define SPI_MEM_FLASH_HPM (BIT(19)) 111 #define SPI_MEM_FLASH_HPM_M (BIT(19)) 112 #define SPI_MEM_FLASH_HPM_V 0x1 113 #define SPI_MEM_FLASH_HPM_S 19 114 /* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ 115 /*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat 116 ion will be triggered when the bit is set. The bit will be cleared once the oper 117 ation done.1: enable 0: disable..*/ 118 #define SPI_MEM_USR (BIT(18)) 119 #define SPI_MEM_USR_M (BIT(18)) 120 #define SPI_MEM_USR_V 0x1 121 #define SPI_MEM_USR_S 18 122 /* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ 123 /*description: In user mode, it is set to indicate that program/erase operation will be trigger 124 ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o 125 peration done.1: enable 0: disable..*/ 126 #define SPI_MEM_FLASH_PE (BIT(17)) 127 #define SPI_MEM_FLASH_PE_M (BIT(17)) 128 #define SPI_MEM_FLASH_PE_V 0x1 129 #define SPI_MEM_FLASH_PE_S 17 130 /* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ 131 /*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta 132 te, 2: send command state, 3: send address state, 4: wait state, 5: read data st 133 ate, 6:write data state, 7: done state, 8: read data end state..*/ 134 #define SPI_MEM_SLV_ST 0x0000000F 135 #define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) 136 #define SPI_MEM_SLV_ST_V 0xF 137 #define SPI_MEM_SLV_ST_S 4 138 /* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 139 /*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT 140 , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se 141 nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ 142 #define SPI_MEM_MST_ST 0x0000000F 143 #define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) 144 #define SPI_MEM_MST_ST_V 0xF 145 #define SPI_MEM_MST_ST_S 0 146 147 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) 148 /* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 149 /*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory 150 address, the bit24-bit31 are the byte length of a transfer..*/ 151 #define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF 152 #define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) 153 #define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF 154 #define SPI_MEM_USR_ADDR_VALUE_S 0 155 156 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) 157 /* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ 158 /*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a 159 lways 1. 0: Others..*/ 160 #define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) 161 #define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) 162 #define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 163 #define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 164 /* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ 165 /*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway 166 s 1. 0: Others..*/ 167 #define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) 168 #define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) 169 #define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 170 #define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 171 /* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ 172 /*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena 173 ble 0: disable..*/ 174 #define SPI_MEM_FREAD_QIO (BIT(24)) 175 #define SPI_MEM_FREAD_QIO_M (BIT(24)) 176 #define SPI_MEM_FREAD_QIO_V 0x1 177 #define SPI_MEM_FREAD_QIO_S 24 178 /* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ 179 /*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena 180 ble 0: disable..*/ 181 #define SPI_MEM_FREAD_DIO (BIT(23)) 182 #define SPI_MEM_FREAD_DIO_M (BIT(23)) 183 #define SPI_MEM_FREAD_DIO_V 0x1 184 #define SPI_MEM_FREAD_DIO_S 23 185 /* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ 186 /*description: two bytes data will be written to status register when it is set. 1: enable 0: d 187 isable..*/ 188 #define SPI_MEM_WRSR_2B (BIT(22)) 189 #define SPI_MEM_WRSR_2B_M (BIT(22)) 190 #define SPI_MEM_WRSR_2B_V 0x1 191 #define SPI_MEM_WRSR_2B_S 22 192 /* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ 193 /*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ 194 #define SPI_MEM_WP_REG (BIT(21)) 195 #define SPI_MEM_WP_REG_M (BIT(21)) 196 #define SPI_MEM_WP_REG_V 0x1 197 #define SPI_MEM_WP_REG_S 21 198 /* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ 199 /*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ 200 #define SPI_MEM_FREAD_QUAD (BIT(20)) 201 #define SPI_MEM_FREAD_QUAD_M (BIT(20)) 202 #define SPI_MEM_FREAD_QUAD_V 0x1 203 #define SPI_MEM_FREAD_QUAD_S 20 204 /* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ 205 /*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ 206 #define SPI_MEM_D_POL (BIT(19)) 207 #define SPI_MEM_D_POL_M (BIT(19)) 208 #define SPI_MEM_D_POL_V 0x1 209 #define SPI_MEM_D_POL_S 19 210 /* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ 211 /*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ 212 #define SPI_MEM_Q_POL (BIT(18)) 213 #define SPI_MEM_Q_POL_M (BIT(18)) 214 #define SPI_MEM_Q_POL_V 0x1 215 #define SPI_MEM_Q_POL_S 18 216 /* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ 217 /*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with 218 spi_mem_flash_res bit. 1: enable 0: disable..*/ 219 #define SPI_MEM_RESANDRES (BIT(15)) 220 #define SPI_MEM_RESANDRES_M (BIT(15)) 221 #define SPI_MEM_RESANDRES_V 0x1 222 #define SPI_MEM_RESANDRES_S 15 223 /* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ 224 /*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ 225 #define SPI_MEM_FREAD_DUAL (BIT(14)) 226 #define SPI_MEM_FREAD_DUAL_M (BIT(14)) 227 #define SPI_MEM_FREAD_DUAL_V 0x1 228 #define SPI_MEM_FREAD_DUAL_S 14 229 /* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ 230 /*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO 231 UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ 232 #define SPI_MEM_FASTRD_MODE (BIT(13)) 233 #define SPI_MEM_FASTRD_MODE_M (BIT(13)) 234 #define SPI_MEM_FASTRD_MODE_V 0x1 235 #define SPI_MEM_FASTRD_MODE_S 13 236 /* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ 237 /*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl 238 e.*/ 239 #define SPI_MEM_TX_CRC_EN (BIT(11)) 240 #define SPI_MEM_TX_CRC_EN_M (BIT(11)) 241 #define SPI_MEM_TX_CRC_EN_V 0x1 242 #define SPI_MEM_TX_CRC_EN_S 11 243 /* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ 244 /*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ 245 e low..*/ 246 #define SPI_MEM_FCS_CRC_EN (BIT(10)) 247 #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) 248 #define SPI_MEM_FCS_CRC_EN_V 0x1 249 #define SPI_MEM_FCS_CRC_EN_S 10 250 /* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */ 251 /*description: Apply 8 signals during command phase 1:enable 0: disable.*/ 252 #define SPI_MEM_FCMD_OCT (BIT(9)) 253 #define SPI_MEM_FCMD_OCT_M (BIT(9)) 254 #define SPI_MEM_FCMD_OCT_V 0x1 255 #define SPI_MEM_FCMD_OCT_S 9 256 /* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 257 /*description: Apply 4 signals during command phase 1:enable 0: disable.*/ 258 #define SPI_MEM_FCMD_QUAD (BIT(8)) 259 #define SPI_MEM_FCMD_QUAD_M (BIT(8)) 260 #define SPI_MEM_FCMD_QUAD_V 0x1 261 #define SPI_MEM_FCMD_QUAD_S 8 262 /* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */ 263 /*description: Apply 8 signals during address phase 1:enable 0: disable.*/ 264 #define SPI_MEM_FADDR_OCT (BIT(6)) 265 #define SPI_MEM_FADDR_OCT_M (BIT(6)) 266 #define SPI_MEM_FADDR_OCT_V 0x1 267 #define SPI_MEM_FADDR_OCT_S 6 268 /* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */ 269 /*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ 270 #define SPI_MEM_FDIN_OCT (BIT(5)) 271 #define SPI_MEM_FDIN_OCT_M (BIT(5)) 272 #define SPI_MEM_FDIN_OCT_V 0x1 273 #define SPI_MEM_FDIN_OCT_S 5 274 /* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */ 275 /*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ 276 #define SPI_MEM_FDOUT_OCT (BIT(4)) 277 #define SPI_MEM_FDOUT_OCT_M (BIT(4)) 278 #define SPI_MEM_FDOUT_OCT_V 0x1 279 #define SPI_MEM_FDOUT_OCT_S 4 280 /* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ 281 /*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] 282 is output by the MSPI controller in the second half part of dummy phase. It is u 283 sed to pre-drive flash..*/ 284 #define SPI_MEM_FDUMMY_WOUT (BIT(3)) 285 #define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) 286 #define SPI_MEM_FDUMMY_WOUT_V 0x1 287 #define SPI_MEM_FDUMMY_WOUT_S 3 288 /* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 289 /*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i 290 s output by the MSPI controller in the first half part of dummy phase. It is use 291 d to mask invalid SPI_DQS in the half part of dummy phase..*/ 292 #define SPI_MEM_FDUMMY_RIN (BIT(2)) 293 #define SPI_MEM_FDUMMY_RIN_M (BIT(2)) 294 #define SPI_MEM_FDUMMY_RIN_V 0x1 295 #define SPI_MEM_FDUMMY_RIN_S 2 296 /* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 297 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le 298 vel of SPI_IO[7:0] is output by the MSPI controller..*/ 299 #define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) 300 #define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) 301 #define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 302 #define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 303 /* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */ 304 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le 305 vel of SPI_DQS is output by the MSPI controller..*/ 306 #define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) 307 #define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) 308 #define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 309 #define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 310 311 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) 312 /* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ 313 /*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to 314 send signals to AXI. Set this bit to reset these FIFO..*/ 315 #define SPI_MEM_TXFIFO_RST (BIT(31)) 316 #define SPI_MEM_TXFIFO_RST_M (BIT(31)) 317 #define SPI_MEM_TXFIFO_RST_V 0x1 318 #define SPI_MEM_TXFIFO_RST_S 31 319 /* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ 320 /*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to 321 receive signals from AXI. Set this bit to reset these FIFO..*/ 322 #define SPI_MEM_RXFIFO_RST (BIT(30)) 323 #define SPI_MEM_RXFIFO_RST_M (BIT(30)) 324 #define SPI_MEM_RXFIFO_RST_V 0x1 325 #define SPI_MEM_RXFIFO_RST_S 30 326 /* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 327 /*description: Set this bit to write data faster, do not wait write data has been stored in tx_ 328 bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored 329 in tx_bus_fifo_l2..*/ 330 #define SPI_MEM_FAST_WRITE_EN (BIT(29)) 331 #define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) 332 #define SPI_MEM_FAST_WRITE_EN_V 0x1 333 #define SPI_MEM_FAST_WRITE_EN_S 29 334 /* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ 335 /*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at 336 the same time..*/ 337 #define SPI_MEM_DUAL_RAM_EN (BIT(28)) 338 #define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) 339 #define SPI_MEM_DUAL_RAM_EN_V 0x1 340 #define SPI_MEM_DUAL_RAM_EN_S 28 341 /* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ 342 /*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac 343 cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi 344 ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac 345 cessed at the same time..*/ 346 #define SPI_MEM_RAM0_EN (BIT(27)) 347 #define SPI_MEM_RAM0_EN_M (BIT(27)) 348 #define SPI_MEM_RAM0_EN_V 0x1 349 #define SPI_MEM_RAM0_EN_S 27 350 /* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */ 351 /*description: Set this bit to enable AXI Write Splice-transfer..*/ 352 #define SPI_MEM_AW_SPLICE_EN (BIT(26)) 353 #define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) 354 #define SPI_MEM_AW_SPLICE_EN_V 0x1 355 #define SPI_MEM_AW_SPLICE_EN_S 26 356 /* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */ 357 /*description: Set this bit to enable AXI Read Splice-transfer..*/ 358 #define SPI_MEM_AR_SPLICE_EN (BIT(25)) 359 #define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) 360 #define SPI_MEM_AR_SPLICE_EN_V 0x1 361 #define SPI_MEM_AR_SPLICE_EN_S 25 362 /* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ 363 /*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY 364 when there is a ECC error in AXI read data. The ECC error information is record 365 ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ 366 #define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) 367 #define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) 368 #define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 369 #define SPI_MEM_RRESP_ECC_ERR_EN_S 24 370 /* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */ 371 /*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R 372 eply AXI read data to AXI bus when all the read data is available..*/ 373 #define SPI_MEM_AXI_RDATA_BACK_FAST (BIT(23)) 374 #define SPI_MEM_AXI_RDATA_BACK_FAST_M (BIT(23)) 375 #define SPI_MEM_AXI_RDATA_BACK_FAST_V 0x1 376 #define SPI_MEM_AXI_RDATA_BACK_FAST_S 23 377 /* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 378 /*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ 379 #define SPI_MEM_AW_SIZE0_1_SUPPORT_EN (BIT(22)) 380 #define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) 381 #define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V 0x1 382 #define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S 22 383 /* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ 384 /*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl 385 y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ 386 #define SPI_MEM_AR_SIZE0_1_SUPPORT_EN (BIT(21)) 387 #define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) 388 #define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V 0x1 389 #define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S 21 390 /* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ 391 /*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 392 12) SPI_CLK cycles..*/ 393 #define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF 394 #define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) 395 #define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF 396 #define SPI_MEM_CS_HOLD_DLY_RES_S 2 397 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 398 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye 399 d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti 400 ve 3: SPI clock is alwasy on..*/ 401 #define SPI_MEM_CLK_MODE 0x00000003 402 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) 403 #define SPI_MEM_CLK_MODE_V 0x3 404 #define SPI_MEM_CLK_MODE_S 0 405 406 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) 407 /* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ 408 /*description: The spi0_mst_st and spi0_slv_st will be reset..*/ 409 #define SPI_MEM_SYNC_RESET (BIT(31)) 410 #define SPI_MEM_SYNC_RESET_M (BIT(31)) 411 #define SPI_MEM_SYNC_RESET_V 0x1 412 #define SPI_MEM_SYNC_RESET_S 31 413 /* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ 414 /*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran 415 sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core 416 clock cycles..*/ 417 #define SPI_MEM_CS_HOLD_DELAY 0x0000003F 418 #define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) 419 #define SPI_MEM_CS_HOLD_DELAY_V 0x3F 420 #define SPI_MEM_CS_HOLD_DELAY_S 25 421 /* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ 422 /*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans 423 fers when one transfer will cross flash or EXT_RAM page corner, valid no matter 424 whether there is an ECC region or not..*/ 425 #define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) 426 #define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) 427 #define SPI_MEM_SPLIT_TRANS_EN_V 0x1 428 #define SPI_MEM_SPLIT_TRANS_EN_S 24 429 /* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ 430 /*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe 431 n accesses flash..*/ 432 #define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) 433 #define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) 434 #define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 435 #define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 436 /* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */ 437 /*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w 438 hen accesses flash..*/ 439 #define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) 440 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) 441 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 442 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 443 /* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */ 444 /*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC 445 mode when accessed flash..*/ 446 #define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 447 #define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) 448 #define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 449 #define SPI_MEM_ECC_CS_HOLD_TIME_S 10 450 /* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ 451 /*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi 452 th SPI_MEM_CS_HOLD bit..*/ 453 #define SPI_MEM_CS_HOLD_TIME 0x0000001F 454 #define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) 455 #define SPI_MEM_CS_HOLD_TIME_V 0x1F 456 #define SPI_MEM_CS_HOLD_TIME_S 5 457 /* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ 458 /*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME 459 M_CS_SETUP bit..*/ 460 #define SPI_MEM_CS_SETUP_TIME 0x0000001F 461 #define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) 462 #define SPI_MEM_CS_SETUP_TIME_V 0x1F 463 #define SPI_MEM_CS_SETUP_TIME_S 0 464 465 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) 466 /* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ 467 /*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module 468 clock..*/ 469 #define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) 470 #define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) 471 #define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 472 #define SPI_MEM_CLK_EQU_SYSCLK_S 31 473 /* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ 474 /*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is 475 system/(spi_mem_clkcnt_N+1).*/ 476 #define SPI_MEM_CLKCNT_N 0x000000FF 477 #define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) 478 #define SPI_MEM_CLKCNT_N_V 0xFF 479 #define SPI_MEM_CLKCNT_N_S 16 480 /* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ 481 /*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ 482 #define SPI_MEM_CLKCNT_H 0x000000FF 483 #define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) 484 #define SPI_MEM_CLKCNT_H_V 0xFF 485 #define SPI_MEM_CLKCNT_H_S 8 486 /* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ 487 /*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ 488 #define SPI_MEM_CLKCNT_L 0x000000FF 489 #define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) 490 #define SPI_MEM_CLKCNT_L_V 0xFF 491 #define SPI_MEM_CLKCNT_L_S 0 492 493 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) 494 /* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ 495 /*description: This bit enable the command phase of an operation..*/ 496 #define SPI_MEM_USR_COMMAND (BIT(31)) 497 #define SPI_MEM_USR_COMMAND_M (BIT(31)) 498 #define SPI_MEM_USR_COMMAND_V 0x1 499 #define SPI_MEM_USR_COMMAND_S 31 500 /* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ 501 /*description: This bit enable the address phase of an operation..*/ 502 #define SPI_MEM_USR_ADDR (BIT(30)) 503 #define SPI_MEM_USR_ADDR_M (BIT(30)) 504 #define SPI_MEM_USR_ADDR_V 0x1 505 #define SPI_MEM_USR_ADDR_S 30 506 /* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ 507 /*description: This bit enable the dummy phase of an operation..*/ 508 #define SPI_MEM_USR_DUMMY (BIT(29)) 509 #define SPI_MEM_USR_DUMMY_M (BIT(29)) 510 #define SPI_MEM_USR_DUMMY_V 0x1 511 #define SPI_MEM_USR_DUMMY_S 29 512 /* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ 513 /*description: This bit enable the read-data phase of an operation..*/ 514 #define SPI_MEM_USR_MISO (BIT(28)) 515 #define SPI_MEM_USR_MISO_M (BIT(28)) 516 #define SPI_MEM_USR_MISO_V 0x1 517 #define SPI_MEM_USR_MISO_S 28 518 /* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ 519 /*description: This bit enable the write-data phase of an operation..*/ 520 #define SPI_MEM_USR_MOSI (BIT(27)) 521 #define SPI_MEM_USR_MOSI_M (BIT(27)) 522 #define SPI_MEM_USR_MOSI_V 0x1 523 #define SPI_MEM_USR_MOSI_S 27 524 /* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 525 /*description: spi clock is disable in dummy phase when the bit is enable..*/ 526 #define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) 527 #define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) 528 #define SPI_MEM_USR_DUMMY_IDLE_V 0x1 529 #define SPI_MEM_USR_DUMMY_IDLE_S 26 530 /* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */ 531 /*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 532 1: enable 0: disable..*/ 533 #define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) 534 #define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) 535 #define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 536 #define SPI_MEM_USR_MOSI_HIGHPART_S 25 537 /* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */ 538 /*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 539 : enable 0: disable..*/ 540 #define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) 541 #define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) 542 #define SPI_MEM_USR_MISO_HIGHPART_V 0x1 543 #define SPI_MEM_USR_MISO_HIGHPART_S 24 544 /* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ 545 /*description: In the write operations address phase and read-data phase apply 4 signals..*/ 546 #define SPI_MEM_FWRITE_QIO (BIT(15)) 547 #define SPI_MEM_FWRITE_QIO_M (BIT(15)) 548 #define SPI_MEM_FWRITE_QIO_V 0x1 549 #define SPI_MEM_FWRITE_QIO_S 15 550 /* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ 551 /*description: In the write operations address phase and read-data phase apply 2 signals..*/ 552 #define SPI_MEM_FWRITE_DIO (BIT(14)) 553 #define SPI_MEM_FWRITE_DIO_M (BIT(14)) 554 #define SPI_MEM_FWRITE_DIO_V 0x1 555 #define SPI_MEM_FWRITE_DIO_S 14 556 /* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 557 /*description: In the write operations read-data phase apply 4 signals.*/ 558 #define SPI_MEM_FWRITE_QUAD (BIT(13)) 559 #define SPI_MEM_FWRITE_QUAD_M (BIT(13)) 560 #define SPI_MEM_FWRITE_QUAD_V 0x1 561 #define SPI_MEM_FWRITE_QUAD_S 13 562 /* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ 563 /*description: In the write operations read-data phase apply 2 signals.*/ 564 #define SPI_MEM_FWRITE_DUAL (BIT(12)) 565 #define SPI_MEM_FWRITE_DUAL_M (BIT(12)) 566 #define SPI_MEM_FWRITE_DUAL_V 0x1 567 #define SPI_MEM_FWRITE_DUAL_S 12 568 /* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 569 /*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ 570 #define SPI_MEM_CK_OUT_EDGE (BIT(9)) 571 #define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) 572 #define SPI_MEM_CK_OUT_EDGE_V 0x1 573 #define SPI_MEM_CK_OUT_EDGE_S 9 574 /* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ 575 /*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ 576 #define SPI_MEM_CS_SETUP (BIT(7)) 577 #define SPI_MEM_CS_SETUP_M (BIT(7)) 578 #define SPI_MEM_CS_SETUP_V 0x1 579 #define SPI_MEM_CS_SETUP_S 7 580 /* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 581 /*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ 582 #define SPI_MEM_CS_HOLD (BIT(6)) 583 #define SPI_MEM_CS_HOLD_M (BIT(6)) 584 #define SPI_MEM_CS_HOLD_V 0x1 585 #define SPI_MEM_CS_HOLD_S 6 586 587 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) 588 /* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ 589 /*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ 590 #define SPI_MEM_USR_ADDR_BITLEN 0x0000003F 591 #define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) 592 #define SPI_MEM_USR_ADDR_BITLEN_V 0x3F 593 #define SPI_MEM_USR_ADDR_BITLEN_S 26 594 /* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */ 595 /*description: SPI0 USR_CMD read or write data byte length -1.*/ 596 #define SPI_MEM_USR_DBYTELEN 0x00000007 597 #define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) 598 #define SPI_MEM_USR_DBYTELEN_V 0x7 599 #define SPI_MEM_USR_DBYTELEN_S 6 600 /* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ 601 /*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy 602 cle_num-1)..*/ 603 #define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F 604 #define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) 605 #define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F 606 #define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 607 608 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) 609 /* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ 610 /*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ 611 #define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F 612 #define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) 613 #define SPI_MEM_USR_COMMAND_BITLEN_V 0xF 614 #define SPI_MEM_USR_COMMAND_BITLEN_S 28 615 /* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 616 /*description: The value of command..*/ 617 #define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF 618 #define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) 619 #define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF 620 #define SPI_MEM_USR_COMMAND_VALUE_S 0 621 622 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) 623 /* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 624 /*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ 625 #define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF 626 #define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) 627 #define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF 628 #define SPI_MEM_USR_MOSI_DBITLEN_S 0 629 630 #define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) 631 /* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 632 /*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ 633 #define SPI_MEM_USR_MISO_DBITLEN 0x000003FF 634 #define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) 635 #define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF 636 #define SPI_MEM_USR_MISO_DBITLEN_S 0 637 638 #define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) 639 /* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ 640 /*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b 641 it..*/ 642 #define SPI_MEM_WB_MODE 0x000000FF 643 #define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) 644 #define SPI_MEM_WB_MODE_V 0xFF 645 #define SPI_MEM_WB_MODE_S 16 646 /* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ 647 /*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ 648 #define SPI_MEM_STATUS 0x0000FFFF 649 #define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) 650 #define SPI_MEM_STATUS_V 0xFFFF 651 #define SPI_MEM_STATUS_S 0 652 653 #define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) 654 /* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 655 /*description: SPI_CS line keep low when the bit is set..*/ 656 #define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) 657 #define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) 658 #define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 659 #define SPI_MEM_CS_KEEP_ACTIVE_S 10 660 /* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 661 /*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ 662 #define SPI_MEM_CK_IDLE_EDGE (BIT(9)) 663 #define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) 664 #define SPI_MEM_CK_IDLE_EDGE_V 0x1 665 #define SPI_MEM_CK_IDLE_EDGE_S 9 666 /* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ 667 /*description: For SPI0, sram is connected to SUBPINs..*/ 668 #define SPI_MEM_SSUB_PIN (BIT(8)) 669 #define SPI_MEM_SSUB_PIN_M (BIT(8)) 670 #define SPI_MEM_SSUB_PIN_V 0x1 671 #define SPI_MEM_SSUB_PIN_S 8 672 /* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ 673 /*description: For SPI0, flash is connected to SUBPINs..*/ 674 #define SPI_MEM_FSUB_PIN (BIT(7)) 675 #define SPI_MEM_FSUB_PIN_M (BIT(7)) 676 #define SPI_MEM_FSUB_PIN_V 0x1 677 #define SPI_MEM_FSUB_PIN_S 7 678 /* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 679 /*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d 680 evice, such as flash, external RAM and so on..*/ 681 #define SPI_MEM_CS1_DIS (BIT(1)) 682 #define SPI_MEM_CS1_DIS_M (BIT(1)) 683 #define SPI_MEM_CS1_DIS_V 0x1 684 #define SPI_MEM_CS1_DIS_S 1 685 /* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 686 /*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d 687 evice, such as flash, external RAM and so on..*/ 688 #define SPI_MEM_CS0_DIS (BIT(0)) 689 #define SPI_MEM_CS0_DIS_M (BIT(0)) 690 #define SPI_MEM_CS0_DIS_V 0x1 691 #define SPI_MEM_CS0_DIS_S 0 692 693 #define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) 694 /* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 695 /*description: For SPI1, the value of crc32..*/ 696 #define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF 697 #define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) 698 #define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF 699 #define SPI_MEM_TX_CRC_DATA_S 0 700 701 #define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) 702 /* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ 703 /*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV 704 _ERR will be replied to BRESP/RRESP..*/ 705 #define SPI_MEM_CLOSE_AXI_INF_EN (BIT(31)) 706 #define SPI_MEM_CLOSE_AXI_INF_EN_M (BIT(31)) 707 #define SPI_MEM_CLOSE_AXI_INF_EN_V 0x1 708 #define SPI_MEM_CLOSE_AXI_INF_EN_S 31 709 /* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */ 710 /*description: Set this bit to check AXI read/write the same address region..*/ 711 #define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) 712 #define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) 713 #define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V 0x1 714 #define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S 30 715 /* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 716 /*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is 717 the same with spi_mem_fread_qio..*/ 718 #define SPI_MEM_FADDR_QUAD (BIT(8)) 719 #define SPI_MEM_FADDR_QUAD_M (BIT(8)) 720 #define SPI_MEM_FADDR_QUAD_V 0x1 721 #define SPI_MEM_FADDR_QUAD_S 8 722 /* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 723 /*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th 724 e same with spi_mem_fread_qio..*/ 725 #define SPI_MEM_FDOUT_QUAD (BIT(7)) 726 #define SPI_MEM_FDOUT_QUAD_M (BIT(7)) 727 #define SPI_MEM_FDOUT_QUAD_V 0x1 728 #define SPI_MEM_FDOUT_QUAD_S 7 729 /* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 730 /*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the 731 same with spi_mem_fread_qio..*/ 732 #define SPI_MEM_FDIN_QUAD (BIT(6)) 733 #define SPI_MEM_FDIN_QUAD_M (BIT(6)) 734 #define SPI_MEM_FDIN_QUAD_V 0x1 735 #define SPI_MEM_FDIN_QUAD_S 6 736 /* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ 737 /*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is 738 the same with spi_mem_fread_dio..*/ 739 #define SPI_MEM_FADDR_DUAL (BIT(5)) 740 #define SPI_MEM_FADDR_DUAL_M (BIT(5)) 741 #define SPI_MEM_FADDR_DUAL_V 0x1 742 #define SPI_MEM_FADDR_DUAL_S 5 743 /* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ 744 /*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the 745 same with spi_mem_fread_dio..*/ 746 #define SPI_MEM_FDOUT_DUAL (BIT(4)) 747 #define SPI_MEM_FDOUT_DUAL_M (BIT(4)) 748 #define SPI_MEM_FDOUT_DUAL_V 0x1 749 #define SPI_MEM_FDOUT_DUAL_S 4 750 /* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ 751 /*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the 752 same with spi_mem_fread_dio..*/ 753 #define SPI_MEM_FDIN_DUAL (BIT(3)) 754 #define SPI_MEM_FDIN_DUAL_M (BIT(3)) 755 #define SPI_MEM_FDIN_DUAL_V 0x1 756 #define SPI_MEM_FDIN_DUAL_S 3 757 /* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 758 /*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ 759 #define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) 760 #define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) 761 #define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 762 #define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 763 /* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 764 /*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ 765 #define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) 766 #define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) 767 #define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 768 #define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 769 /* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 770 /*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ 771 #define SPI_MEM_AXI_REQ_EN (BIT(0)) 772 #define SPI_MEM_AXI_REQ_EN_M (BIT(0)) 773 #define SPI_MEM_AXI_REQ_EN_V 0x1 774 #define SPI_MEM_AXI_REQ_EN_S 0 775 776 #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) 777 /* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */ 778 /*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas 779 e. The register value shall be (bit_num-1)..*/ 780 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F 781 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) 782 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F 783 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 784 /* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ 785 /*description: reserved.*/ 786 #define SPI_MEM_SRAM_OCT (BIT(21)) 787 #define SPI_MEM_SRAM_OCT_M (BIT(21)) 788 #define SPI_MEM_SRAM_OCT_V 0x1 789 #define SPI_MEM_SRAM_OCT_S 21 790 /* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */ 791 /*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ 792 #define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) 793 #define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) 794 #define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 795 #define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 796 /* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */ 797 /*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T 798 he register value shall be (bit_num-1)..*/ 799 #define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F 800 #define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) 801 #define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F 802 #define SPI_MEM_SRAM_ADDR_BITLEN_S 14 803 /* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */ 804 /*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase 805 . The register value shall be (bit_num-1)..*/ 806 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F 807 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) 808 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F 809 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 810 /* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ 811 /*description: For SPI0, In the external RAM mode cache read external RAM for user define comma 812 nd..*/ 813 #define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) 814 #define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) 815 #define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 816 #define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 817 /* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */ 818 /*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read 819 operations..*/ 820 #define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) 821 #define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) 822 #define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 823 #define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 824 /* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */ 825 /*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ 826 e operations..*/ 827 #define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) 828 #define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) 829 #define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 830 #define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 831 /* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */ 832 /*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab 833 le.*/ 834 #define SPI_MEM_USR_SRAM_QIO (BIT(2)) 835 #define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) 836 #define SPI_MEM_USR_SRAM_QIO_V 0x1 837 #define SPI_MEM_USR_SRAM_QIO_S 2 838 /* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */ 839 /*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab 840 le.*/ 841 #define SPI_MEM_USR_SRAM_DIO (BIT(1)) 842 #define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) 843 #define SPI_MEM_USR_SRAM_DIO_V 0x1 844 #define SPI_MEM_USR_SRAM_DIO_S 1 845 /* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */ 846 /*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en 847 able, 0:disable..*/ 848 #define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) 849 #define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) 850 #define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 851 #define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 852 853 #define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) 854 /* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */ 855 /*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 856 ] are always 1. 0: Others..*/ 857 #define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) 858 #define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) 859 #define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V 0x1 860 #define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S 31 861 /* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */ 862 /*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar 863 e always 1. 0: Others..*/ 864 #define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) 865 #define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) 866 #define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V 0x1 867 #define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S 30 868 /* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */ 869 /*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, 870 the level of SPI_IO[7:0] is output by the MSPI controller..*/ 871 #define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) 872 #define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) 873 #define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 874 #define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S 25 875 /* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */ 876 /*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, 877 the level of SPI_DQS is output by the MSPI controller..*/ 878 #define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) 879 #define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) 880 #define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 881 #define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 882 /* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */ 883 /*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, 884 the signal level of SPI bus is output by the MSPI controller..*/ 885 #define SPI_MEM_SDUMMY_WOUT (BIT(23)) 886 #define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) 887 #define SPI_MEM_SDUMMY_WOUT_V 0x1 888 #define SPI_MEM_SDUMMY_WOUT_S 23 889 /* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 890 /*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t 891 he signal level of SPI bus is output by the MSPI controller..*/ 892 #define SPI_MEM_SDUMMY_RIN (BIT(22)) 893 #define SPI_MEM_SDUMMY_RIN_M (BIT(22)) 894 #define SPI_MEM_SDUMMY_RIN_V 0x1 895 #define SPI_MEM_SDUMMY_RIN_S 22 896 /* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ 897 /*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ 898 #define SPI_MEM_SCMD_OCT (BIT(21)) 899 #define SPI_MEM_SCMD_OCT_M (BIT(21)) 900 #define SPI_MEM_SCMD_OCT_V 0x1 901 #define SPI_MEM_SCMD_OCT_S 21 902 /* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */ 903 /*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ 904 #define SPI_MEM_SADDR_OCT (BIT(20)) 905 #define SPI_MEM_SADDR_OCT_M (BIT(20)) 906 #define SPI_MEM_SADDR_OCT_V 0x1 907 #define SPI_MEM_SADDR_OCT_S 20 908 /* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */ 909 /*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ 910 #define SPI_MEM_SDOUT_OCT (BIT(19)) 911 #define SPI_MEM_SDOUT_OCT_M (BIT(19)) 912 #define SPI_MEM_SDOUT_OCT_V 0x1 913 #define SPI_MEM_SDOUT_OCT_S 19 914 /* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */ 915 /*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ 916 #define SPI_MEM_SDIN_OCT (BIT(18)) 917 #define SPI_MEM_SDIN_OCT_M (BIT(18)) 918 #define SPI_MEM_SDIN_OCT_V 0x1 919 #define SPI_MEM_SDIN_OCT_S 18 920 /* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */ 921 /*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit 922 is the same with spi_mem_usr_sram_qio..*/ 923 #define SPI_MEM_SCMD_QUAD (BIT(17)) 924 #define SPI_MEM_SCMD_QUAD_M (BIT(17)) 925 #define SPI_MEM_SCMD_QUAD_V 0x1 926 #define SPI_MEM_SCMD_QUAD_S 17 927 /* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */ 928 /*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The 929 bit is the same with spi_mem_usr_sram_qio..*/ 930 #define SPI_MEM_SADDR_QUAD (BIT(16)) 931 #define SPI_MEM_SADDR_QUAD_M (BIT(16)) 932 #define SPI_MEM_SADDR_QUAD_V 0x1 933 #define SPI_MEM_SADDR_QUAD_S 16 934 /* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */ 935 /*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi 936 t is the same with spi_mem_usr_sram_qio..*/ 937 #define SPI_MEM_SDOUT_QUAD (BIT(15)) 938 #define SPI_MEM_SDOUT_QUAD_M (BIT(15)) 939 #define SPI_MEM_SDOUT_QUAD_V 0x1 940 #define SPI_MEM_SDOUT_QUAD_S 15 941 /* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */ 942 /*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit 943 is the same with spi_mem_usr_sram_qio..*/ 944 #define SPI_MEM_SDIN_QUAD (BIT(14)) 945 #define SPI_MEM_SDIN_QUAD_M (BIT(14)) 946 #define SPI_MEM_SDIN_QUAD_V 0x1 947 #define SPI_MEM_SDIN_QUAD_S 14 948 /* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */ 949 /*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The 950 bit is the same with spi_mem_usr_sram_dio..*/ 951 #define SPI_MEM_SADDR_DUAL (BIT(12)) 952 #define SPI_MEM_SADDR_DUAL_M (BIT(12)) 953 #define SPI_MEM_SADDR_DUAL_V 0x1 954 #define SPI_MEM_SADDR_DUAL_S 12 955 /* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */ 956 /*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi 957 t is the same with spi_mem_usr_sram_dio..*/ 958 #define SPI_MEM_SDOUT_DUAL (BIT(11)) 959 #define SPI_MEM_SDOUT_DUAL_M (BIT(11)) 960 #define SPI_MEM_SDOUT_DUAL_V 0x1 961 #define SPI_MEM_SDOUT_DUAL_S 11 962 /* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */ 963 /*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit 964 is the same with spi_mem_usr_sram_dio..*/ 965 #define SPI_MEM_SDIN_DUAL (BIT(10)) 966 #define SPI_MEM_SDIN_DUAL_M (BIT(10)) 967 #define SPI_MEM_SDIN_DUAL_V 0x1 968 #define SPI_MEM_SDIN_DUAL_S 10 969 /* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */ 970 /*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd 971 _mode bit..*/ 972 #define SPI_MEM_SWB_MODE 0x000000FF 973 #define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) 974 #define SPI_MEM_SWB_MODE_V 0xFF 975 #define SPI_MEM_SWB_MODE_S 2 976 /* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */ 977 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye 978 d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti 979 ve 3: SPI clock is always on..*/ 980 #define SPI_MEM_SCLK_MODE 0x00000003 981 #define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) 982 #define SPI_MEM_SCLK_MODE_V 0x3 983 #define SPI_MEM_SCLK_MODE_S 0 984 985 #define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) 986 /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ 987 /*description: For SPI0,When cache mode is enable it is the length in bits of command phase for 988 sram. The register value shall be (bit_num-1)..*/ 989 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F 990 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) 991 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF 992 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 993 /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ 994 /*description: For SPI0,When cache mode is enable it is the read command value of command phase 995 for sram..*/ 996 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF 997 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) 998 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF 999 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 1000 1001 #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) 1002 /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ 1003 /*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. 1004 The register value shall be (bit_num-1)..*/ 1005 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F 1006 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) 1007 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF 1008 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 1009 /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ 1010 /*description: For SPI0,When cache mode is enable it is the write command value of command phas 1011 e for sram..*/ 1012 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF 1013 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) 1014 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF 1015 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 1016 1017 #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) 1018 /* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ 1019 /*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c 1020 lk is divided from system clock..*/ 1021 #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) 1022 #define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) 1023 #define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 1024 #define SPI_MEM_SCLK_EQU_SYSCLK_S 31 1025 /* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */ 1026 /*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c 1027 lk frequency is system/(spi_mem_clkcnt_N+1).*/ 1028 #define SPI_MEM_SCLKCNT_N 0x000000FF 1029 #define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) 1030 #define SPI_MEM_SCLKCNT_N_V 0xFF 1031 #define SPI_MEM_SCLKCNT_N_S 16 1032 /* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */ 1033 /*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ 1034 #define SPI_MEM_SCLKCNT_H 0x000000FF 1035 #define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) 1036 #define SPI_MEM_SCLKCNT_H_V 0xFF 1037 #define SPI_MEM_SCLKCNT_H_S 8 1038 /* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */ 1039 /*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ 1040 #define SPI_MEM_SCLKCNT_L 0x000000FF 1041 #define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) 1042 #define SPI_MEM_SCLKCNT_L_V 0xFF 1043 #define SPI_MEM_SCLKCNT_L_S 0 1044 1045 #define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) 1046 /* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ 1047 /*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ 1048 #define SPI_MEM_LOCK_DELAY_TIME 0x0000001F 1049 #define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) 1050 #define SPI_MEM_LOCK_DELAY_TIME_V 0x1F 1051 #define SPI_MEM_LOCK_DELAY_TIME_S 7 1052 1053 #define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) 1054 /* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1055 /*description: data buffer.*/ 1056 #define SPI_MEM_BUF0 0xFFFFFFFF 1057 #define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) 1058 #define SPI_MEM_BUF0_V 0xFFFFFFFF 1059 #define SPI_MEM_BUF0_S 0 1060 1061 #define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) 1062 /* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1063 /*description: data buffer.*/ 1064 #define SPI_MEM_BUF1 0xFFFFFFFF 1065 #define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) 1066 #define SPI_MEM_BUF1_V 0xFFFFFFFF 1067 #define SPI_MEM_BUF1_S 0 1068 1069 #define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) 1070 /* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1071 /*description: data buffer.*/ 1072 #define SPI_MEM_BUF2 0xFFFFFFFF 1073 #define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) 1074 #define SPI_MEM_BUF2_V 0xFFFFFFFF 1075 #define SPI_MEM_BUF2_S 0 1076 1077 #define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) 1078 /* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1079 /*description: data buffer.*/ 1080 #define SPI_MEM_BUF3 0xFFFFFFFF 1081 #define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) 1082 #define SPI_MEM_BUF3_V 0xFFFFFFFF 1083 #define SPI_MEM_BUF3_S 0 1084 1085 #define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) 1086 /* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1087 /*description: data buffer.*/ 1088 #define SPI_MEM_BUF4 0xFFFFFFFF 1089 #define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) 1090 #define SPI_MEM_BUF4_V 0xFFFFFFFF 1091 #define SPI_MEM_BUF4_S 0 1092 1093 #define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) 1094 /* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1095 /*description: data buffer.*/ 1096 #define SPI_MEM_BUF5 0xFFFFFFFF 1097 #define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) 1098 #define SPI_MEM_BUF5_V 0xFFFFFFFF 1099 #define SPI_MEM_BUF5_S 0 1100 1101 #define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) 1102 /* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1103 /*description: data buffer.*/ 1104 #define SPI_MEM_BUF6 0xFFFFFFFF 1105 #define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) 1106 #define SPI_MEM_BUF6_V 0xFFFFFFFF 1107 #define SPI_MEM_BUF6_S 0 1108 1109 #define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) 1110 /* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1111 /*description: data buffer.*/ 1112 #define SPI_MEM_BUF7 0xFFFFFFFF 1113 #define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) 1114 #define SPI_MEM_BUF7_V 0xFFFFFFFF 1115 #define SPI_MEM_BUF7_S 0 1116 1117 #define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) 1118 /* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1119 /*description: data buffer.*/ 1120 #define SPI_MEM_BUF8 0xFFFFFFFF 1121 #define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) 1122 #define SPI_MEM_BUF8_V 0xFFFFFFFF 1123 #define SPI_MEM_BUF8_S 0 1124 1125 #define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) 1126 /* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1127 /*description: data buffer.*/ 1128 #define SPI_MEM_BUF9 0xFFFFFFFF 1129 #define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) 1130 #define SPI_MEM_BUF9_V 0xFFFFFFFF 1131 #define SPI_MEM_BUF9_S 0 1132 1133 #define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) 1134 /* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1135 /*description: data buffer.*/ 1136 #define SPI_MEM_BUF10 0xFFFFFFFF 1137 #define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) 1138 #define SPI_MEM_BUF10_V 0xFFFFFFFF 1139 #define SPI_MEM_BUF10_S 0 1140 1141 #define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) 1142 /* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1143 /*description: data buffer.*/ 1144 #define SPI_MEM_BUF11 0xFFFFFFFF 1145 #define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) 1146 #define SPI_MEM_BUF11_V 0xFFFFFFFF 1147 #define SPI_MEM_BUF11_S 0 1148 1149 #define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) 1150 /* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1151 /*description: data buffer.*/ 1152 #define SPI_MEM_BUF12 0xFFFFFFFF 1153 #define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) 1154 #define SPI_MEM_BUF12_V 0xFFFFFFFF 1155 #define SPI_MEM_BUF12_S 0 1156 1157 #define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) 1158 /* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1159 /*description: data buffer.*/ 1160 #define SPI_MEM_BUF13 0xFFFFFFFF 1161 #define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) 1162 #define SPI_MEM_BUF13_V 0xFFFFFFFF 1163 #define SPI_MEM_BUF13_S 0 1164 1165 #define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) 1166 /* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1167 /*description: data buffer.*/ 1168 #define SPI_MEM_BUF14 0xFFFFFFFF 1169 #define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) 1170 #define SPI_MEM_BUF14_V 0xFFFFFFFF 1171 #define SPI_MEM_BUF14_S 0 1172 1173 #define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) 1174 /* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ 1175 /*description: data buffer.*/ 1176 #define SPI_MEM_BUF15 0xFFFFFFFF 1177 #define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) 1178 #define SPI_MEM_BUF15_V 0xFFFFFFFF 1179 #define SPI_MEM_BUF15_S 0 1180 1181 #define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) 1182 /* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ 1183 /*description: The command value to wait flash idle(RDSR)..*/ 1184 #define SPI_MEM_WAITI_CMD 0x0000FFFF 1185 #define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) 1186 #define SPI_MEM_WAITI_CMD_V 0xFFFF 1187 #define SPI_MEM_WAITI_CMD_S 16 1188 /* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ 1189 /*description: The dummy cycle length when wait flash idle(RDSR)..*/ 1190 #define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F 1191 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) 1192 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F 1193 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 1194 /* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ 1195 /*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 1196 8..*/ 1197 #define SPI_MEM_WAITI_CMD_2B (BIT(9)) 1198 #define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) 1199 #define SPI_MEM_WAITI_CMD_2B_V 0x1 1200 #define SPI_MEM_WAITI_CMD_2B_S 9 1201 /* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ 1202 /*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI 1203 _MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when 1204 SPI_MEM_WAITI_ADDR_EN is cleared..*/ 1205 #define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 1206 #define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) 1207 #define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 1208 #define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 1209 /* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1210 /*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad 1211 dress in RDSR or read SUS command transfer..*/ 1212 #define SPI_MEM_WAITI_ADDR_EN (BIT(2)) 1213 #define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) 1214 #define SPI_MEM_WAITI_ADDR_EN_V 0x1 1215 #define SPI_MEM_WAITI_ADDR_EN_S 2 1216 /* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1217 /*description: The dummy phase enable when wait flash idle (RDSR).*/ 1218 #define SPI_MEM_WAITI_DUMMY (BIT(1)) 1219 #define SPI_MEM_WAITI_DUMMY_M (BIT(1)) 1220 #define SPI_MEM_WAITI_DUMMY_V 0x1 1221 #define SPI_MEM_WAITI_DUMMY_S 1 1222 /* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1223 /*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto 1224 Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto 1225 Suspend/Resume are not supported..*/ 1226 #define SPI_MEM_WAITI_EN (BIT(0)) 1227 #define SPI_MEM_WAITI_EN_M (BIT(0)) 1228 #define SPI_MEM_WAITI_EN_V 0x1 1229 #define SPI_MEM_WAITI_EN_S 0 1230 1231 #define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) 1232 /* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ 1233 /*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, 1234 it will be treated as check pass..*/ 1235 #define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F 1236 #define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) 1237 #define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F 1238 #define SPI_MEM_SUS_TIMEOUT_CNT_S 25 1239 /* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ 1240 /*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu 1241 s of flash. 0: Only need to check WIP is 0..*/ 1242 #define SPI_MEM_PES_END_EN (BIT(24)) 1243 #define SPI_MEM_PES_END_EN_M (BIT(24)) 1244 #define SPI_MEM_PES_END_EN_V 0x1 1245 #define SPI_MEM_PES_END_EN_S 24 1246 /* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1247 /*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status 1248 of flash. 0: Only need to check WIP is 0..*/ 1249 #define SPI_MEM_PER_END_EN (BIT(23)) 1250 #define SPI_MEM_PER_END_EN_M (BIT(23)) 1251 #define SPI_MEM_PER_END_EN_V 0x1 1252 #define SPI_MEM_PER_END_EN_S 23 1253 /* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ 1254 /*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w 1255 hen check flash SUS/SUS1/SUS2 status bit.*/ 1256 #define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) 1257 #define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22)) 1258 #define SPI_MEM_FMEM_RD_SUS_2B_V 0x1 1259 #define SPI_MEM_FMEM_RD_SUS_2B_S 22 1260 /* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ 1261 /*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is 1262 status_in[15:0](only status_in[7:0] is valid when only one byte of data is read 1263 out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS 1264 2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ 1265 #define SPI_MEM_PESR_END_MSK 0x0000FFFF 1266 #define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) 1267 #define SPI_MEM_PESR_END_MSK_V 0xFFFF 1268 #define SPI_MEM_PESR_END_MSK_S 6 1269 /* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1270 /*description: Set this bit to enable Auto-suspending function..*/ 1271 #define SPI_MEM_FLASH_PES_EN (BIT(5)) 1272 #define SPI_MEM_FLASH_PES_EN_M (BIT(5)) 1273 #define SPI_MEM_FLASH_PES_EN_V 0x1 1274 #define SPI_MEM_FLASH_PES_EN_S 5 1275 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1276 /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a 1277 pplication should send PER after PES is done..*/ 1278 #define SPI_MEM_PES_PER_EN (BIT(4)) 1279 #define SPI_MEM_PES_PER_EN_M (BIT(4)) 1280 #define SPI_MEM_PES_PER_EN_V 0x1 1281 #define SPI_MEM_PES_PER_EN_S 4 1282 /* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1283 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after 1284 program erase suspend command is sent. 0: SPI1 does not wait after program erase 1285 suspend command is sent..*/ 1286 #define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) 1287 #define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) 1288 #define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 1289 #define SPI_MEM_FLASH_PES_WAIT_EN_S 3 1290 /* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1291 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after 1292 program erase resume command is sent. 0: SPI1 does not wait after program erase 1293 resume command is sent..*/ 1294 #define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) 1295 #define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) 1296 #define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 1297 #define SPI_MEM_FLASH_PER_WAIT_EN_S 2 1298 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ 1299 /*description: program erase suspend bit, program erase suspend operation will be triggered whe 1300 n the bit is set. The bit will be cleared once the operation done.1: enable 0: d 1301 isable..*/ 1302 #define SPI_MEM_FLASH_PES (BIT(1)) 1303 #define SPI_MEM_FLASH_PES_M (BIT(1)) 1304 #define SPI_MEM_FLASH_PES_V 0x1 1305 #define SPI_MEM_FLASH_PES_S 1 1306 /* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ 1307 /*description: program erase resume bit, program erase suspend operation will be triggered when 1308 the bit is set. The bit will be cleared once the operation done.1: enable 0: di 1309 sable..*/ 1310 #define SPI_MEM_FLASH_PER (BIT(0)) 1311 #define SPI_MEM_FLASH_PER_M (BIT(0)) 1312 #define SPI_MEM_FLASH_PER_V 0x1 1313 #define SPI_MEM_FLASH_PER_S 0 1314 1315 #define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) 1316 /* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ 1317 /*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS 1318 /SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash 1319 ..*/ 1320 #define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF 1321 #define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) 1322 #define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF 1323 #define SPI_MEM_WAIT_PESR_COMMAND_S 16 1324 /* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ 1325 /*description: Program/Erase suspend command..*/ 1326 #define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF 1327 #define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) 1328 #define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF 1329 #define SPI_MEM_FLASH_PES_COMMAND_S 0 1330 1331 #define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) 1332 /* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ 1333 /*description: Program/Erase resume command..*/ 1334 #define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF 1335 #define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) 1336 #define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF 1337 #define SPI_MEM_FLASH_PER_COMMAND_S 16 1338 /* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1339 /*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng 1340 th of Program/Erase Suspend/Resume command is 8..*/ 1341 #define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) 1342 #define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) 1343 #define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 1344 #define SPI_MEM_FLASH_PESR_CMD_2B_S 15 1345 /* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1346 /*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ 1347 #define SPI_MEM_SPI0_LOCK_EN (BIT(7)) 1348 #define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) 1349 #define SPI_MEM_SPI0_LOCK_EN_V 0x1 1350 #define SPI_MEM_SPI0_LOCK_EN_S 7 1351 /* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1352 /*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ 1353 RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM 1354 _CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ 1355 #define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) 1356 #define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) 1357 #define SPI_MEM_FLASH_PES_DLY_128_V 0x1 1358 #define SPI_MEM_FLASH_PES_DLY_128_S 6 1359 /* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1360 /*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ 1361 RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM 1362 _CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ 1363 #define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) 1364 #define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) 1365 #define SPI_MEM_FLASH_PER_DLY_128_V 0x1 1366 #define SPI_MEM_FLASH_PER_DLY_128_S 5 1367 /* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1368 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com 1369 mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles 1370 after DP command is sent..*/ 1371 #define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) 1372 #define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) 1373 #define SPI_MEM_FLASH_DP_DLY_128_V 0x1 1374 #define SPI_MEM_FLASH_DP_DLY_128_S 4 1375 /* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1376 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co 1377 mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles 1378 after RES command is sent..*/ 1379 #define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) 1380 #define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) 1381 #define SPI_MEM_FLASH_RES_DLY_128_V 0x1 1382 #define SPI_MEM_FLASH_RES_DLY_128_S 3 1383 /* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1384 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co 1385 mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles 1386 after HPM command is sent..*/ 1387 #define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) 1388 #define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) 1389 #define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 1390 #define SPI_MEM_FLASH_HPM_DLY_128_S 2 1391 /* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1392 /*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: 1393 SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ 1394 #define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) 1395 #define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) 1396 #define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 1397 #define SPI_MEM_WAIT_PESR_CMD_2B_S 1 1398 /* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ 1399 /*description: The status of flash suspend, only used in SPI1..*/ 1400 #define SPI_MEM_FLASH_SUS (BIT(0)) 1401 #define SPI_MEM_FLASH_SUS_M (BIT(0)) 1402 #define SPI_MEM_FLASH_SUS_V 0x1 1403 #define SPI_MEM_FLASH_SUS_S 0 1404 1405 #define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) 1406 /* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1407 /*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ 1408 #define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) 1409 #define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) 1410 #define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 1411 #define SPI_MEM_BROWN_OUT_INT_ENA_S 10 1412 /* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */ 1413 /*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ 1414 #define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) 1415 #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (BIT(9)) 1416 #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x1 1417 #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 1418 /* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */ 1419 /*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ 1420 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) 1421 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) 1422 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 1423 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 1424 /* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1425 /*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ 1426 #define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) 1427 #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) 1428 #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 1429 #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 1430 /* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1431 /*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ 1432 #define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) 1433 #define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) 1434 #define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 1435 #define SPI_MEM_PMS_REJECT_INT_ENA_S 6 1436 /* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */ 1437 /*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ 1438 #define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) 1439 #define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) 1440 #define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 1441 #define SPI_MEM_ECC_ERR_INT_ENA_S 5 1442 /* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1443 /*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ 1444 #define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) 1445 #define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) 1446 #define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 1447 #define SPI_MEM_MST_ST_END_INT_ENA_S 4 1448 /* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1449 /*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ 1450 #define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) 1451 #define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) 1452 #define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 1453 #define SPI_MEM_SLV_ST_END_INT_ENA_S 3 1454 /* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1455 /*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ 1456 #define SPI_MEM_WPE_END_INT_ENA (BIT(2)) 1457 #define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) 1458 #define SPI_MEM_WPE_END_INT_ENA_V 0x1 1459 #define SPI_MEM_WPE_END_INT_ENA_S 2 1460 /* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1461 /*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ 1462 #define SPI_MEM_PES_END_INT_ENA (BIT(1)) 1463 #define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) 1464 #define SPI_MEM_PES_END_INT_ENA_V 0x1 1465 #define SPI_MEM_PES_END_INT_ENA_S 1 1466 /* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1467 /*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ 1468 #define SPI_MEM_PER_END_INT_ENA (BIT(0)) 1469 #define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) 1470 #define SPI_MEM_PER_END_INT_ENA_V 0x1 1471 #define SPI_MEM_PER_END_INT_ENA_S 0 1472 1473 #define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) 1474 /* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ 1475 /*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ 1476 #define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) 1477 #define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) 1478 #define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 1479 #define SPI_MEM_BROWN_OUT_INT_CLR_S 10 1480 /* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */ 1481 /*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ 1482 #define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) 1483 #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) 1484 #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 1485 #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 1486 /* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */ 1487 /*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ 1488 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) 1489 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) 1490 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 1491 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 1492 /* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ 1493 /*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ 1494 #define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) 1495 #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) 1496 #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 1497 #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 1498 /* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ 1499 /*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ 1500 #define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) 1501 #define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) 1502 #define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 1503 #define SPI_MEM_PMS_REJECT_INT_CLR_S 6 1504 /* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */ 1505 /*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ 1506 #define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) 1507 #define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) 1508 #define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 1509 #define SPI_MEM_ECC_ERR_INT_CLR_S 5 1510 /* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ 1511 /*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ 1512 #define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) 1513 #define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) 1514 #define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 1515 #define SPI_MEM_MST_ST_END_INT_CLR_S 4 1516 /* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ 1517 /*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ 1518 #define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) 1519 #define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) 1520 #define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 1521 #define SPI_MEM_SLV_ST_END_INT_CLR_S 3 1522 /* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ 1523 /*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ 1524 #define SPI_MEM_WPE_END_INT_CLR (BIT(2)) 1525 #define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) 1526 #define SPI_MEM_WPE_END_INT_CLR_V 0x1 1527 #define SPI_MEM_WPE_END_INT_CLR_S 2 1528 /* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ 1529 /*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ 1530 #define SPI_MEM_PES_END_INT_CLR (BIT(1)) 1531 #define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) 1532 #define SPI_MEM_PES_END_INT_CLR_V 0x1 1533 #define SPI_MEM_PES_END_INT_CLR_S 1 1534 /* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ 1535 /*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ 1536 #define SPI_MEM_PER_END_INT_CLR (BIT(0)) 1537 #define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) 1538 #define SPI_MEM_PER_END_INT_CLR_V 0x1 1539 #define SPI_MEM_PER_END_INT_CLR_S 0 1540 1541 #define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) 1542 /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ 1543 /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that 1544 chip is loosing power and RTC module sends out brown out close flash request to 1545 SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered 1546 and MSPI returns to idle state. 0: Others..*/ 1547 #define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) 1548 #define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) 1549 #define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 1550 #define SPI_MEM_BROWN_OUT_INT_RAW_S 10 1551 /* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */ 1552 /*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write 1553 address is invalid by compared to MMU configuration. 0: Others..*/ 1554 #define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) 1555 #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) 1556 #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 1557 #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 1558 /* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */ 1559 /*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr 1560 ite flash request is received. 0: Others..*/ 1561 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) 1562 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) 1563 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 1564 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 1565 /* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ 1566 /*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read 1567 address is invalid by compared to MMU configuration. 0: Others..*/ 1568 #define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) 1569 #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) 1570 #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 1571 #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 1572 /* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ 1573 /*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access 1574 is rejected. 0: Others..*/ 1575 #define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) 1576 #define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) 1577 #define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 1578 #define SPI_MEM_PMS_REJECT_INT_RAW_S 6 1579 /* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */ 1580 /*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s 1581 et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error 1582 times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM 1583 . When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t 1584 his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq 1585 ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP 1586 I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times 1587 of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E 1588 RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare 1589 d, this bit will not be triggered..*/ 1590 #define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) 1591 #define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) 1592 #define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 1593 #define SPI_MEM_ECC_ERR_INT_RAW_S 5 1594 /* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ 1595 /*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st 1596 is changed from non idle state to idle state. 0: Others..*/ 1597 #define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) 1598 #define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) 1599 #define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 1600 #define SPI_MEM_MST_ST_END_INT_RAW_S 4 1601 /* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ 1602 /*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st 1603 is changed from non idle state to idle state. It means that SPI_CS raises high. 1604 0: Others.*/ 1605 #define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) 1606 #define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) 1607 #define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 1608 #define SPI_MEM_SLV_ST_END_INT_RAW_S 3 1609 /* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ 1610 /*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C 1611 E is sent and flash is already idle. 0: Others..*/ 1612 #define SPI_MEM_WPE_END_INT_RAW (BIT(2)) 1613 #define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) 1614 #define SPI_MEM_WPE_END_INT_RAW_V 0x1 1615 #define SPI_MEM_WPE_END_INT_RAW_S 2 1616 /* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ 1617 /*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com 1618 mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ 1619 #define SPI_MEM_PES_END_INT_RAW (BIT(1)) 1620 #define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) 1621 #define SPI_MEM_PES_END_INT_RAW_V 0x1 1622 #define SPI_MEM_PES_END_INT_RAW_S 1 1623 /* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ 1624 /*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com 1625 mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ 1626 #define SPI_MEM_PER_END_INT_RAW (BIT(0)) 1627 #define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) 1628 #define SPI_MEM_PER_END_INT_RAW_V 0x1 1629 #define SPI_MEM_PER_END_INT_RAW_S 0 1630 1631 #define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) 1632 /* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 1633 /*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ 1634 #define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) 1635 #define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) 1636 #define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 1637 #define SPI_MEM_BROWN_OUT_INT_ST_S 10 1638 /* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */ 1639 /*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ 1640 #define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) 1641 #define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) 1642 #define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 1643 #define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 1644 /* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */ 1645 /*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ 1646 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) 1647 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) 1648 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 1649 #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 1650 /* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 1651 /*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ 1652 #define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) 1653 #define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) 1654 #define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 1655 #define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 1656 /* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 1657 /*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ 1658 #define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) 1659 #define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) 1660 #define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 1661 #define SPI_MEM_PMS_REJECT_INT_ST_S 6 1662 /* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */ 1663 /*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ 1664 #define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) 1665 #define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) 1666 #define SPI_MEM_ECC_ERR_INT_ST_V 0x1 1667 #define SPI_MEM_ECC_ERR_INT_ST_S 5 1668 /* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1669 /*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ 1670 #define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) 1671 #define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) 1672 #define SPI_MEM_MST_ST_END_INT_ST_V 0x1 1673 #define SPI_MEM_MST_ST_END_INT_ST_S 4 1674 /* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1675 /*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ 1676 #define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) 1677 #define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) 1678 #define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 1679 #define SPI_MEM_SLV_ST_END_INT_ST_S 3 1680 /* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1681 /*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ 1682 #define SPI_MEM_WPE_END_INT_ST (BIT(2)) 1683 #define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) 1684 #define SPI_MEM_WPE_END_INT_ST_V 0x1 1685 #define SPI_MEM_WPE_END_INT_ST_S 2 1686 /* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1687 /*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ 1688 #define SPI_MEM_PES_END_INT_ST (BIT(1)) 1689 #define SPI_MEM_PES_END_INT_ST_M (BIT(1)) 1690 #define SPI_MEM_PES_END_INT_ST_V 0x1 1691 #define SPI_MEM_PES_END_INT_ST_S 1 1692 /* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1693 /*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ 1694 #define SPI_MEM_PER_END_INT_ST (BIT(0)) 1695 #define SPI_MEM_PER_END_INT_ST_M (BIT(0)) 1696 #define SPI_MEM_PER_END_INT_ST_V 0x1 1697 #define SPI_MEM_PER_END_INT_ST_S 0 1698 1699 #define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) 1700 /* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ 1701 /*description: Set this bit to enable HyperRAM address out when accesses to flash, which means 1702 ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ 1703 #define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) 1704 #define SPI_MEM_FMEM_HYPERBUS_CA_M (BIT(30)) 1705 #define SPI_MEM_FMEM_HYPERBUS_CA_V 0x1 1706 #define SPI_MEM_FMEM_HYPERBUS_CA_S 30 1707 /* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ 1708 /*description: Set this bit to enable octa_ram address out when accesses to flash, which means 1709 ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} 1710 ..*/ 1711 #define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) 1712 #define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (BIT(29)) 1713 #define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x1 1714 #define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 1715 /* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ 1716 /*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ 1717 #define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) 1718 #define SPI_MEM_FMEM_CLK_DIFF_INV_M (BIT(28)) 1719 #define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x1 1720 #define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 1721 /* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ 1722 /*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a 1723 ccesses flash or SPI1 accesses flash or sram..*/ 1724 #define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) 1725 #define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) 1726 #define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x1 1727 #define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 1728 /* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ 1729 /*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR 1730 ..*/ 1731 #define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) 1732 #define SPI_MEM_FMEM_DQS_CA_IN_M (BIT(26)) 1733 #define SPI_MEM_FMEM_DQS_CA_IN_V 0x1 1734 #define SPI_MEM_FMEM_DQS_CA_IN_S 26 1735 /* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ 1736 /*description: Set this bit to enable the differential SPI_CLK#..*/ 1737 #define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) 1738 #define SPI_MEM_FMEM_CLK_DIFF_EN_M (BIT(24)) 1739 #define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x1 1740 #define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 1741 /* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ 1742 /*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi 1743 0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or 1744 SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n 1745 egative edge of SPI_DQS..*/ 1746 #define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) 1747 #define SPI_MEM_FMEM_DDR_DQS_LOOP_M (BIT(21)) 1748 #define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x1 1749 #define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 1750 /* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ 1751 /*description: The delay number of data strobe which from memory based on SPI clock..*/ 1752 #define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007F 1753 #define SPI_MEM_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S)) 1754 #define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x7F 1755 #define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 1756 /* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ 1757 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when 1758 accesses to flash..*/ 1759 #define SPI_MEM_FMEM_RX_DDR_MSK_EN (BIT(13)) 1760 #define SPI_MEM_FMEM_RX_DDR_MSK_EN_M (BIT(13)) 1761 #define SPI_MEM_FMEM_RX_DDR_MSK_EN_V 0x1 1762 #define SPI_MEM_FMEM_RX_DDR_MSK_EN_S 13 1763 /* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ 1764 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when 1765 accesses to flash..*/ 1766 #define SPI_MEM_FMEM_TX_DDR_MSK_EN (BIT(12)) 1767 #define SPI_MEM_FMEM_TX_DDR_MSK_EN_M (BIT(12)) 1768 #define SPI_MEM_FMEM_TX_DDR_MSK_EN_V 0x1 1769 #define SPI_MEM_FMEM_TX_DDR_MSK_EN_S 12 1770 /* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ 1771 /*description: It is the minimum output data length in the panda device..*/ 1772 #define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007F 1773 #define SPI_MEM_FMEM_OUTMINBYTELEN_M ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S)) 1774 #define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x7F 1775 #define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 1776 /* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ 1777 /*description: the bit is used to disable dual edge in command phase when DDR mode..*/ 1778 #define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) 1779 #define SPI_MEM_FMEM_DDR_CMD_DIS_M (BIT(4)) 1780 #define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x1 1781 #define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 1782 /* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ 1783 /*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ 1784 #define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) 1785 #define SPI_MEM_FMEM_DDR_WDAT_SWP_M (BIT(3)) 1786 #define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x1 1787 #define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 1788 /* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ 1789 /*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ 1790 #define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) 1791 #define SPI_MEM_FMEM_DDR_RDAT_SWP_M (BIT(2)) 1792 #define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x1 1793 #define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 1794 /* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ 1795 /*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ 1796 #define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) 1797 #define SPI_MEM_FMEM_VAR_DUMMY_M (BIT(1)) 1798 #define SPI_MEM_FMEM_VAR_DUMMY_V 0x1 1799 #define SPI_MEM_FMEM_VAR_DUMMY_S 1 1800 /* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ 1801 /*description: 1: in DDR mode, 0 in SDR mode.*/ 1802 #define SPI_MEM_FMEM_DDR_EN (BIT(0)) 1803 #define SPI_MEM_FMEM_DDR_EN_M (BIT(0)) 1804 #define SPI_MEM_FMEM_DDR_EN_V 0x1 1805 #define SPI_MEM_FMEM_DDR_EN_S 0 1806 1807 #define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) 1808 /* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ 1809 /*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which 1810 means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 1811 ]}..*/ 1812 #define SPI_MEM_SMEM_HYPERBUS_CA (BIT(30)) 1813 #define SPI_MEM_SMEM_HYPERBUS_CA_M (BIT(30)) 1814 #define SPI_MEM_SMEM_HYPERBUS_CA_V 0x1 1815 #define SPI_MEM_SMEM_HYPERBUS_CA_S 30 1816 /* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ 1817 /*description: Set this bit to enable octa_ram address out when accesses to external RAM, which 1818 means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] 1819 , 1'b0}..*/ 1820 #define SPI_MEM_SMEM_OCTA_RAM_ADDR (BIT(29)) 1821 #define SPI_MEM_SMEM_OCTA_RAM_ADDR_M (BIT(29)) 1822 #define SPI_MEM_SMEM_OCTA_RAM_ADDR_V 0x1 1823 #define SPI_MEM_SMEM_OCTA_RAM_ADDR_S 29 1824 /* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ 1825 /*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ 1826 #define SPI_MEM_SMEM_CLK_DIFF_INV (BIT(28)) 1827 #define SPI_MEM_SMEM_CLK_DIFF_INV_M (BIT(28)) 1828 #define SPI_MEM_SMEM_CLK_DIFF_INV_V 0x1 1829 #define SPI_MEM_SMEM_CLK_DIFF_INV_S 28 1830 /* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ 1831 /*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a 1832 ccesses flash or SPI1 accesses flash or sram..*/ 1833 #define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) 1834 #define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) 1835 #define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V 0x1 1836 #define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S 27 1837 /* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ 1838 /*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR 1839 ..*/ 1840 #define SPI_MEM_SMEM_DQS_CA_IN (BIT(26)) 1841 #define SPI_MEM_SMEM_DQS_CA_IN_M (BIT(26)) 1842 #define SPI_MEM_SMEM_DQS_CA_IN_V 0x1 1843 #define SPI_MEM_SMEM_DQS_CA_IN_S 26 1844 /* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ 1845 /*description: Set this bit to enable the differential SPI_CLK#..*/ 1846 #define SPI_MEM_SMEM_CLK_DIFF_EN (BIT(24)) 1847 #define SPI_MEM_SMEM_CLK_DIFF_EN_M (BIT(24)) 1848 #define SPI_MEM_SMEM_CLK_DIFF_EN_V 0x1 1849 #define SPI_MEM_SMEM_CLK_DIFF_EN_S 24 1850 /* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ 1851 /*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi 1852 0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or 1853 SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n 1854 egative edge of SPI_DQS..*/ 1855 #define SPI_MEM_SMEM_DDR_DQS_LOOP (BIT(21)) 1856 #define SPI_MEM_SMEM_DDR_DQS_LOOP_M (BIT(21)) 1857 #define SPI_MEM_SMEM_DDR_DQS_LOOP_V 0x1 1858 #define SPI_MEM_SMEM_DDR_DQS_LOOP_S 21 1859 /* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ 1860 /*description: The delay number of data strobe which from memory based on SPI clock..*/ 1861 #define SPI_MEM_SMEM_USR_DDR_DQS_THD 0x0000007F 1862 #define SPI_MEM_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S)) 1863 #define SPI_MEM_SMEM_USR_DDR_DQS_THD_V 0x7F 1864 #define SPI_MEM_SMEM_USR_DDR_DQS_THD_S 14 1865 /* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ 1866 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when 1867 accesses to external RAM..*/ 1868 #define SPI_MEM_SMEM_RX_DDR_MSK_EN (BIT(13)) 1869 #define SPI_MEM_SMEM_RX_DDR_MSK_EN_M (BIT(13)) 1870 #define SPI_MEM_SMEM_RX_DDR_MSK_EN_V 0x1 1871 #define SPI_MEM_SMEM_RX_DDR_MSK_EN_S 13 1872 /* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ 1873 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when 1874 accesses to external RAM..*/ 1875 #define SPI_MEM_SMEM_TX_DDR_MSK_EN (BIT(12)) 1876 #define SPI_MEM_SMEM_TX_DDR_MSK_EN_M (BIT(12)) 1877 #define SPI_MEM_SMEM_TX_DDR_MSK_EN_V 0x1 1878 #define SPI_MEM_SMEM_TX_DDR_MSK_EN_S 12 1879 /* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ 1880 /*description: It is the minimum output data length in the DDR psram..*/ 1881 #define SPI_MEM_SMEM_OUTMINBYTELEN 0x0000007F 1882 #define SPI_MEM_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S)) 1883 #define SPI_MEM_SMEM_OUTMINBYTELEN_V 0x7F 1884 #define SPI_MEM_SMEM_OUTMINBYTELEN_S 5 1885 /* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ 1886 /*description: the bit is used to disable dual edge in command phase when DDR mode..*/ 1887 #define SPI_MEM_SMEM_DDR_CMD_DIS (BIT(4)) 1888 #define SPI_MEM_SMEM_DDR_CMD_DIS_M (BIT(4)) 1889 #define SPI_MEM_SMEM_DDR_CMD_DIS_V 0x1 1890 #define SPI_MEM_SMEM_DDR_CMD_DIS_S 4 1891 /* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ 1892 /*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ 1893 #define SPI_MEM_SMEM_DDR_WDAT_SWP (BIT(3)) 1894 #define SPI_MEM_SMEM_DDR_WDAT_SWP_M (BIT(3)) 1895 #define SPI_MEM_SMEM_DDR_WDAT_SWP_V 0x1 1896 #define SPI_MEM_SMEM_DDR_WDAT_SWP_S 3 1897 /* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ 1898 /*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ 1899 #define SPI_MEM_SMEM_DDR_RDAT_SWP (BIT(2)) 1900 #define SPI_MEM_SMEM_DDR_RDAT_SWP_M (BIT(2)) 1901 #define SPI_MEM_SMEM_DDR_RDAT_SWP_V 0x1 1902 #define SPI_MEM_SMEM_DDR_RDAT_SWP_S 2 1903 /* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ 1904 /*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ 1905 #define SPI_MEM_SMEM_VAR_DUMMY (BIT(1)) 1906 #define SPI_MEM_SMEM_VAR_DUMMY_M (BIT(1)) 1907 #define SPI_MEM_SMEM_VAR_DUMMY_V 0x1 1908 #define SPI_MEM_SMEM_VAR_DUMMY_S 1 1909 /* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ 1910 /*description: 1: in DDR mode, 0 in SDR mode.*/ 1911 #define SPI_MEM_SMEM_DDR_EN (BIT(0)) 1912 #define SPI_MEM_SMEM_DDR_EN_M (BIT(0)) 1913 #define SPI_MEM_SMEM_DDR_EN_V 0x1 1914 #define SPI_MEM_SMEM_DDR_EN_S 0 1915 1916 #define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) 1917 /* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1918 /*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash 1919 ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ 1920 PMS$n_SIZE_REG..*/ 1921 #define SPI_MEM_FMEM_PMS0_ECC (BIT(2)) 1922 #define SPI_MEM_FMEM_PMS0_ECC_M (BIT(2)) 1923 #define SPI_MEM_FMEM_PMS0_ECC_V 0x1 1924 #define SPI_MEM_FMEM_PMS0_ECC_S 2 1925 /* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1926 /*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ 1927 #define SPI_MEM_FMEM_PMS0_WR_ATTR (BIT(1)) 1928 #define SPI_MEM_FMEM_PMS0_WR_ATTR_M (BIT(1)) 1929 #define SPI_MEM_FMEM_PMS0_WR_ATTR_V 0x1 1930 #define SPI_MEM_FMEM_PMS0_WR_ATTR_S 1 1931 /* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 1932 /*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ 1933 #define SPI_MEM_FMEM_PMS0_RD_ATTR (BIT(0)) 1934 #define SPI_MEM_FMEM_PMS0_RD_ATTR_M (BIT(0)) 1935 #define SPI_MEM_FMEM_PMS0_RD_ATTR_V 0x1 1936 #define SPI_MEM_FMEM_PMS0_RD_ATTR_S 0 1937 1938 #define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) 1939 /* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1940 /*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash 1941 ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ 1942 PMS$n_SIZE_REG..*/ 1943 #define SPI_MEM_FMEM_PMS1_ECC (BIT(2)) 1944 #define SPI_MEM_FMEM_PMS1_ECC_M (BIT(2)) 1945 #define SPI_MEM_FMEM_PMS1_ECC_V 0x1 1946 #define SPI_MEM_FMEM_PMS1_ECC_S 2 1947 /* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1948 /*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ 1949 #define SPI_MEM_FMEM_PMS1_WR_ATTR (BIT(1)) 1950 #define SPI_MEM_FMEM_PMS1_WR_ATTR_M (BIT(1)) 1951 #define SPI_MEM_FMEM_PMS1_WR_ATTR_V 0x1 1952 #define SPI_MEM_FMEM_PMS1_WR_ATTR_S 1 1953 /* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 1954 /*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ 1955 #define SPI_MEM_FMEM_PMS1_RD_ATTR (BIT(0)) 1956 #define SPI_MEM_FMEM_PMS1_RD_ATTR_M (BIT(0)) 1957 #define SPI_MEM_FMEM_PMS1_RD_ATTR_V 0x1 1958 #define SPI_MEM_FMEM_PMS1_RD_ATTR_S 0 1959 1960 #define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) 1961 /* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1962 /*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash 1963 ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ 1964 PMS$n_SIZE_REG..*/ 1965 #define SPI_MEM_FMEM_PMS2_ECC (BIT(2)) 1966 #define SPI_MEM_FMEM_PMS2_ECC_M (BIT(2)) 1967 #define SPI_MEM_FMEM_PMS2_ECC_V 0x1 1968 #define SPI_MEM_FMEM_PMS2_ECC_S 2 1969 /* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1970 /*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ 1971 #define SPI_MEM_FMEM_PMS2_WR_ATTR (BIT(1)) 1972 #define SPI_MEM_FMEM_PMS2_WR_ATTR_M (BIT(1)) 1973 #define SPI_MEM_FMEM_PMS2_WR_ATTR_V 0x1 1974 #define SPI_MEM_FMEM_PMS2_WR_ATTR_S 1 1975 /* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 1976 /*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ 1977 #define SPI_MEM_FMEM_PMS2_RD_ATTR (BIT(0)) 1978 #define SPI_MEM_FMEM_PMS2_RD_ATTR_M (BIT(0)) 1979 #define SPI_MEM_FMEM_PMS2_RD_ATTR_V 0x1 1980 #define SPI_MEM_FMEM_PMS2_RD_ATTR_S 0 1981 1982 #define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) 1983 /* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1984 /*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash 1985 ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ 1986 PMS$n_SIZE_REG..*/ 1987 #define SPI_MEM_FMEM_PMS3_ECC (BIT(2)) 1988 #define SPI_MEM_FMEM_PMS3_ECC_M (BIT(2)) 1989 #define SPI_MEM_FMEM_PMS3_ECC_V 0x1 1990 #define SPI_MEM_FMEM_PMS3_ECC_S 2 1991 /* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1992 /*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ 1993 #define SPI_MEM_FMEM_PMS3_WR_ATTR (BIT(1)) 1994 #define SPI_MEM_FMEM_PMS3_WR_ATTR_M (BIT(1)) 1995 #define SPI_MEM_FMEM_PMS3_WR_ATTR_V 0x1 1996 #define SPI_MEM_FMEM_PMS3_WR_ATTR_S 1 1997 /* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 1998 /*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ 1999 #define SPI_MEM_FMEM_PMS3_RD_ATTR (BIT(0)) 2000 #define SPI_MEM_FMEM_PMS3_RD_ATTR_M (BIT(0)) 2001 #define SPI_MEM_FMEM_PMS3_RD_ATTR_V 0x1 2002 #define SPI_MEM_FMEM_PMS3_RD_ATTR_S 0 2003 2004 #define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) 2005 /* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ 2006 /*description: SPI1 flash ACE section $n start address value.*/ 2007 #define SPI_MEM_FMEM_PMS0_ADDR_S 0x03FFFFFF 2008 #define SPI_MEM_FMEM_PMS0_ADDR_S_M ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S)) 2009 #define SPI_MEM_FMEM_PMS0_ADDR_S_V 0x3FFFFFF 2010 #define SPI_MEM_FMEM_PMS0_ADDR_S_S 0 2011 2012 #define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) 2013 /* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ 2014 /*description: SPI1 flash ACE section $n start address value.*/ 2015 #define SPI_MEM_FMEM_PMS1_ADDR_S 0x03FFFFFF 2016 #define SPI_MEM_FMEM_PMS1_ADDR_S_M ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S)) 2017 #define SPI_MEM_FMEM_PMS1_ADDR_S_V 0x3FFFFFF 2018 #define SPI_MEM_FMEM_PMS1_ADDR_S_S 0 2019 2020 #define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) 2021 /* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ 2022 /*description: SPI1 flash ACE section $n start address value.*/ 2023 #define SPI_MEM_FMEM_PMS2_ADDR_S 0x03FFFFFF 2024 #define SPI_MEM_FMEM_PMS2_ADDR_S_M ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S)) 2025 #define SPI_MEM_FMEM_PMS2_ADDR_S_V 0x3FFFFFF 2026 #define SPI_MEM_FMEM_PMS2_ADDR_S_S 0 2027 2028 #define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) 2029 /* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ 2030 /*description: SPI1 flash ACE section $n start address value.*/ 2031 #define SPI_MEM_FMEM_PMS3_ADDR_S 0x03FFFFFF 2032 #define SPI_MEM_FMEM_PMS3_ADDR_S_M ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S)) 2033 #define SPI_MEM_FMEM_PMS3_ADDR_S_V 0x3FFFFFF 2034 #define SPI_MEM_FMEM_PMS3_ADDR_S_S 0 2035 2036 #define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) 2037 /* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2038 /*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS 2039 $n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ 2040 #define SPI_MEM_FMEM_PMS0_SIZE 0x00003FFF 2041 #define SPI_MEM_FMEM_PMS0_SIZE_M ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S)) 2042 #define SPI_MEM_FMEM_PMS0_SIZE_V 0x3FFF 2043 #define SPI_MEM_FMEM_PMS0_SIZE_S 0 2044 2045 #define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) 2046 /* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2047 /*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS 2048 $n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ 2049 #define SPI_MEM_FMEM_PMS1_SIZE 0x00003FFF 2050 #define SPI_MEM_FMEM_PMS1_SIZE_M ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S)) 2051 #define SPI_MEM_FMEM_PMS1_SIZE_V 0x3FFF 2052 #define SPI_MEM_FMEM_PMS1_SIZE_S 0 2053 2054 #define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) 2055 /* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2056 /*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS 2057 $n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ 2058 #define SPI_MEM_FMEM_PMS2_SIZE 0x00003FFF 2059 #define SPI_MEM_FMEM_PMS2_SIZE_M ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S)) 2060 #define SPI_MEM_FMEM_PMS2_SIZE_V 0x3FFF 2061 #define SPI_MEM_FMEM_PMS2_SIZE_S 0 2062 2063 #define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) 2064 /* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2065 /*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS 2066 $n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ 2067 #define SPI_MEM_FMEM_PMS3_SIZE 0x00003FFF 2068 #define SPI_MEM_FMEM_PMS3_SIZE_M ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S)) 2069 #define SPI_MEM_FMEM_PMS3_SIZE_V 0x3FFF 2070 #define SPI_MEM_FMEM_PMS3_SIZE_S 0 2071 2072 #define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) 2073 /* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2074 /*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th 2075 e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG 2076 and SPI_SMEM_PMS$n_SIZE_REG..*/ 2077 #define SPI_MEM_SMEM_PMS0_ECC (BIT(2)) 2078 #define SPI_MEM_SMEM_PMS0_ECC_M (BIT(2)) 2079 #define SPI_MEM_SMEM_PMS0_ECC_V 0x1 2080 #define SPI_MEM_SMEM_PMS0_ECC_S 2 2081 /* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 2082 /*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ 2083 #define SPI_MEM_SMEM_PMS0_WR_ATTR (BIT(1)) 2084 #define SPI_MEM_SMEM_PMS0_WR_ATTR_M (BIT(1)) 2085 #define SPI_MEM_SMEM_PMS0_WR_ATTR_V 0x1 2086 #define SPI_MEM_SMEM_PMS0_WR_ATTR_S 1 2087 /* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 2088 /*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ 2089 #define SPI_MEM_SMEM_PMS0_RD_ATTR (BIT(0)) 2090 #define SPI_MEM_SMEM_PMS0_RD_ATTR_M (BIT(0)) 2091 #define SPI_MEM_SMEM_PMS0_RD_ATTR_V 0x1 2092 #define SPI_MEM_SMEM_PMS0_RD_ATTR_S 0 2093 2094 #define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) 2095 /* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2096 /*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th 2097 e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG 2098 and SPI_SMEM_PMS$n_SIZE_REG..*/ 2099 #define SPI_MEM_SMEM_PMS1_ECC (BIT(2)) 2100 #define SPI_MEM_SMEM_PMS1_ECC_M (BIT(2)) 2101 #define SPI_MEM_SMEM_PMS1_ECC_V 0x1 2102 #define SPI_MEM_SMEM_PMS1_ECC_S 2 2103 /* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 2104 /*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ 2105 #define SPI_MEM_SMEM_PMS1_WR_ATTR (BIT(1)) 2106 #define SPI_MEM_SMEM_PMS1_WR_ATTR_M (BIT(1)) 2107 #define SPI_MEM_SMEM_PMS1_WR_ATTR_V 0x1 2108 #define SPI_MEM_SMEM_PMS1_WR_ATTR_S 1 2109 /* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 2110 /*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ 2111 #define SPI_MEM_SMEM_PMS1_RD_ATTR (BIT(0)) 2112 #define SPI_MEM_SMEM_PMS1_RD_ATTR_M (BIT(0)) 2113 #define SPI_MEM_SMEM_PMS1_RD_ATTR_V 0x1 2114 #define SPI_MEM_SMEM_PMS1_RD_ATTR_S 0 2115 2116 #define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) 2117 /* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2118 /*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th 2119 e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG 2120 and SPI_SMEM_PMS$n_SIZE_REG..*/ 2121 #define SPI_MEM_SMEM_PMS2_ECC (BIT(2)) 2122 #define SPI_MEM_SMEM_PMS2_ECC_M (BIT(2)) 2123 #define SPI_MEM_SMEM_PMS2_ECC_V 0x1 2124 #define SPI_MEM_SMEM_PMS2_ECC_S 2 2125 /* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 2126 /*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ 2127 #define SPI_MEM_SMEM_PMS2_WR_ATTR (BIT(1)) 2128 #define SPI_MEM_SMEM_PMS2_WR_ATTR_M (BIT(1)) 2129 #define SPI_MEM_SMEM_PMS2_WR_ATTR_V 0x1 2130 #define SPI_MEM_SMEM_PMS2_WR_ATTR_S 1 2131 /* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 2132 /*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ 2133 #define SPI_MEM_SMEM_PMS2_RD_ATTR (BIT(0)) 2134 #define SPI_MEM_SMEM_PMS2_RD_ATTR_M (BIT(0)) 2135 #define SPI_MEM_SMEM_PMS2_RD_ATTR_V 0x1 2136 #define SPI_MEM_SMEM_PMS2_RD_ATTR_S 0 2137 2138 #define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) 2139 /* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2140 /*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th 2141 e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG 2142 and SPI_SMEM_PMS$n_SIZE_REG..*/ 2143 #define SPI_MEM_SMEM_PMS3_ECC (BIT(2)) 2144 #define SPI_MEM_SMEM_PMS3_ECC_M (BIT(2)) 2145 #define SPI_MEM_SMEM_PMS3_ECC_V 0x1 2146 #define SPI_MEM_SMEM_PMS3_ECC_S 2 2147 /* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ 2148 /*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ 2149 #define SPI_MEM_SMEM_PMS3_WR_ATTR (BIT(1)) 2150 #define SPI_MEM_SMEM_PMS3_WR_ATTR_M (BIT(1)) 2151 #define SPI_MEM_SMEM_PMS3_WR_ATTR_V 0x1 2152 #define SPI_MEM_SMEM_PMS3_WR_ATTR_S 1 2153 /* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ 2154 /*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ 2155 #define SPI_MEM_SMEM_PMS3_RD_ATTR (BIT(0)) 2156 #define SPI_MEM_SMEM_PMS3_RD_ATTR_M (BIT(0)) 2157 #define SPI_MEM_SMEM_PMS3_RD_ATTR_V 0x1 2158 #define SPI_MEM_SMEM_PMS3_RD_ATTR_S 0 2159 2160 #define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) 2161 /* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ 2162 /*description: SPI1 external RAM ACE section $n start address value.*/ 2163 #define SPI_MEM_SMEM_PMS0_ADDR_S 0x03FFFFFF 2164 #define SPI_MEM_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S)) 2165 #define SPI_MEM_SMEM_PMS0_ADDR_S_V 0x3FFFFFF 2166 #define SPI_MEM_SMEM_PMS0_ADDR_S_S 0 2167 2168 #define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) 2169 /* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ 2170 /*description: SPI1 external RAM ACE section $n start address value.*/ 2171 #define SPI_MEM_SMEM_PMS1_ADDR_S 0x03FFFFFF 2172 #define SPI_MEM_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S)) 2173 #define SPI_MEM_SMEM_PMS1_ADDR_S_V 0x3FFFFFF 2174 #define SPI_MEM_SMEM_PMS1_ADDR_S_S 0 2175 2176 #define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) 2177 /* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ 2178 /*description: SPI1 external RAM ACE section $n start address value.*/ 2179 #define SPI_MEM_SMEM_PMS2_ADDR_S 0x03FFFFFF 2180 #define SPI_MEM_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S)) 2181 #define SPI_MEM_SMEM_PMS2_ADDR_S_V 0x3FFFFFF 2182 #define SPI_MEM_SMEM_PMS2_ADDR_S_S 0 2183 2184 #define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) 2185 /* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ 2186 /*description: SPI1 external RAM ACE section $n start address value.*/ 2187 #define SPI_MEM_SMEM_PMS3_ADDR_S 0x03FFFFFF 2188 #define SPI_MEM_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S)) 2189 #define SPI_MEM_SMEM_PMS3_ADDR_S_V 0x3FFFFFF 2190 #define SPI_MEM_SMEM_PMS3_ADDR_S_S 0 2191 2192 #define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) 2193 /* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2194 /*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S 2195 MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ 2196 #define SPI_MEM_SMEM_PMS0_SIZE 0x00003FFF 2197 #define SPI_MEM_SMEM_PMS0_SIZE_M ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S)) 2198 #define SPI_MEM_SMEM_PMS0_SIZE_V 0x3FFF 2199 #define SPI_MEM_SMEM_PMS0_SIZE_S 0 2200 2201 #define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) 2202 /* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2203 /*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S 2204 MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ 2205 #define SPI_MEM_SMEM_PMS1_SIZE 0x00003FFF 2206 #define SPI_MEM_SMEM_PMS1_SIZE_M ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S)) 2207 #define SPI_MEM_SMEM_PMS1_SIZE_V 0x3FFF 2208 #define SPI_MEM_SMEM_PMS1_SIZE_S 0 2209 2210 #define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) 2211 /* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2212 /*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S 2213 MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ 2214 #define SPI_MEM_SMEM_PMS2_SIZE 0x00003FFF 2215 #define SPI_MEM_SMEM_PMS2_SIZE_M ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S)) 2216 #define SPI_MEM_SMEM_PMS2_SIZE_V 0x3FFF 2217 #define SPI_MEM_SMEM_PMS2_SIZE_S 0 2218 2219 #define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) 2220 /* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ 2221 /*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S 2222 MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ 2223 #define SPI_MEM_SMEM_PMS3_SIZE 0x00003FFF 2224 #define SPI_MEM_SMEM_PMS3_SIZE_M ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S)) 2225 #define SPI_MEM_SMEM_PMS3_SIZE_V 0x3FFF 2226 #define SPI_MEM_SMEM_PMS3_SIZE_S 0 2227 2228 #define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) 2229 /* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ 2230 /*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit 2231 error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ 2232 #define SPI_MEM_PMS_IVD (BIT(31)) 2233 #define SPI_MEM_PMS_IVD_M (BIT(31)) 2234 #define SPI_MEM_PMS_IVD_V 0x1 2235 #define SPI_MEM_PMS_IVD_S 31 2236 /* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ 2237 /*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It 2238 is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ 2239 #define SPI_MEM_PMS_MULTI_HIT (BIT(30)) 2240 #define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) 2241 #define SPI_MEM_PMS_MULTI_HIT_V 0x1 2242 #define SPI_MEM_PMS_MULTI_HIT_S 30 2243 /* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ 2244 /*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M 2245 EM_PMS_REJECT_INT_CLR bit is set..*/ 2246 #define SPI_MEM_PMS_ST (BIT(29)) 2247 #define SPI_MEM_PMS_ST_M (BIT(29)) 2248 #define SPI_MEM_PMS_ST_V 0x1 2249 #define SPI_MEM_PMS_ST_S 29 2250 /* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ 2251 /*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI 2252 _MEM_PMS_REJECT_INT_CLR bit is set..*/ 2253 #define SPI_MEM_PMS_LD (BIT(28)) 2254 #define SPI_MEM_PMS_LD_M (BIT(28)) 2255 #define SPI_MEM_PMS_LD_V 0x1 2256 #define SPI_MEM_PMS_LD_S 28 2257 /* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2258 /*description: Set this bit to enable SPI0/1 transfer permission control function..*/ 2259 #define SPI_MEM_PM_EN (BIT(26)) 2260 #define SPI_MEM_PM_EN_M (BIT(26)) 2261 #define SPI_MEM_PM_EN_V 0x1 2262 #define SPI_MEM_PM_EN_S 26 2263 /* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ 2264 /*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M 2265 EM_PMS_REJECT_INT_CLR bit is set..*/ 2266 #define SPI_MEM_REJECT_ADDR 0x03FFFFFF 2267 #define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) 2268 #define SPI_MEM_REJECT_ADDR_V 0x3FFFFFF 2269 #define SPI_MEM_REJECT_ADDR_S 0 2270 2271 #define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) 2272 /* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */ 2273 /*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding 2274 to byte 0 bit 0 to byte 15 bit 7).*/ 2275 #define SPI_MEM_ECC_ERR_BITS 0x0000007F 2276 #define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) 2277 #define SPI_MEM_ECC_ERR_BITS_V 0x7F 2278 #define SPI_MEM_ECC_ERR_BITS_S 25 2279 /* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */ 2280 /*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd 2281 ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD 2282 R record the first ECC error information..*/ 2283 #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) 2284 #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) 2285 #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 2286 #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 2287 /* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */ 2288 /*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ 2289 #define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) 2290 #define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21)) 2291 #define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 2292 #define SPI_MEM_USR_ECC_ADDR_EN_S 21 2293 /* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ 2294 /*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t 2295 he ECC region or non-ECC region of flash. If there is no ECC region in flash, th 2296 is bit should be 0. Otherwise, this bit should be 1..*/ 2297 #define SPI_MEM_FMEM_ECC_ADDR_EN (BIT(20)) 2298 #define SPI_MEM_FMEM_ECC_ADDR_EN_M (BIT(20)) 2299 #define SPI_MEM_FMEM_ECC_ADDR_EN_V 0x1 2300 #define SPI_MEM_FMEM_ECC_ADDR_EN_S 20 2301 /* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 2302 /*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 2303 1024 bytes. 3: 2048 bytes..*/ 2304 #define SPI_MEM_FMEM_PAGE_SIZE 0x00000003 2305 #define SPI_MEM_FMEM_PAGE_SIZE_M ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S)) 2306 #define SPI_MEM_FMEM_PAGE_SIZE_V 0x3 2307 #define SPI_MEM_FMEM_PAGE_SIZE_S 18 2308 /* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ 2309 /*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas 2310 h..*/ 2311 #define SPI_MEM_FMEM_ECC_ERR_INT_EN (BIT(17)) 2312 #define SPI_MEM_FMEM_ECC_ERR_INT_EN_M (BIT(17)) 2313 #define SPI_MEM_FMEM_ECC_ERR_INT_EN_V 0x1 2314 #define SPI_MEM_FMEM_ECC_ERR_INT_EN_S 17 2315 /* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */ 2316 /*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr 2317 upt..*/ 2318 #define SPI_MEM_FMEM_ECC_ERR_INT_NUM 0x0000003F 2319 #define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S)) 2320 #define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V 0x3F 2321 #define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S 11 2322 2323 #define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) 2324 /* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */ 2325 /*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ 2326 ECC_ERR_INT_CLR bit is set..*/ 2327 #define SPI_MEM_ECC_ERR_CNT 0x0000003F 2328 #define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) 2329 #define SPI_MEM_ECC_ERR_CNT_V 0x3F 2330 #define SPI_MEM_ECC_ERR_CNT_S 26 2331 /* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */ 2332 /*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ 2333 ECC_ERR_INT_CLR bit is set..*/ 2334 #define SPI_MEM_ECC_ERR_ADDR 0x03FFFFFF 2335 #define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) 2336 #define SPI_MEM_ECC_ERR_ADDR_V 0x3FFFFFF 2337 #define SPI_MEM_ECC_ERR_ADDR_S 0 2338 2339 #define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) 2340 /* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ 2341 /*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO 2342 and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ 2343 #define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) 2344 #define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) 2345 #define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 2346 #define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 2347 /* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ 2348 /*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ 2349 #define SPI_MEM_WBLEN_AFIFO_REMPTY (BIT(30)) 2350 #define SPI_MEM_WBLEN_AFIFO_REMPTY_M (BIT(30)) 2351 #define SPI_MEM_WBLEN_AFIFO_REMPTY_V 0x1 2352 #define SPI_MEM_WBLEN_AFIFO_REMPTY_S 30 2353 /* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ 2354 /*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ 2355 #define SPI_MEM_WDATA_AFIFO_REMPTY (BIT(29)) 2356 #define SPI_MEM_WDATA_AFIFO_REMPTY_M (BIT(29)) 2357 #define SPI_MEM_WDATA_AFIFO_REMPTY_V 0x1 2358 #define SPI_MEM_WDATA_AFIFO_REMPTY_S 29 2359 /* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ 2360 /*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ 2361 #define SPI_MEM_RADDR_AFIFO_REMPTY (BIT(28)) 2362 #define SPI_MEM_RADDR_AFIFO_REMPTY_M (BIT(28)) 2363 #define SPI_MEM_RADDR_AFIFO_REMPTY_V 0x1 2364 #define SPI_MEM_RADDR_AFIFO_REMPTY_S 28 2365 /* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ 2366 /*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ 2367 #define SPI_MEM_RDATA_AFIFO_REMPTY (BIT(27)) 2368 #define SPI_MEM_RDATA_AFIFO_REMPTY_M (BIT(27)) 2369 #define SPI_MEM_RDATA_AFIFO_REMPTY_V 0x1 2370 #define SPI_MEM_RDATA_AFIFO_REMPTY_S 27 2371 /* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ 2372 /*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers 2373 and SPI0 transfers are done. 0: Others..*/ 2374 #define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) 2375 #define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) 2376 #define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 2377 #define SPI_MEM_ALL_FIFO_EMPTY_S 26 2378 /* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ 2379 /*description: This bits show the first AXI write/read invalid error or AXI write flash error a 2380 ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS 2381 H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ 2382 #define SPI_MEM_AXI_ERR_ADDR 0x03FFFFFF 2383 #define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) 2384 #define SPI_MEM_AXI_ERR_ADDR_V 0x3FFFFFF 2385 #define SPI_MEM_AXI_ERR_ADDR_S 0 2386 2387 #define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) 2388 /* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ 2389 /*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t 2390 he ECC region or non-ECC region of external RAM. If there is no ECC region in ex 2391 ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ 2392 #define SPI_MEM_SMEM_ECC_ADDR_EN (BIT(20)) 2393 #define SPI_MEM_SMEM_ECC_ADDR_EN_M (BIT(20)) 2394 #define SPI_MEM_SMEM_ECC_ADDR_EN_V 0x1 2395 #define SPI_MEM_SMEM_ECC_ADDR_EN_S 20 2396 /* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */ 2397 /*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt 2398 es. 2: 1024 bytes. 3: 2048 bytes..*/ 2399 #define SPI_MEM_SMEM_PAGE_SIZE 0x00000003 2400 #define SPI_MEM_SMEM_PAGE_SIZE_M ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S)) 2401 #define SPI_MEM_SMEM_PAGE_SIZE_V 0x3 2402 #define SPI_MEM_SMEM_PAGE_SIZE_S 18 2403 /* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ 2404 /*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte 2405 rnal RAM..*/ 2406 #define SPI_MEM_SMEM_ECC_ERR_INT_EN (BIT(17)) 2407 #define SPI_MEM_SMEM_ECC_ERR_INT_EN_M (BIT(17)) 2408 #define SPI_MEM_SMEM_ECC_ERR_INT_EN_V 0x1 2409 #define SPI_MEM_SMEM_ECC_ERR_INT_EN_S 17 2410 2411 #define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) 2412 /* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ 2413 /*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ 2414 #define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) 2415 #define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) 2416 #define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 2417 #define SPI_MEM_TIMING_CALI_UPDATE_S 6 2418 /* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ 2419 /*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f 2420 lash..*/ 2421 #define SPI_MEM_DLL_TIMING_CALI (BIT(5)) 2422 #define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) 2423 #define SPI_MEM_DLL_TIMING_CALI_V 0x1 2424 #define SPI_MEM_DLL_TIMING_CALI_S 5 2425 /* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ 2426 /*description: add extra dummy spi clock cycle length for spi clock calibration..*/ 2427 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 2428 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) 2429 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 2430 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 2431 /* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2432 /*description: The bit is used to enable timing auto-calibration for all reading operations..*/ 2433 #define SPI_MEM_TIMING_CALI (BIT(1)) 2434 #define SPI_MEM_TIMING_CALI_M (BIT(1)) 2435 #define SPI_MEM_TIMING_CALI_V 0x1 2436 #define SPI_MEM_TIMING_CALI_S 1 2437 /* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 2438 /*description: The bit is used to enable timing adjust clock for all reading operations..*/ 2439 #define SPI_MEM_TIMING_CLK_ENA (BIT(0)) 2440 #define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) 2441 #define SPI_MEM_TIMING_CLK_ENA_V 0x1 2442 #define SPI_MEM_TIMING_CLK_ENA_S 0 2443 2444 #define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) 2445 /* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ 2446 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2447 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp 2448 ut with the spi_clk.*/ 2449 #define SPI_MEM_DINS_MODE 0x00000007 2450 #define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) 2451 #define SPI_MEM_DINS_MODE_V 0x7 2452 #define SPI_MEM_DINS_MODE_S 24 2453 /* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ 2454 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2455 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp 2456 ut with the spi_clk.*/ 2457 #define SPI_MEM_DIN7_MODE 0x00000007 2458 #define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) 2459 #define SPI_MEM_DIN7_MODE_V 0x7 2460 #define SPI_MEM_DIN7_MODE_S 21 2461 /* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ 2462 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2463 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp 2464 ut with the spi_clk.*/ 2465 #define SPI_MEM_DIN6_MODE 0x00000007 2466 #define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) 2467 #define SPI_MEM_DIN6_MODE_V 0x7 2468 #define SPI_MEM_DIN6_MODE_S 18 2469 /* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ 2470 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2471 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp 2472 ut with the spi_clk.*/ 2473 #define SPI_MEM_DIN5_MODE 0x00000007 2474 #define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) 2475 #define SPI_MEM_DIN5_MODE_V 0x7 2476 #define SPI_MEM_DIN5_MODE_S 15 2477 /* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ 2478 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2479 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp 2480 ut with the spi_clk.*/ 2481 #define SPI_MEM_DIN4_MODE 0x00000007 2482 #define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) 2483 #define SPI_MEM_DIN4_MODE_V 0x7 2484 #define SPI_MEM_DIN4_MODE_S 12 2485 /* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 2486 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2487 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2488 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2489 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2490 #define SPI_MEM_DIN3_MODE 0x00000007 2491 #define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) 2492 #define SPI_MEM_DIN3_MODE_V 0x7 2493 #define SPI_MEM_DIN3_MODE_S 9 2494 /* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ 2495 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2496 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2497 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2498 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2499 #define SPI_MEM_DIN2_MODE 0x00000007 2500 #define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) 2501 #define SPI_MEM_DIN2_MODE_V 0x7 2502 #define SPI_MEM_DIN2_MODE_S 6 2503 /* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ 2504 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2505 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2506 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2507 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2508 #define SPI_MEM_DIN1_MODE 0x00000007 2509 #define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) 2510 #define SPI_MEM_DIN1_MODE_V 0x7 2511 #define SPI_MEM_DIN1_MODE_S 3 2512 /* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 2513 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2514 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2515 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2516 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2517 #define SPI_MEM_DIN0_MODE 0x00000007 2518 #define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) 2519 #define SPI_MEM_DIN0_MODE_V 0x7 2520 #define SPI_MEM_DIN0_MODE_S 0 2521 2522 #define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) 2523 /* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ 2524 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2525 delayed by 2 cycles,....*/ 2526 #define SPI_MEM_DINS_NUM 0x00000003 2527 #define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) 2528 #define SPI_MEM_DINS_NUM_V 0x3 2529 #define SPI_MEM_DINS_NUM_S 16 2530 /* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ 2531 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2532 delayed by 2 cycles,....*/ 2533 #define SPI_MEM_DIN7_NUM 0x00000003 2534 #define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) 2535 #define SPI_MEM_DIN7_NUM_V 0x3 2536 #define SPI_MEM_DIN7_NUM_S 14 2537 /* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ 2538 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2539 delayed by 2 cycles,....*/ 2540 #define SPI_MEM_DIN6_NUM 0x00000003 2541 #define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) 2542 #define SPI_MEM_DIN6_NUM_V 0x3 2543 #define SPI_MEM_DIN6_NUM_S 12 2544 /* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ 2545 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2546 delayed by 2 cycles,....*/ 2547 #define SPI_MEM_DIN5_NUM 0x00000003 2548 #define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) 2549 #define SPI_MEM_DIN5_NUM_V 0x3 2550 #define SPI_MEM_DIN5_NUM_S 10 2551 /* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ 2552 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2553 delayed by 2 cycles,....*/ 2554 #define SPI_MEM_DIN4_NUM 0x00000003 2555 #define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) 2556 #define SPI_MEM_DIN4_NUM_V 0x3 2557 #define SPI_MEM_DIN4_NUM_S 8 2558 /* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ 2559 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2560 delayed by 2 cycles,....*/ 2561 #define SPI_MEM_DIN3_NUM 0x00000003 2562 #define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) 2563 #define SPI_MEM_DIN3_NUM_V 0x3 2564 #define SPI_MEM_DIN3_NUM_S 6 2565 /* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ 2566 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2567 delayed by 2 cycles,....*/ 2568 #define SPI_MEM_DIN2_NUM 0x00000003 2569 #define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) 2570 #define SPI_MEM_DIN2_NUM_V 0x3 2571 #define SPI_MEM_DIN2_NUM_S 4 2572 /* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ 2573 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2574 delayed by 2 cycles,....*/ 2575 #define SPI_MEM_DIN1_NUM 0x00000003 2576 #define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) 2577 #define SPI_MEM_DIN1_NUM_V 0x3 2578 #define SPI_MEM_DIN1_NUM_S 2 2579 /* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 2580 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2581 delayed by 2 cycles,....*/ 2582 #define SPI_MEM_DIN0_NUM 0x00000003 2583 #define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) 2584 #define SPI_MEM_DIN0_NUM_V 0x3 2585 #define SPI_MEM_DIN0_NUM_S 0 2586 2587 #define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) 2588 /* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ 2589 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2590 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2591 output with the spi_clk.*/ 2592 #define SPI_MEM_DOUTS_MODE (BIT(8)) 2593 #define SPI_MEM_DOUTS_MODE_M (BIT(8)) 2594 #define SPI_MEM_DOUTS_MODE_V 0x1 2595 #define SPI_MEM_DOUTS_MODE_S 8 2596 /* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ 2597 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2598 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2599 output with the spi_clk.*/ 2600 #define SPI_MEM_DOUT7_MODE (BIT(7)) 2601 #define SPI_MEM_DOUT7_MODE_M (BIT(7)) 2602 #define SPI_MEM_DOUT7_MODE_V 0x1 2603 #define SPI_MEM_DOUT7_MODE_S 7 2604 /* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ 2605 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2606 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2607 output with the spi_clk.*/ 2608 #define SPI_MEM_DOUT6_MODE (BIT(6)) 2609 #define SPI_MEM_DOUT6_MODE_M (BIT(6)) 2610 #define SPI_MEM_DOUT6_MODE_V 0x1 2611 #define SPI_MEM_DOUT6_MODE_S 6 2612 /* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ 2613 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2614 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2615 output with the spi_clk.*/ 2616 #define SPI_MEM_DOUT5_MODE (BIT(5)) 2617 #define SPI_MEM_DOUT5_MODE_M (BIT(5)) 2618 #define SPI_MEM_DOUT5_MODE_V 0x1 2619 #define SPI_MEM_DOUT5_MODE_S 5 2620 /* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ 2621 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2622 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2623 output with the spi_clk.*/ 2624 #define SPI_MEM_DOUT4_MODE (BIT(4)) 2625 #define SPI_MEM_DOUT4_MODE_M (BIT(4)) 2626 #define SPI_MEM_DOUT4_MODE_V 0x1 2627 #define SPI_MEM_DOUT4_MODE_S 4 2628 /* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ 2629 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2630 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2631 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2632 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2633 #define SPI_MEM_DOUT3_MODE (BIT(3)) 2634 #define SPI_MEM_DOUT3_MODE_M (BIT(3)) 2635 #define SPI_MEM_DOUT3_MODE_V 0x1 2636 #define SPI_MEM_DOUT3_MODE_S 3 2637 /* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ 2638 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2639 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2640 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2641 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2642 #define SPI_MEM_DOUT2_MODE (BIT(2)) 2643 #define SPI_MEM_DOUT2_MODE_M (BIT(2)) 2644 #define SPI_MEM_DOUT2_MODE_V 0x1 2645 #define SPI_MEM_DOUT2_MODE_S 2 2646 /* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ 2647 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2648 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2649 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2650 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2651 #define SPI_MEM_DOUT1_MODE (BIT(1)) 2652 #define SPI_MEM_DOUT1_MODE_M (BIT(1)) 2653 #define SPI_MEM_DOUT1_MODE_V 0x1 2654 #define SPI_MEM_DOUT1_MODE_S 1 2655 /* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ 2656 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2657 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2658 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2659 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2660 #define SPI_MEM_DOUT0_MODE (BIT(0)) 2661 #define SPI_MEM_DOUT0_MODE_M (BIT(0)) 2662 #define SPI_MEM_DOUT0_MODE_V 0x1 2663 #define SPI_MEM_DOUT0_MODE_S 0 2664 2665 #define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) 2666 /* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ 2667 /*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E 2668 XT_RAM..*/ 2669 #define SPI_MEM_SMEM_DLL_TIMING_CALI (BIT(5)) 2670 #define SPI_MEM_SMEM_DLL_TIMING_CALI_M (BIT(5)) 2671 #define SPI_MEM_SMEM_DLL_TIMING_CALI_V 0x1 2672 #define SPI_MEM_SMEM_DLL_TIMING_CALI_S 5 2673 /* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */ 2674 /*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ 2675 #define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 2676 #define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S)) 2677 #define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 2678 #define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 2679 /* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */ 2680 /*description: For sram, the bit is used to enable timing auto-calibration for all reading oper 2681 ations..*/ 2682 #define SPI_MEM_SMEM_TIMING_CALI (BIT(1)) 2683 #define SPI_MEM_SMEM_TIMING_CALI_M (BIT(1)) 2684 #define SPI_MEM_SMEM_TIMING_CALI_V 0x1 2685 #define SPI_MEM_SMEM_TIMING_CALI_S 1 2686 /* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ 2687 /*description: For sram, the bit is used to enable timing adjust clock for all reading operatio 2688 ns..*/ 2689 #define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) 2690 #define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) 2691 #define SPI_MEM_SMEM_TIMING_CLK_ENA_V 0x1 2692 #define SPI_MEM_SMEM_TIMING_CLK_ENA_S 0 2693 2694 #define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) 2695 /* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ 2696 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2697 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2698 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2699 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2700 #define SPI_MEM_SMEM_DINS_MODE 0x00000007 2701 #define SPI_MEM_SMEM_DINS_MODE_M ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S)) 2702 #define SPI_MEM_SMEM_DINS_MODE_V 0x7 2703 #define SPI_MEM_SMEM_DINS_MODE_S 24 2704 /* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ 2705 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2706 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2707 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2708 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2709 #define SPI_MEM_SMEM_DIN7_MODE 0x00000007 2710 #define SPI_MEM_SMEM_DIN7_MODE_M ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S)) 2711 #define SPI_MEM_SMEM_DIN7_MODE_V 0x7 2712 #define SPI_MEM_SMEM_DIN7_MODE_S 21 2713 /* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ 2714 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2715 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2716 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2717 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2718 #define SPI_MEM_SMEM_DIN6_MODE 0x00000007 2719 #define SPI_MEM_SMEM_DIN6_MODE_M ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S)) 2720 #define SPI_MEM_SMEM_DIN6_MODE_V 0x7 2721 #define SPI_MEM_SMEM_DIN6_MODE_S 18 2722 /* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ 2723 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2724 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2725 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2726 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2727 #define SPI_MEM_SMEM_DIN5_MODE 0x00000007 2728 #define SPI_MEM_SMEM_DIN5_MODE_M ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S)) 2729 #define SPI_MEM_SMEM_DIN5_MODE_V 0x7 2730 #define SPI_MEM_SMEM_DIN5_MODE_S 15 2731 /* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ 2732 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2733 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2734 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2735 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2736 #define SPI_MEM_SMEM_DIN4_MODE 0x00000007 2737 #define SPI_MEM_SMEM_DIN4_MODE_M ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S)) 2738 #define SPI_MEM_SMEM_DIN4_MODE_V 0x7 2739 #define SPI_MEM_SMEM_DIN4_MODE_S 12 2740 /* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ 2741 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2742 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2743 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2744 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2745 #define SPI_MEM_SMEM_DIN3_MODE 0x00000007 2746 #define SPI_MEM_SMEM_DIN3_MODE_M ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S)) 2747 #define SPI_MEM_SMEM_DIN3_MODE_V 0x7 2748 #define SPI_MEM_SMEM_DIN3_MODE_S 9 2749 /* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ 2750 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2751 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2752 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2753 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2754 #define SPI_MEM_SMEM_DIN2_MODE 0x00000007 2755 #define SPI_MEM_SMEM_DIN2_MODE_M ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S)) 2756 #define SPI_MEM_SMEM_DIN2_MODE_V 0x7 2757 #define SPI_MEM_SMEM_DIN2_MODE_S 6 2758 /* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ 2759 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2760 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2761 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2762 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2763 #define SPI_MEM_SMEM_DIN1_MODE 0x00000007 2764 #define SPI_MEM_SMEM_DIN1_MODE_M ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S)) 2765 #define SPI_MEM_SMEM_DIN1_MODE_V 0x7 2766 #define SPI_MEM_SMEM_DIN1_MODE_S 3 2767 /* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ 2768 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2769 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2770 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2771 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2772 #define SPI_MEM_SMEM_DIN0_MODE 0x00000007 2773 #define SPI_MEM_SMEM_DIN0_MODE_M ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S)) 2774 #define SPI_MEM_SMEM_DIN0_MODE_V 0x7 2775 #define SPI_MEM_SMEM_DIN0_MODE_S 0 2776 2777 #define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) 2778 /* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ 2779 /*description: the input signals are delayed by system clock cycles, 0: input without delayed, 2780 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in 2781 put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w 2782 ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ 2783 #define SPI_MEM_SMEM_DINS_NUM 0x00000003 2784 #define SPI_MEM_SMEM_DINS_NUM_M ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S)) 2785 #define SPI_MEM_SMEM_DINS_NUM_V 0x3 2786 #define SPI_MEM_SMEM_DINS_NUM_S 16 2787 /* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ 2788 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2789 delayed by 2 cycles,....*/ 2790 #define SPI_MEM_SMEM_DIN7_NUM 0x00000003 2791 #define SPI_MEM_SMEM_DIN7_NUM_M ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S)) 2792 #define SPI_MEM_SMEM_DIN7_NUM_V 0x3 2793 #define SPI_MEM_SMEM_DIN7_NUM_S 14 2794 /* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ 2795 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2796 delayed by 2 cycles,....*/ 2797 #define SPI_MEM_SMEM_DIN6_NUM 0x00000003 2798 #define SPI_MEM_SMEM_DIN6_NUM_M ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S)) 2799 #define SPI_MEM_SMEM_DIN6_NUM_V 0x3 2800 #define SPI_MEM_SMEM_DIN6_NUM_S 12 2801 /* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ 2802 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2803 delayed by 2 cycles,....*/ 2804 #define SPI_MEM_SMEM_DIN5_NUM 0x00000003 2805 #define SPI_MEM_SMEM_DIN5_NUM_M ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S)) 2806 #define SPI_MEM_SMEM_DIN5_NUM_V 0x3 2807 #define SPI_MEM_SMEM_DIN5_NUM_S 10 2808 /* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ 2809 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2810 delayed by 2 cycles,....*/ 2811 #define SPI_MEM_SMEM_DIN4_NUM 0x00000003 2812 #define SPI_MEM_SMEM_DIN4_NUM_M ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S)) 2813 #define SPI_MEM_SMEM_DIN4_NUM_V 0x3 2814 #define SPI_MEM_SMEM_DIN4_NUM_S 8 2815 /* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ 2816 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2817 delayed by 2 cycles,....*/ 2818 #define SPI_MEM_SMEM_DIN3_NUM 0x00000003 2819 #define SPI_MEM_SMEM_DIN3_NUM_M ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S)) 2820 #define SPI_MEM_SMEM_DIN3_NUM_V 0x3 2821 #define SPI_MEM_SMEM_DIN3_NUM_S 6 2822 /* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ 2823 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2824 delayed by 2 cycles,....*/ 2825 #define SPI_MEM_SMEM_DIN2_NUM 0x00000003 2826 #define SPI_MEM_SMEM_DIN2_NUM_M ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S)) 2827 #define SPI_MEM_SMEM_DIN2_NUM_V 0x3 2828 #define SPI_MEM_SMEM_DIN2_NUM_S 4 2829 /* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ 2830 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2831 delayed by 2 cycles,....*/ 2832 #define SPI_MEM_SMEM_DIN1_NUM 0x00000003 2833 #define SPI_MEM_SMEM_DIN1_NUM_M ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S)) 2834 #define SPI_MEM_SMEM_DIN1_NUM_V 0x3 2835 #define SPI_MEM_SMEM_DIN1_NUM_S 2 2836 /* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ 2837 /*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: 2838 delayed by 2 cycles,....*/ 2839 #define SPI_MEM_SMEM_DIN0_NUM 0x00000003 2840 #define SPI_MEM_SMEM_DIN0_NUM_M ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S)) 2841 #define SPI_MEM_SMEM_DIN0_NUM_V 0x3 2842 #define SPI_MEM_SMEM_DIN0_NUM_S 0 2843 2844 #define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) 2845 /* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ 2846 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2847 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2848 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2849 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2850 #define SPI_MEM_SMEM_DOUTS_MODE (BIT(8)) 2851 #define SPI_MEM_SMEM_DOUTS_MODE_M (BIT(8)) 2852 #define SPI_MEM_SMEM_DOUTS_MODE_V 0x1 2853 #define SPI_MEM_SMEM_DOUTS_MODE_S 8 2854 /* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ 2855 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2856 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2857 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2858 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2859 #define SPI_MEM_SMEM_DOUT7_MODE (BIT(7)) 2860 #define SPI_MEM_SMEM_DOUT7_MODE_M (BIT(7)) 2861 #define SPI_MEM_SMEM_DOUT7_MODE_V 0x1 2862 #define SPI_MEM_SMEM_DOUT7_MODE_S 7 2863 /* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ 2864 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2865 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2866 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2867 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2868 #define SPI_MEM_SMEM_DOUT6_MODE (BIT(6)) 2869 #define SPI_MEM_SMEM_DOUT6_MODE_M (BIT(6)) 2870 #define SPI_MEM_SMEM_DOUT6_MODE_V 0x1 2871 #define SPI_MEM_SMEM_DOUT6_MODE_S 6 2872 /* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ 2873 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2874 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2875 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2876 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2877 #define SPI_MEM_SMEM_DOUT5_MODE (BIT(5)) 2878 #define SPI_MEM_SMEM_DOUT5_MODE_M (BIT(5)) 2879 #define SPI_MEM_SMEM_DOUT5_MODE_V 0x1 2880 #define SPI_MEM_SMEM_DOUT5_MODE_S 5 2881 /* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ 2882 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2883 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2884 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2885 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2886 #define SPI_MEM_SMEM_DOUT4_MODE (BIT(4)) 2887 #define SPI_MEM_SMEM_DOUT4_MODE_M (BIT(4)) 2888 #define SPI_MEM_SMEM_DOUT4_MODE_V 0x1 2889 #define SPI_MEM_SMEM_DOUT4_MODE_S 4 2890 /* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ 2891 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2892 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2893 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2894 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2895 #define SPI_MEM_SMEM_DOUT3_MODE (BIT(3)) 2896 #define SPI_MEM_SMEM_DOUT3_MODE_M (BIT(3)) 2897 #define SPI_MEM_SMEM_DOUT3_MODE_V 0x1 2898 #define SPI_MEM_SMEM_DOUT3_MODE_S 3 2899 /* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ 2900 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2901 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2902 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2903 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2904 #define SPI_MEM_SMEM_DOUT2_MODE (BIT(2)) 2905 #define SPI_MEM_SMEM_DOUT2_MODE_M (BIT(2)) 2906 #define SPI_MEM_SMEM_DOUT2_MODE_V 0x1 2907 #define SPI_MEM_SMEM_DOUT2_MODE_S 2 2908 /* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ 2909 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2910 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2911 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2912 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2913 #define SPI_MEM_SMEM_DOUT1_MODE (BIT(1)) 2914 #define SPI_MEM_SMEM_DOUT1_MODE_M (BIT(1)) 2915 #define SPI_MEM_SMEM_DOUT1_MODE_V 0x1 2916 #define SPI_MEM_SMEM_DOUT1_MODE_S 1 2917 /* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ 2918 /*description: the output signals are delayed by system clock cycles, 0: output without delayed 2919 , 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: 2920 output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp 2921 ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ 2922 #define SPI_MEM_SMEM_DOUT0_MODE (BIT(0)) 2923 #define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0)) 2924 #define SPI_MEM_SMEM_DOUT0_MODE_V 0x1 2925 #define SPI_MEM_SMEM_DOUT0_MODE_S 0 2926 2927 #define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) 2928 /* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */ 2929 /*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI 2930 transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt 2931 er whether there is an ECC region or not..*/ 2932 #define SPI_MEM_SMEM_SPLIT_TRANS_EN (BIT(31)) 2933 #define SPI_MEM_SMEM_SPLIT_TRANS_EN_M (BIT(31)) 2934 #define SPI_MEM_SMEM_SPLIT_TRANS_EN_V 0x1 2935 #define SPI_MEM_SMEM_SPLIT_TRANS_EN_S 31 2936 /* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */ 2937 /*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran 2938 sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M 2939 SPI core clock cycles..*/ 2940 #define SPI_MEM_SMEM_CS_HOLD_DELAY 0x0000003F 2941 #define SPI_MEM_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S)) 2942 #define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F 2943 #define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 2944 /* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ 2945 /*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe 2946 n accesses external RAM..*/ 2947 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) 2948 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) 2949 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 2950 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16 2951 /* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */ 2952 /*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh 2953 en accesses external RAM..*/ 2954 #define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) 2955 #define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) 2956 #define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 2957 #define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S 15 2958 /* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */ 2959 /*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c 2960 ycles in ECC mode when accessed external RAM..*/ 2961 #define SPI_MEM_SMEM_ECC_CS_HOLD_TIME 0x00000007 2962 #define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S)) 2963 #define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V 0x7 2964 #define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S 12 2965 /* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */ 2966 /*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a 2967 re combined with spi_mem_cs_hold bit..*/ 2968 #define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F 2969 #define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S)) 2970 #define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F 2971 #define SPI_MEM_SMEM_CS_HOLD_TIME_S 7 2972 /* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */ 2973 /*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s 2974 pi_mem_cs_setup bit..*/ 2975 #define SPI_MEM_SMEM_CS_SETUP_TIME 0x0000001F 2976 #define SPI_MEM_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S)) 2977 #define SPI_MEM_SMEM_CS_SETUP_TIME_V 0x1F 2978 #define SPI_MEM_SMEM_CS_SETUP_TIME_S 2 2979 /* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */ 2980 /*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab 2981 le..*/ 2982 #define SPI_MEM_SMEM_CS_HOLD (BIT(1)) 2983 #define SPI_MEM_SMEM_CS_HOLD_M (BIT(1)) 2984 #define SPI_MEM_SMEM_CS_HOLD_V 0x1 2985 #define SPI_MEM_SMEM_CS_HOLD_S 1 2986 /* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */ 2987 /*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d 2988 isable..*/ 2989 #define SPI_MEM_SMEM_CS_SETUP (BIT(0)) 2990 #define SPI_MEM_SMEM_CS_SETUP_M (BIT(0)) 2991 #define SPI_MEM_SMEM_CS_SETUP_V 0x1 2992 #define SPI_MEM_SMEM_CS_SETUP_S 0 2993 2994 #define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) 2995 /* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 2996 /*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ 2997 #define SPI_MEM_CLK_EN (BIT(0)) 2998 #define SPI_MEM_CLK_EN_M (BIT(0)) 2999 #define SPI_MEM_CLK_EN_V 0x1 3000 #define SPI_MEM_CLK_EN_S 0 3001 3002 #define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) 3003 /* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ 3004 /*description: MSPI-MMU item content.*/ 3005 #define SPI_MEM_MMU_ITEM_CONTENT 0xFFFFFFFF 3006 #define SPI_MEM_MMU_ITEM_CONTENT_M ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S)) 3007 #define SPI_MEM_MMU_ITEM_CONTENT_V 0xFFFFFFFF 3008 #define SPI_MEM_MMU_ITEM_CONTENT_S 0 3009 3010 #define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) 3011 /* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 3012 /*description: MSPI-MMU item index.*/ 3013 #define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF 3014 #define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S)) 3015 #define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF 3016 #define SPI_MEM_MMU_ITEM_INDEX_S 0 3017 3018 #define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) 3019 /* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ 3020 /*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ 3021 #define SPI_MEM_RDN_RESULT (BIT(31)) 3022 #define SPI_MEM_RDN_RESULT_M (BIT(31)) 3023 #define SPI_MEM_RDN_RESULT_V 0x1 3024 #define SPI_MEM_RDN_RESULT_S 31 3025 /* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */ 3026 /*description: ECO register enable bit.*/ 3027 #define SPI_MEM_RDN_ENA (BIT(30)) 3028 #define SPI_MEM_RDN_ENA_M (BIT(30)) 3029 #define SPI_MEM_RDN_ENA_V 0x1 3030 #define SPI_MEM_RDN_ENA_S 30 3031 /* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */ 3032 /*description: MMU PSRAM aux control register.*/ 3033 #define SPI_MEM_AUX_CTRL 0x00003FFF 3034 #define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) 3035 #define SPI_MEM_AUX_CTRL_V 0x3FFF 3036 #define SPI_MEM_AUX_CTRL_S 16 3037 /* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ 3038 /*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ 3039 #define SPI_MEM_MMU_PAGE_SIZE 0x00000003 3040 #define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S)) 3041 #define SPI_MEM_MMU_PAGE_SIZE_V 0x3 3042 #define SPI_MEM_MMU_PAGE_SIZE_S 3 3043 /* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 3044 /*description: Set this bit to force mmu-memory powerup, in this case, the power should also be 3045 controlled by rtc..*/ 3046 #define SPI_MEM_MMU_MEM_FORCE_PU (BIT(2)) 3047 #define SPI_MEM_MMU_MEM_FORCE_PU_M (BIT(2)) 3048 #define SPI_MEM_MMU_MEM_FORCE_PU_V 0x1 3049 #define SPI_MEM_MMU_MEM_FORCE_PU_S 2 3050 /* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 3051 /*description: Set this bit to force mmu-memory powerdown.*/ 3052 #define SPI_MEM_MMU_MEM_FORCE_PD (BIT(1)) 3053 #define SPI_MEM_MMU_MEM_FORCE_PD_M (BIT(1)) 3054 #define SPI_MEM_MMU_MEM_FORCE_PD_V 0x1 3055 #define SPI_MEM_MMU_MEM_FORCE_PD_S 1 3056 /* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3057 /*description: Set this bit to enable mmu-memory clock force on.*/ 3058 #define SPI_MEM_MMU_MEM_FORCE_ON (BIT(0)) 3059 #define SPI_MEM_MMU_MEM_FORCE_ON_M (BIT(0)) 3060 #define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1 3061 #define SPI_MEM_MMU_MEM_FORCE_ON_S 0 3062 3063 #define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) 3064 /* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */ 3065 /*description: ECO high register.*/ 3066 #define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF 3067 #define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) 3068 #define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF 3069 #define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 3070 3071 #define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) 3072 /* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */ 3073 /*description: ECO low register.*/ 3074 #define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF 3075 #define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) 3076 #define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF 3077 #define SPI_MEM_REGISTERRND_ECO_LOW_S 0 3078 3079 #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) 3080 /* SPI_MEM_DATE : R/W; bitpos: [27:0] ;default: 35663920; */ 3081 /*description: SPI0 register version..*/ 3082 /* SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; */ 3083 /*description: SPI1 register version..*/ 3084 #define SPI_MEM_DATE 0x0FFFFFFF 3085 #define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) 3086 #define SPI_MEM_DATE_V 0xFFFFFFF 3087 #define SPI_MEM_DATE_S 0 3088 3089 #ifdef __cplusplus 3090 } 3091 #endif 3092
