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Searched refs:SPI_MEM_CACHE_SCTRL_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32s3/
Desp_psram_impl_octal.c352 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); in s_config_psram_spi_phases()
357 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); in s_config_psram_spi_phases()
362 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, OCT_PSRAM_ADDR_BITLEN - … in s_config_psram_spi_phases()
363 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_USR_SCMD_4BYTE_M); in s_config_psram_spi_phases()
366 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M | SPI_MEM_USR_WR_SRAM_DU… in s_config_psram_spi_phases()
367 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, OCT_PSRAM_RD_DUMMY_B… in s_config_psram_spi_phases()
369 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_WDUMMY_CYCLELEN_V, OCT_PSRAM_WR_DUMMY_B… in s_config_psram_spi_phases()
375 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_OCT_M); in s_config_psram_spi_phases()
Desp_psram_impl_quad.c397 …CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode … in config_psram_spi_phases()
398 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode f… in config_psram_spi_phases()
399 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read… in config_psram_spi_phases()
400 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache writ… in config_psram_spi_phases()
407 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BI… in config_psram_spi_phases()
414 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read… in config_psram_spi_phases()
415 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUA… in config_psram_spi_phases()
/hal_espressif-latest/components/esp_psram/esp32s2/
Desp_psram_impl_quad.c514 …CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode … in psram_cache_init()
515 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode f… in psram_cache_init()
516 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read… in psram_cache_init()
517 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache writ… in psram_cache_init()
518 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BI… in psram_cache_init()
519 …SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read… in psram_cache_init()
530 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD… in psram_cache_init()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmspi_timing_tuning_ll.h341 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M); in mspi_timing_ll_set_quad_psram_dummy()
342 …SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, dummy, SPI_MEM… in mspi_timing_ll_set_quad_psram_dummy()
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_mem_reg.h640 #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x040) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_mem_reg.h656 #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dspi_mem_reg.h776 #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dspi_mem_reg.h771 #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) macro