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Searched refs:RTC_CNTL_ANA_CONF_REG (Results 1 – 25 of 30) sorted by relevance

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/hal_espressif-latest/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_init.c56 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
58 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
Dsoc_random.c20 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in soc_random_enable()
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c38 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M); in soc_random_enable()
39 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in soc_random_enable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32s2.c43 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M); in bootloader_random_enable()
44 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in bootloader_random_enable()
Dbootloader_random_esp32c2.c20 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in bootloader_random_enable()
Dbootloader_random_esp32c3.c20 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in bootloader_random_enable()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_init.c42 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); in rtc_init()
102 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in rtc_init()
103 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in rtc_init()
130 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_SAR_I2C_FORCE_PD); in rtc_init()
Drtc_sleep.c226 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, in rtc_sleep_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_init.c48 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); in rtc_init()
97 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in rtc_init()
98 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in rtc_init()
101 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); in rtc_init()
Drtc_sleep.c214 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, in rtc_sleep_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_init.c33 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | RTC_CNTL_TXRF_I2C_PU | in rtc_init()
77 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in rtc_init()
78 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in rtc_init()
Drtc_sleep.c208 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, in rtc_sleep_init()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c45 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
47 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h133 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_enable()
134 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in clk_ll_apll_enable()
142 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_disable()
143 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in clk_ll_apll_disable()
153 return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_is_fpd()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_tree_ll.h100 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_enable()
101 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in clk_ll_apll_enable()
109 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_disable()
110 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); in clk_ll_apll_disable()
Dadc_ll.h156 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in adc_ll_set_sample_cycle()
1070 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M); in adc_ll_calibration_prepare()
1071 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in adc_ll_calibration_prepare()
1118 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in adc_ll_set_calibration_param()
1146 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); in adc_ll_vref_output()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_init.c61 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); in rtc_init()
137 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); in rtc_init()
162 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); in rtc_init()
Drtc_sleep.c226 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, in rtc_sleep_init()
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_random.c20 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in soc_random_enable()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_sleep.c166 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, in rtc_sleep_init()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dadc_ll.h136 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); in adc_ll_set_sample_cycle()
713 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); in adc_ll_vref_output()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dadc_ll.h166 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in adc_ll_set_sample_cycle()
751 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); in adc_ll_calibration_prepare()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dadc_ll.h98 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); in adc_ll_set_sample_cycle()

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