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Searched refs:DPORT_PRO_CACHE_CTRL1_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h149 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask); in cache_ll_l1_enable_bus()
175 uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG); in cache_ll_l1_get_enabled_bus()
216 DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask); in cache_ll_l1_disable_bus()
/hal_espressif-latest/zephyr/esp32/src/
Dsoc_init.c86 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); in reset_mmu()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Dcache_sram_mmu.c118 DPORT_REG_SET_FIELD(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, mask_s); in cache_sram_mmu_set()
Drtc_init.c50 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON); in rtc_init()
/hal_espressif-latest/components/bootloader_support/src/esp32/
Dbootloader_esp32.c66 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); in bootloader_reset_mmu()
/hal_espressif-latest/components/esp_hw_support/
Dsleep_modes.c369 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG, in esp_default_wake_deep_sleep()
370 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR); in esp_default_wake_deep_sleep()
371 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG, in esp_default_wake_deep_sleep()
372 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR)); in esp_default_wake_deep_sleep()
/hal_espressif-latest/components/esp_psram/esp32/
Desp_psram_impl_quad.c1119 …DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MA… in psram_cache_init()
1121 …DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMM… in psram_cache_init()
/hal_espressif-latest/components/soc/esp32/include/soc/
Ddport_reg.h267 #define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) macro