1 /*
2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "soc_init.h"
8 #include "esp_log.h"
9 #include "rom/cache.h"
10 #include "soc/dport_reg.h"
11 #include <stdint.h>
12
13 static const char *TAG = "soc_init";
14
wdt_reset_info_dump(int cpu)15 void wdt_reset_info_dump(int cpu)
16 {
17 uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0, lsstat = 0, lsaddr = 0, lsdata = 0,
18 dstat = 0;
19 const char *cpu_name = cpu ? "APP" : "PRO";
20
21 stat = 0xdeadbeef;
22 pid = 0;
23
24 if (cpu == 0) {
25 stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
26 pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
27 inst = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG);
28 dstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG);
29 data = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG);
30 pc = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG);
31 lsstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
32 lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
33 lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
34 } else {
35 ESP_EARLY_LOGE(TAG, "WDT reset info: %s CPU not support!\n", cpu_name);
36 return;
37 }
38
39 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08" PRIx32, cpu_name, stat);
40 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08" PRIx32, cpu_name, pid);
41 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08" PRIx32, cpu_name, inst);
42 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08" PRIx32, cpu_name, dstat);
43 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08" PRIx32, cpu_name, data);
44 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08" PRIx32, cpu_name, pc);
45 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08" PRIx32, cpu_name, lsstat);
46 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08" PRIx32, cpu_name, lsaddr);
47 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08" PRIx32, cpu_name, lsdata);
48 }
49
wdt_reset_cpu0_info_enable(void)50 void wdt_reset_cpu0_info_enable(void)
51 {
52 DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG,
53 DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
54 DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
55 }
56
check_wdt_reset(void)57 void check_wdt_reset(void)
58 {
59 int wdt_rst = 0;
60 soc_reset_reason_t rst_reas;
61
62 rst_reas = esp_rom_get_reset_reason(0);
63 if (rst_reas == RESET_REASON_CORE_RTC_WDT || rst_reas == RESET_REASON_CORE_MWDT0 ||
64 rst_reas == RESET_REASON_CORE_MWDT1 || rst_reas == RESET_REASON_CPU0_RTC_WDT) {
65 ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
66 wdt_rst = 1;
67 }
68
69 if (wdt_rst) {
70 wdt_reset_info_dump(0);
71 }
72
73 wdt_reset_cpu0_info_enable();
74 }
75
reset_mmu(void)76 void reset_mmu(void)
77 {
78 /* completely reset MMU in case serial bootloader was running */
79 Cache_Read_Disable(0);
80 Cache_Flush(0);
81 mmu_init(0);
82
83 /* normal ROM boot exits with DROM0 cache unmasked,
84 * but serial bootloader exits with it masked.
85 */
86 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
87 }
88
89 /* Not supported but common bootloader calls the function. Do nothing */
ana_clock_glitch_reset_config(bool enable)90 void ana_clock_glitch_reset_config(bool enable)
91 {
92 (void)enable;
93 }
94
