1 /*
2 Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
3 */
4
5 /*
6 * SPDX-FileCopyrightText: 2013-2022 Espressif Systems (Shanghai) CO LTD
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11
12 #include "sdkconfig.h"
13 #include "string.h"
14 #include "esp_attr.h"
15 #include "esp_err.h"
16 #include "esp_types.h"
17 #include "esp_bit_defs.h"
18 #include "esp_log.h"
19 #include "../esp_psram_impl.h"
20 #include "esp32/rom/spi_flash.h"
21 #include "esp32/rom/cache.h"
22 #include "esp32/rom/efuse.h"
23 #include "esp32/rom/gpio.h"
24 #include "esp_rom_efuse.h"
25 #include "soc/dport_reg.h"
26 #include "soc/efuse_periph.h"
27 #include "soc/soc_caps.h"
28 #include "soc/spi_periph.h"
29 #include "soc/chip_revision.h"
30 #include "driver/gpio.h"
31 #include "hal/efuse_hal.h"
32 #include "hal/gpio_hal.h"
33 #include "esp_private/spi_common_internal.h"
34 #include "esp_private/periph_ctrl.h"
35 #include "bootloader_common.h"
36 #include "esp_rom_gpio.h"
37 #include "soc_flash_init.h"
38 #include "esp_private/esp_gpio_reserve.h"
39
40 #if CONFIG_SPIRAM
41 #include "soc/rtc.h"
42
43 //Commands for PSRAM chip
44 #define PSRAM_READ 0x03
45 #define PSRAM_FAST_READ 0x0B
46 #define PSRAM_FAST_READ_DUMMY 0x3
47 #define PSRAM_FAST_READ_QUAD 0xEB
48 #define PSRAM_FAST_READ_QUAD_DUMMY 0x5
49 #define PSRAM_WRITE 0x02
50 #define PSRAM_QUAD_WRITE 0x38
51 #define PSRAM_ENTER_QMODE 0x35
52 #define PSRAM_EXIT_QMODE 0xF5
53 #define PSRAM_RESET_EN 0x66
54 #define PSRAM_RESET 0x99
55 #define PSRAM_SET_BURST_LEN 0xC0
56 #define PSRAM_DEVICE_ID 0x9F
57
58 typedef enum {
59 PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */
60 PSRAM_CLK_MODE_DCLK = 1, /*!< Two extra clock cycles after CS is set high level */
61 } psram_clk_mode_t;
62
63 #define PSRAM_ID_KGD_M 0xff
64 #define PSRAM_ID_KGD_S 8
65 #define PSRAM_ID_KGD 0x5d
66 #define PSRAM_ID_EID_M 0xff
67 #define PSRAM_ID_EID_S 16
68
69 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
70 //
71 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
72 // -------------------------------------
73 // 0 | 0 | 0 | 16
74 // 0 | 0 | 1 | 32
75 // 0 | 1 | 0 | 64
76 #define PSRAM_EID_SIZE_M 0x07
77 #define PSRAM_EID_SIZE_S 5
78
79 typedef enum {
80 PSRAM_EID_SIZE_16MBITS = 0,
81 PSRAM_EID_SIZE_32MBITS = 1,
82 PSRAM_EID_SIZE_64MBITS = 2,
83 } psram_eid_size_t;
84
85 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
86 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
87 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
88 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
89
90 // For the old version 32Mbit psram, using the spicial driver */
91 #define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20)
92 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
93
94 // IO-pins for PSRAM.
95 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
96 // hardcode the flash pins as well, making this code incompatible with either a setup
97 // that has the flash on non-standard pins or ESP32s with built-in flash.
98 #define PSRAM_SPIQ_SD0_IO 7
99 #define PSRAM_SPID_SD1_IO 8
100 #define PSRAM_SPIWP_SD3_IO 10
101 #define PSRAM_SPIHD_SD2_IO 9
102
103 #define FLASH_HSPI_CLK_IO 14
104 #define FLASH_HSPI_CS_IO 15
105 #define PSRAM_HSPI_SPIQ_SD0_IO 12
106 #define PSRAM_HSPI_SPID_SD1_IO 13
107 #define PSRAM_HSPI_SPIWP_SD3_IO 2
108 #define PSRAM_HSPI_SPIHD_SD2_IO 4
109
110 // PSRAM clock and cs IO should be configured based on hardware design.
111 // For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the cs IO is IO16,
112 // they are the default value for these two configs.
113 #define D0WD_PSRAM_CLK_IO CONFIG_D0WD_PSRAM_CLK_IO // Default value is 17
114 #define D0WD_PSRAM_CS_IO CONFIG_D0WD_PSRAM_CS_IO // Default value is 16
115
116 #define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO // Default value is 9
117 #define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO // Default value is 10
118
119 // There is no reason to change the pin of an embedded psram.
120 // So define the number of pin directly, instead of configurable.
121 #define D0WDR2_V3_PSRAM_CLK_IO 6
122 #define D0WDR2_V3_PSRAM_CS_IO 16
123
124 // For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
125 #define PICO_PSRAM_CLK_IO 6
126 #define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10
127
128 #define PICO_V3_02_PSRAM_CLK_IO 10
129 #define PICO_V3_02_PSRAM_CS_IO 9
130
131 typedef enum {
132 PSRAM_CACHE_F80M_S40M = 0,
133 PSRAM_CACHE_F40M_S40M,
134 PSRAM_CACHE_F80M_S80M,
135 PSRAM_CACHE_MAX,
136 } psram_cache_speed_t;
137
138 #if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
139 #define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
140 #define PSRAM_CS_HOLD_TIME 0
141 #elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
142 #define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
143 #define PSRAM_CS_HOLD_TIME 0
144 #elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
145 #define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
146 #define PSRAM_CS_HOLD_TIME 1
147 #else
148 #error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
149 #endif
150
151 typedef struct {
152 uint8_t flash_clk_io;
153 uint8_t flash_cs_io;
154 uint8_t psram_clk_io;
155 uint8_t psram_cs_io;
156 uint8_t psram_spiq_sd0_io;
157 uint8_t psram_spid_sd1_io;
158 uint8_t psram_spiwp_sd3_io;
159 uint8_t psram_spihd_sd2_io;
160 } psram_io_t;
161
162 #define PSRAM_INTERNAL_IO_28 28
163 #define PSRAM_INTERNAL_IO_29 29
164 #define PSRAM_IO_MATRIX_DUMMY_40M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M
165 #define PSRAM_IO_MATRIX_DUMMY_80M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M
166
167 #define _SPI_CACHE_PORT 0
168 #define _SPI_FLASH_PORT 1
169 #define _SPI_80M_CLK_DIV 1
170 #define _SPI_40M_CLK_DIV 2
171
172 //For 4MB PSRAM, we need one more SPI host, select which one to use by kconfig
173 #ifdef CONFIG_SPIRAM_OCCUPY_HSPI_HOST
174 #define PSRAM_SPI_MODULE PERIPH_HSPI_MODULE
175 #define PSRAM_SPI_HOST HSPI_HOST
176 #define PSRAM_CLK_SIGNAL HSPICLK_OUT_IDX
177 #define PSRAM_SPI_NUM PSRAM_SPI_2
178 #define PSRAM_SPICLKEN DPORT_SPI2_CLK_EN
179 #elif defined CONFIG_SPIRAM_OCCUPY_VSPI_HOST
180 #define PSRAM_SPI_MODULE PERIPH_VSPI_MODULE
181 #define PSRAM_SPI_HOST VSPI_HOST
182 #define PSRAM_CLK_SIGNAL VSPICLK_OUT_IDX
183 #define PSRAM_SPI_NUM PSRAM_SPI_3
184 #define PSRAM_SPICLKEN DPORT_SPI3_CLK_EN
185 #else //set to SPI avoid HSPI and VSPI being used
186 #define PSRAM_SPI_MODULE PERIPH_SPI_MODULE
187 #define PSRAM_SPI_HOST SPI_HOST
188 #define PSRAM_CLK_SIGNAL SPICLK_OUT_IDX
189 #define PSRAM_SPI_NUM PSRAM_SPI_1
190 #define PSRAM_SPICLKEN DPORT_SPI01_CLK_EN
191 #endif
192
193 static const char* TAG = "quad_psram";
194 typedef enum {
195 PSRAM_SPI_1 = 0x1,
196 PSRAM_SPI_2,
197 PSRAM_SPI_3,
198 PSRAM_SPI_MAX ,
199 } psram_spi_num_t;
200
201 static psram_cache_speed_t s_psram_mode = PSRAM_CACHE_MAX;
202 static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
203 static uint64_t s_psram_id = 0;
204 static bool s_2t_mode_enabled = false;
205
206 /* dummy_len_plus values defined in ROM for SPI flash configuration */
207 extern uint8_t g_rom_spiflash_dummy_len_plus[];
208 static int extra_dummy = 0;
209 typedef enum {
210 PSRAM_CMD_QPI,
211 PSRAM_CMD_SPI,
212 } psram_cmd_mode_t;
213
214 typedef struct {
215 uint16_t cmd; /*!< Command value */
216 uint16_t cmdBitLen; /*!< Command byte length*/
217 uint32_t *addr; /*!< Point to address value*/
218 uint16_t addrBitLen; /*!< Address byte length*/
219 uint32_t *txData; /*!< Point to send data buffer*/
220 uint16_t txDataBitLen; /*!< Send data byte length.*/
221 uint32_t *rxData; /*!< Point to recevie data buffer*/
222 uint16_t rxDataBitLen; /*!< Recevie Data byte length.*/
223 uint32_t dummyBitLen;
224 } psram_cmd_t;
225
226 static void psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
227
228 static uint8_t s_psram_cs_io = (uint8_t)-1;
229
esp_psram_impl_get_cs_io(void)230 uint8_t esp_psram_impl_get_cs_io(void)
231 {
232 return s_psram_cs_io;
233 }
234
psram_clear_spi_fifo(psram_spi_num_t spi_num)235 static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
236 {
237 int i;
238 for (i = 0; i < 16; i++) {
239 WRITE_PERI_REG(SPI_W0_REG(spi_num)+i*4, 0);
240 }
241 }
242
243 //set basic SPI write mode
psram_set_basic_write_mode(psram_spi_num_t spi_num)244 static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
245 {
246 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
247 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
248 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
249 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
250 }
251 //set QPI write mode
psram_set_qio_write_mode(psram_spi_num_t spi_num)252 static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
253 {
254 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
255 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
256 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
257 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
258 }
259 //set QPI read mode
psram_set_qio_read_mode(psram_spi_num_t spi_num)260 static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
261 {
262 SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
263 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
264 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
265 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
266 }
267 //set SPI read mode
psram_set_basic_read_mode(psram_spi_num_t spi_num)268 static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
269 {
270 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
271 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
272 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
273 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
274 }
275
276
277 //start sending cmd/addr and optionally, receiving data
psram_cmd_recv_start(psram_spi_num_t spi_num,uint32_t * pRxData,uint16_t rxByteLen,psram_cmd_mode_t cmd_mode)278 static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
279 psram_cmd_mode_t cmd_mode)
280 {
281 //get cs1
282 CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
283 SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
284
285 uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
286 uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
287 if (cmd_mode == PSRAM_CMD_SPI) {
288 psram_set_basic_write_mode(spi_num);
289 psram_set_basic_read_mode(spi_num);
290 } else if (cmd_mode == PSRAM_CMD_QPI) {
291 psram_set_qio_write_mode(spi_num);
292 psram_set_qio_read_mode(spi_num);
293 }
294
295 //Wait for SPI0 to idle
296 while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
297 DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
298
299 // Start send data
300 SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
301 while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
302 DPORT_CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
303
304 //recover spi mode
305 SET_PERI_REG_BITS(SPI_USER_REG(spi_num), (pRxData?SPI_FWRITE_DUAL_M:0xf), mode_backup, SPI_FWRITE_DUAL_S);
306 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
307 SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
308
309 //return cs to cs0
310 SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
311 CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
312
313 if (pRxData) {
314 int idx = 0;
315 // Read data out
316 do {
317 *pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));
318 } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
319 }
320 }
321
322 static uint32_t backup_usr[3];
323 static uint32_t backup_usr1[3];
324 static uint32_t backup_usr2[3];
325
326 //setup spi command/addr/data/dummy in user mode
psram_cmd_config(psram_spi_num_t spi_num,psram_cmd_t * pInData)327 static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
328 {
329 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
330 backup_usr[spi_num]=READ_PERI_REG(SPI_USER_REG(spi_num));
331 backup_usr1[spi_num]=READ_PERI_REG(SPI_USER1_REG(spi_num));
332 backup_usr2[spi_num]=READ_PERI_REG(SPI_USER2_REG(spi_num));
333 // Set command by user.
334 if (pInData->cmdBitLen != 0) {
335 // Max command length 16 bits.
336 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
337 SPI_USR_COMMAND_BITLEN_S);
338 // Enable command
339 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
340 // Load command,bit15-0 is cmd value.
341 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
342 } else {
343 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
344 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
345 }
346 // Set Address by user.
347 if (pInData->addrBitLen != 0) {
348 SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_USR_ADDR_BITLEN_S);
349 // Enable address
350 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
351 // Set address
352 WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);
353 } else {
354 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
355 SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
356 }
357 // Set data by user.
358 uint32_t* p_tx_val = pInData->txData;
359 if (pInData->txDataBitLen != 0) {
360 // Enable MOSI
361 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
362 // Load send buffer
363 int len = (pInData->txDataBitLen + 31) / 32;
364 if (p_tx_val != NULL) {
365 memcpy((void*)SPI_W0_REG(spi_num), p_tx_val, len * 4);
366 }
367 // Set data send buffer length.Max data length 64 bytes.
368 SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
369 SPI_USR_MOSI_DBITLEN_S);
370 } else {
371 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
372 SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, 0, SPI_USR_MOSI_DBITLEN_S);
373 }
374 // Set rx data by user.
375 if (pInData->rxDataBitLen != 0) {
376 // Enable MOSI
377 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
378 // Set data send buffer length.Max data length 64 bytes.
379 SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
380 SPI_USR_MISO_DBITLEN_S);
381 } else {
382 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
383 SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
384 }
385 if (pInData->dummyBitLen != 0) {
386 SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
387 SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
388 SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
389 } else {
390 CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
391 SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, 0, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
392 }
393 return 0;
394 }
395
psram_cmd_end(int spi_num)396 static void psram_cmd_end(int spi_num) {
397 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
398 WRITE_PERI_REG(SPI_USER_REG(spi_num), backup_usr[spi_num]);
399 WRITE_PERI_REG(SPI_USER1_REG(spi_num), backup_usr1[spi_num]);
400 WRITE_PERI_REG(SPI_USER2_REG(spi_num), backup_usr2[spi_num]);
401 }
402
403 //exit QPI mode(set back to SPI mode)
psram_disable_qio_mode(psram_spi_num_t spi_num)404 static void psram_disable_qio_mode(psram_spi_num_t spi_num)
405 {
406 psram_cmd_t ps_cmd;
407 uint32_t cmd_exit_qpi;
408 cmd_exit_qpi = PSRAM_EXIT_QMODE;
409 ps_cmd.txDataBitLen = 8;
410 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
411 switch (s_psram_mode) {
412 case PSRAM_CACHE_F80M_S80M:
413 break;
414 case PSRAM_CACHE_F80M_S40M:
415 case PSRAM_CACHE_F40M_S40M:
416 default:
417 cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
418 ps_cmd.txDataBitLen = 16;
419 break;
420 }
421 }
422 ps_cmd.txData = &cmd_exit_qpi;
423 ps_cmd.cmd = 0;
424 ps_cmd.cmdBitLen = 0;
425 ps_cmd.addr = 0;
426 ps_cmd.addrBitLen = 0;
427 ps_cmd.rxData = NULL;
428 ps_cmd.rxDataBitLen = 0;
429 ps_cmd.dummyBitLen = 0;
430 psram_cmd_config(spi_num, &ps_cmd);
431 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
432 psram_cmd_end(spi_num);
433 }
434
435 //read psram id, should issue `psram_disable_qio_mode` before calling this
psram_read_id(psram_spi_num_t spi_num,uint64_t * dev_id)436 static void psram_read_id(psram_spi_num_t spi_num, uint64_t* dev_id)
437 {
438 uint32_t dummy_bits = 0 + extra_dummy;
439 uint32_t psram_id[2] = {0};
440 psram_cmd_t ps_cmd;
441
442 uint32_t addr = 0;
443 ps_cmd.addrBitLen = 3 * 8;
444 ps_cmd.cmd = PSRAM_DEVICE_ID;
445 ps_cmd.cmdBitLen = 8;
446 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
447 switch (s_psram_mode) {
448 case PSRAM_CACHE_F80M_S80M:
449 break;
450 case PSRAM_CACHE_F80M_S40M:
451 case PSRAM_CACHE_F40M_S40M:
452 default:
453 ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle
454 ps_cmd.cmd = 0;
455 addr = (PSRAM_DEVICE_ID << 24) | 0;
456 ps_cmd.addrBitLen = 4 * 8;
457 break;
458 }
459 }
460 ps_cmd.addr = &addr;
461 ps_cmd.txDataBitLen = 0;
462 ps_cmd.txData = NULL;
463 ps_cmd.rxDataBitLen = 8 * 8;
464 ps_cmd.rxData = psram_id;
465 ps_cmd.dummyBitLen = dummy_bits;
466
467 psram_cmd_config(spi_num, &ps_cmd);
468 psram_clear_spi_fifo(spi_num);
469 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
470 psram_cmd_end(spi_num);
471 *dev_id = (uint64_t)(((uint64_t)psram_id[1] << 32) | psram_id[0]);
472 }
473
474 //enter QPI mode
psram_enable_qio_mode(psram_spi_num_t spi_num)475 static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
476 {
477 psram_cmd_t ps_cmd;
478 uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
479
480 ps_cmd.cmdBitLen = 0;
481 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
482 switch (s_psram_mode) {
483 case PSRAM_CACHE_F80M_S80M:
484 break;
485 case PSRAM_CACHE_F80M_S40M:
486 case PSRAM_CACHE_F40M_S40M:
487 default:
488 ps_cmd.cmdBitLen = 2;
489 break;
490 }
491 }
492 ps_cmd.cmd = 0;
493 ps_cmd.addr = &addr;
494 ps_cmd.addrBitLen = 8;
495 ps_cmd.txData = NULL;
496 ps_cmd.txDataBitLen = 0;
497 ps_cmd.rxData = NULL;
498 ps_cmd.rxDataBitLen = 0;
499 ps_cmd.dummyBitLen = 0;
500 psram_cmd_config(spi_num, &ps_cmd);
501 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
502 psram_cmd_end(spi_num);
503 return ESP_OK;
504 }
505
506 #if CONFIG_SPIRAM_2T_MODE
507 // use SPI user mode to write psram
spi_user_psram_write(psram_spi_num_t spi_num,uint32_t address,uint32_t * data_buffer,uint32_t data_len)508 static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
509 {
510 uint32_t addr = (PSRAM_QUAD_WRITE << 24) | (address & 0x7fffff);
511 psram_cmd_t ps_cmd;
512 ps_cmd.cmdBitLen = 0;
513 ps_cmd.cmd = 0;
514 ps_cmd.addr = &addr;
515 ps_cmd.addrBitLen = 4 * 8;
516 ps_cmd.txDataBitLen = 32 * 8;
517 ps_cmd.txData = NULL;
518 ps_cmd.rxDataBitLen = 0;
519 ps_cmd.rxData = NULL;
520 ps_cmd.dummyBitLen = 0;
521
522 for(uint32_t i=0; i<data_len; i+=32) {
523 psram_clear_spi_fifo(spi_num);
524 addr = (PSRAM_QUAD_WRITE << 24) | ((address & 0x7fffff) + i);
525 ps_cmd.txData = data_buffer + (i / 4);
526 psram_cmd_config(spi_num, &ps_cmd);
527 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
528 }
529 psram_cmd_end(spi_num);
530 }
531
532 // use SPI user mode to read psram
spi_user_psram_read(psram_spi_num_t spi_num,uint32_t address,uint32_t * data_buffer,uint32_t data_len)533 static void spi_user_psram_read(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
534 {
535 uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | (address & 0x7fffff);
536 uint32_t dummy_bits = PSRAM_FAST_READ_QUAD_DUMMY + 1;
537 psram_cmd_t ps_cmd;
538 ps_cmd.cmdBitLen = 0;
539 ps_cmd.cmd = 0;
540 ps_cmd.addr = &addr;
541 ps_cmd.addrBitLen = 4 * 8;
542 ps_cmd.txDataBitLen = 0;
543 ps_cmd.txData = NULL;
544 ps_cmd.rxDataBitLen = 32 * 8;
545 ps_cmd.dummyBitLen = dummy_bits + extra_dummy;
546
547 for(uint32_t i=0; i<data_len; i+=32) {
548 psram_clear_spi_fifo(spi_num);
549 addr = (PSRAM_FAST_READ_QUAD << 24) | ((address & 0x7fffff) + i);
550 ps_cmd.rxData = data_buffer + (i / 4);
551 psram_cmd_config(spi_num, &ps_cmd);
552 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
553 }
554 psram_cmd_end(spi_num);
555 }
556
557 //enable psram 2T mode
psram_2t_mode_enable(psram_spi_num_t spi_num)558 static esp_err_t IRAM_ATTR psram_2t_mode_enable(psram_spi_num_t spi_num)
559 {
560 psram_disable_qio_mode(spi_num);
561 // configure psram clock as 5 MHz
562 uint32_t div = rtc_clk_apb_freq_get() / 5000000;
563 esp_rom_spiflash_config_clk(div, spi_num);
564
565 psram_cmd_t ps_cmd;
566
567 // setp1: send cmd 0x5e
568 // send one more bit clock after send cmd
569 ps_cmd.cmd = 0x5e;
570 ps_cmd.cmdBitLen = 8;
571 ps_cmd.addrBitLen = 0;
572 ps_cmd.addr = 0;
573 ps_cmd.txDataBitLen = 0;
574 ps_cmd.txData = NULL;
575 ps_cmd.rxDataBitLen =0;
576 ps_cmd.rxData = NULL;
577 ps_cmd.dummyBitLen = 1;
578 psram_cmd_config(spi_num, &ps_cmd);
579 psram_clear_spi_fifo(spi_num);
580 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
581 psram_cmd_end(spi_num);
582
583 // setp2: send cmd 0x5f
584 // send one more bit clock after send cmd
585 ps_cmd.cmd = 0x5f;
586 psram_cmd_config(spi_num, &ps_cmd);
587 psram_clear_spi_fifo(spi_num);
588 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
589 psram_cmd_end(spi_num);
590
591 // setp3: keep cs as high level
592 // send 128 cycles clock
593 // send 1 bit high levle in ninth clock from the back to PSRAM SIO1
594 GPIO_OUTPUT_SET(D0WD_PSRAM_CS_IO, 1);
595 esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
596
597 esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
598 esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
599 esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
600 esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
601
602 uint32_t w_data_2t[4] = {0x0, 0x0, 0x0, 0x00010000};
603
604 ps_cmd.cmd = 0;
605 ps_cmd.cmdBitLen = 0;
606 ps_cmd.txDataBitLen = 128;
607 ps_cmd.txData = w_data_2t;
608 ps_cmd.dummyBitLen = 0;
609 psram_clear_spi_fifo(spi_num);
610 psram_cmd_config(spi_num, &ps_cmd);
611 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
612 psram_cmd_end(spi_num);
613
614 esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
615 esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
616 esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
617 esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
618
619 esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
620
621 // setp4: send cmd 0x5f
622 // send one more bit clock after send cmd
623 ps_cmd.cmd = 0x5f;
624 ps_cmd.cmdBitLen = 8;
625 ps_cmd.txDataBitLen = 0;
626 ps_cmd.txData = NULL;
627 ps_cmd.dummyBitLen = 1;
628 psram_cmd_config(spi_num, &ps_cmd);
629 psram_clear_spi_fifo(spi_num);
630 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
631 psram_cmd_end(spi_num);
632
633 // configure psram clock back to the default value
634 switch (s_psram_mode) {
635 case PSRAM_CACHE_F80M_S40M:
636 case PSRAM_CACHE_F40M_S40M:
637 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, spi_num);
638 break;
639 case PSRAM_CACHE_F80M_S80M:
640 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, spi_num);
641 break;
642 default:
643 break;
644 }
645 psram_enable_qio_mode(spi_num);
646 return ESP_OK;
647 }
648
649 #define CHECK_DATA_LEN (1024)
650 #define CHECK_ADDR_STEP (0x100000)
651 #define SIZE_32MBIT (0x400000)
652 #define SIZE_64MBIT (0x800000)
653
psram_2t_mode_check(psram_spi_num_t spi_num)654 static esp_err_t psram_2t_mode_check(psram_spi_num_t spi_num)
655 {
656 uint8_t w_check_data[CHECK_DATA_LEN] = {0};
657 uint8_t r_check_data[CHECK_DATA_LEN] = {0};
658
659 for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
660 spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
661 }
662
663 memset(w_check_data, 0xff, sizeof(w_check_data));
664
665 for (uint32_t addr=SIZE_32MBIT; addr<SIZE_64MBIT; addr+=CHECK_ADDR_STEP) {
666 spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
667 }
668
669 for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
670 spi_user_psram_read(spi_num, addr, (uint32_t *)r_check_data, CHECK_DATA_LEN);
671 for (uint32_t j=0; j<CHECK_DATA_LEN; j++) {
672 if (r_check_data[j] != 0xff) {
673 return ESP_FAIL;
674 }
675 }
676 }
677
678 return ESP_OK;
679 }
680 #endif
681
psram_set_cs_timing(psram_spi_num_t spi_num,psram_clk_mode_t clk_mode)682 void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
683 {
684 if (clk_mode == PSRAM_CLK_MODE_NORM) {
685 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
686 // Set cs time.
687 SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, PSRAM_CS_HOLD_TIME, SPI_HOLD_TIME_S);
688 SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
689 } else {
690 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
691 }
692 }
693
694 //spi param init for psram
psram_spi_init(psram_spi_num_t spi_num,psram_cache_speed_t mode)695 void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_speed_t mode)
696 {
697 CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5);
698 // SPI_CPOL & SPI_CPHA
699 CLEAR_PERI_REG_MASK(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE);
700 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE);
701 // SPI bit order
702 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER);
703 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER);
704 // SPI bit order
705 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_DOUTDIN);
706 // May be not must to do.
707 WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);
708 // SPI mode type
709 CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
710 memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
711 psram_set_cs_timing(spi_num, s_clk_mode);
712 }
713
714 //psram gpio init , different working frequency we have different solutions
psram_gpio_config(psram_io_t * psram_io,psram_cache_speed_t mode)715 static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_t mode)
716 {
717 int spi_cache_dummy = 0;
718 uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
719 if (rd_mode_reg & SPI_FREAD_QIO_M) {
720 spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
721 } else if (rd_mode_reg & SPI_FREAD_DIO_M) {
722 spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
723 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
724 } else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
725 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
726 } else {
727 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
728 }
729
730 switch (mode) {
731 case PSRAM_CACHE_F80M_S40M:
732 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
733 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
734 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
735 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
736 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
737 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
738 //set drive ability for clock
739 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
740 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
741 break;
742 case PSRAM_CACHE_F80M_S80M:
743 extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
744 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
745 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
746 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
747 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
748 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT);
749 //set drive ability for clock
750 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
751 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 3, FUN_DRV_S);
752 break;
753 case PSRAM_CACHE_F40M_S40M:
754 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
755 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
756 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
757 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
758 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT);
759 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
760 //set drive ability for clock
761 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 2, FUN_DRV_S);
762 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
763 break;
764 default:
765 break;
766 }
767 SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy enable
768
769 // In bootloader, all the signals are already configured,
770 // We keep the following code in case the bootloader is some older version.
771 esp_rom_gpio_connect_out_signal(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
772 esp_rom_gpio_connect_out_signal(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
773 esp_rom_gpio_connect_out_signal(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
774 esp_rom_gpio_connect_in_signal(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
775 esp_rom_gpio_connect_out_signal(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
776 esp_rom_gpio_connect_in_signal(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
777 esp_rom_gpio_connect_out_signal(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
778 esp_rom_gpio_connect_in_signal(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
779 esp_rom_gpio_connect_out_signal(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
780 esp_rom_gpio_connect_in_signal(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
781
782 //select pin function gpio
783 if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
784 //flash clock signal should come from IO MUX.
785 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
786 } else {
787 //flash clock signal should come from GPIO matrix.
788 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);
789 }
790 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO);
791 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO);
792 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO);
793 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO);
794 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO);
795 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO);
796 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO);
797
798 uint32_t flash_id = g_rom_flashchip.device_id;
799 if (flash_id == FLASH_ID_GD25LQ32C) {
800 // Set drive ability for 1.8v flash in 80Mhz.
801 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
802 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
803 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
804 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
805 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], FUN_DRV_V, 3, FUN_DRV_S);
806 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], FUN_DRV_V, 3, FUN_DRV_S);
807 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], FUN_DRV_V, 3, FUN_DRV_S);
808 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], FUN_DRV_V, 3, FUN_DRV_S);
809 }
810
811 // Reserve psram pins
812 esp_gpio_reserve_pins(BIT64(psram_io->flash_clk_io) |
813 BIT64(psram_io->flash_cs_io) |
814 BIT64(psram_io->psram_clk_io) |
815 BIT64(psram_io->psram_cs_io) |
816 BIT64(psram_io->psram_spiq_sd0_io) |
817 BIT64(psram_io->psram_spid_sd1_io) |
818 BIT64(psram_io->psram_spihd_sd2_io) |
819 BIT64(psram_io->psram_spiwp_sd3_io) );
820 }
821
822 //used in UT only
psram_is_32mbit_ver0(void)823 bool psram_is_32mbit_ver0(void)
824 {
825 return PSRAM_IS_32MBIT_VER0(s_psram_id);
826 }
827
828 /*
829 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
830 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
831 */
esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)832 esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init
833 {
834 psram_cache_speed_t mode = PSRAM_SPEED;
835 psram_io_t psram_io={0};
836 uint32_t pkg_ver = efuse_ll_get_chip_ver_pkg();
837 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
838 ESP_EARLY_LOGI(TAG, "This chip is ESP32-D2WD");
839 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
840 if (cfg.tieh != RTC_VDDSDIO_TIEH_1_8V) {
841 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 1.8V");
842 return ESP_FAIL;
843 }
844 psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
845 psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
846 } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
847 ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
848 abort();
849 } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
850 ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
851 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
852 if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
853 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
854 return ESP_FAIL;
855 }
856 s_clk_mode = PSRAM_CLK_MODE_NORM;
857 psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
858 psram_io.psram_cs_io = PICO_PSRAM_CS_IO;
859 } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
860 ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO-V3-02");
861 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
862 if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
863 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
864 return ESP_FAIL;
865 }
866 s_clk_mode = PSRAM_CLK_MODE_NORM;
867 psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO;
868 psram_io.psram_cs_io = PICO_V3_02_PSRAM_CS_IO;
869 } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){
870 ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD");
871 psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO;
872 psram_io.psram_cs_io = D0WD_PSRAM_CS_IO;
873 } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3){
874 ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WDR2-V3");
875 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
876 if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
877 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
878 return ESP_FAIL;
879 }
880 s_clk_mode = PSRAM_CLK_MODE_NORM;
881 psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
882 psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
883 } else {
884 ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
885 abort();
886 }
887 s_psram_cs_io = psram_io.psram_cs_io;
888
889 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
890 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
891 psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK;
892 psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS;
893 psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO;
894 psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO;
895 psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO;
896 psram_io.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO;
897 } else if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
898 psram_io.flash_clk_io = FLASH_HSPI_CLK_IO;
899 psram_io.flash_cs_io = FLASH_HSPI_CS_IO;
900 psram_io.psram_spiq_sd0_io = PSRAM_HSPI_SPIQ_SD0_IO;
901 psram_io.psram_spid_sd1_io = PSRAM_HSPI_SPID_SD1_IO;
902 psram_io.psram_spiwp_sd3_io = PSRAM_HSPI_SPIWP_SD3_IO;
903 psram_io.psram_spihd_sd2_io = PSRAM_HSPI_SPIHD_SD2_IO;
904 } else {
905 psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
906 psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
907 psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
908 psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
909 psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
910 psram_io.psram_spiwp_sd3_io = flash_get_wp_pin();
911 }
912
913 assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
914 s_psram_mode = mode;
915
916 WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);
917 CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
918
919 psram_spi_init(PSRAM_SPI_1, mode);
920
921 switch (mode) {
922 case PSRAM_CACHE_F80M_S80M:
923 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
924 break;
925 case PSRAM_CACHE_F80M_S40M:
926 case PSRAM_CACHE_F40M_S40M:
927 default:
928 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
929 /* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
930 We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
931 the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
932 silicon) as a temporary pad for this. So the signal path is:
933 SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
934 */
935 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
936 esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
937 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
938 esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
939 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0);
940 } else {
941 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
942 }
943 break;
944 }
945
946 // Rise VDDSIO for 1.8V psram.
947 #if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
948 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
949 if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1.8V
950 cfg.drefh = 3;
951 cfg.drefm = 3;
952 cfg.drefl = 3;
953 cfg.force = 1;
954 rtc_vddsdio_set_config(cfg);
955 esp_rom_delay_us(10); // wait for regulator to become stable
956 }
957 #endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
958 // GPIO related settings
959 psram_gpio_config(&psram_io, mode);
960
961 psram_spi_num_t spi_num = PSRAM_SPI_1;
962 psram_disable_qio_mode(spi_num);
963 psram_read_id(spi_num, &s_psram_id);
964 if (!PSRAM_IS_VALID(s_psram_id)) {
965 /* 16Mbit psram ID read error workaround:
966 * treat the first read id as a dummy one as the pre-condition,
967 * Send Read ID command again
968 */
969 psram_read_id(spi_num, &s_psram_id);
970 if (!PSRAM_IS_VALID(s_psram_id)) {
971 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported", (uint32_t)s_psram_id);
972 return ESP_ERR_NOT_SUPPORTED;
973 }
974 }
975
976 if (psram_is_32mbit_ver0()) {
977 s_clk_mode = PSRAM_CLK_MODE_DCLK;
978 if (mode == PSRAM_CACHE_F80M_S80M) {
979 #ifdef CONFIG_SPIRAM_OCCUPY_NO_HOST
980 ESP_EARLY_LOGE(TAG, "This version of PSRAM needs to claim an extra SPI peripheral at 80MHz. Please either: choose lower frequency by SPIRAM_SPEED_, or select one SPI peripheral it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig.");
981 abort();
982 #else
983 /* note: If the third mode(80Mhz+80Mhz) is enabled for 32MBit 1V8 psram, one of HSPI/VSPI port will be
984 occupied by the system (according to kconfig).
985 Application code should never touch HSPI/VSPI hardware in this case. We try to stop applications
986 from doing this using the drivers by claiming the port for ourselves */
987 periph_module_enable(PSRAM_SPI_MODULE);
988 bool r=spicommon_periph_claim(PSRAM_SPI_HOST, "psram");
989 if (!r) {
990 return ESP_ERR_INVALID_STATE;
991 }
992 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0);
993 //use spi3 clock,but use spi1 data/cs wires
994 //We get a solid 80MHz clock from SPI3 by setting it up, starting a transaction, waiting until it
995 //is in progress, then cutting the clock (but not the reset!) to that peripheral.
996 WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_NUM), 32 << 24);
997 SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_NUM), SPI_FLASH_READ_M);
998 uint32_t spi_status;
999 while (1) {
1000 spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_NUM));
1001 if (spi_status != 0 && spi_status != 1) {
1002 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, PSRAM_SPICLKEN);
1003 break;
1004 }
1005 }
1006 #endif
1007 }
1008 } else {
1009 // For other psram, we don't need any extra clock cycles after cs get back to high level
1010 s_clk_mode = PSRAM_CLK_MODE_NORM;
1011 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
1012 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
1013 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
1014 }
1015
1016 // Update cs timing according to psram driving method.
1017 psram_set_cs_timing(PSRAM_SPI_1, s_clk_mode);
1018 psram_set_cs_timing(_SPI_CACHE_PORT, s_clk_mode);
1019 psram_enable_qio_mode(PSRAM_SPI_1);
1020
1021 if(((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id))) {
1022 #if CONFIG_SPIRAM_2T_MODE
1023 #if CONFIG_SPIRAM_BANKSWITCH_ENABLE
1024 ESP_EARLY_LOGE(TAG, "PSRAM 2T mode and SPIRAM bank switching can not enabled meanwhile. Please read the help text for SPIRAM_2T_MODE in the project configuration menu.");
1025 abort();
1026 #endif
1027 /* Note: 2T mode command should not be sent twice,
1028 otherwise psram would get back to normal mode. */
1029 if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
1030 psram_2t_mode_enable(PSRAM_SPI_1);
1031 if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
1032 ESP_EARLY_LOGE(TAG, "PSRAM 2T mode enable fail!");
1033 return ESP_FAIL;
1034 }
1035 }
1036 s_2t_mode_enabled = true;
1037 ESP_EARLY_LOGI(TAG, "PSRAM is in 2T mode");
1038 #endif
1039 }
1040
1041 psram_cache_init(mode, vaddrmode);
1042 return ESP_OK;
1043 }
1044
1045 //register initialization for sram cache params and r/w commands
psram_cache_init(psram_cache_speed_t psram_cache_mode,psram_vaddr_mode_t vaddrmode)1046 static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
1047 {
1048 switch (psram_cache_mode) {
1049 case PSRAM_CACHE_F80M_S80M:
1050 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk,80+40;
1051 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
1052 break;
1053 case PSRAM_CACHE_F80M_S40M:
1054 CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M);
1055 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, SPI_CLKDIV_PRE_S);
1056 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
1057 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
1058 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
1059 SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
1060 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
1061 break;
1062 case PSRAM_CACHE_F40M_S40M:
1063 default:
1064 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
1065 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
1066 break;
1067 }
1068
1069 CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cache command
1070 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache command
1071 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable cache read command
1072 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); //enable cache write command
1073 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //write address for cache command.
1074 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
1075
1076 //config sram cache r/w command
1077 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
1078 SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
1079 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
1080 SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
1081 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
1082 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
1083 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
1084 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
1085 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
1086 SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
1087
1088 switch (psram_cache_mode) {
1089 case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
1090 break;
1091 case PSRAM_CACHE_F80M_S40M: //if sram is @40M, need 2 cycles of delay
1092 case PSRAM_CACHE_F40M_S40M:
1093 default:
1094 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
1095 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
1096 SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
1097 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ_QUAD) << 8),
1098 SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB, read command value,(0x00 for delay,0xeb for cmd)
1099 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
1100 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
1101 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
1102 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
1103 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
1104 SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
1105 }
1106 break;
1107 }
1108
1109 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
1110 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
1111 if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
1112 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
1113 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
1114 } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
1115 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
1116 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
1117 }
1118
1119 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
1120 //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
1121 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
1122 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
1123 //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
1124 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
1125
1126 CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
1127 }
1128
1129
esp_psram_impl_get_physical_size(uint32_t * out_size_bytes)1130 esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
1131 {
1132 if (!out_size_bytes) {
1133 return ESP_ERR_INVALID_ARG;
1134 }
1135
1136 if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
1137 *out_size_bytes = s_2t_mode_enabled ? PSRAM_SIZE_4MB : PSRAM_SIZE_8MB;
1138 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
1139 *out_size_bytes = PSRAM_SIZE_4MB;
1140 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
1141 *out_size_bytes = PSRAM_SIZE_2MB;
1142 } else {
1143 return ESP_ERR_NOT_SUPPORTED;
1144 }
1145 return ESP_OK;
1146 }
1147
1148 /**
1149 * This function is to get the available physical psram size in bytes.
1150 * On ESP32, all of the PSRAM physical region are available
1151 */
esp_psram_impl_get_available_size(uint32_t * out_size_bytes)1152 esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
1153 {
1154 return esp_psram_impl_get_physical_size(out_size_bytes);
1155 }
1156 #endif // CONFIG_SPIRAM
1157
