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Searched refs:period_cycles (Results 1 – 25 of 47) sorted by relevance

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/Zephyr-latest/drivers/pwm/
Dpwm_imx.c30 uint32_t period_cycles; member
50 uint32_t period_cycles, uint32_t pulse_cycles, in imx_pwm_set_cycles() argument
61 if (period_cycles == 0U) { in imx_pwm_set_cycles()
72 " duty_cycle=%d\n", enabled, pulse_cycles, period_cycles, in imx_pwm_set_cycles()
73 (pulse_cycles * 100U / period_cycles)); in imx_pwm_set_cycles()
113 if (period_cycles > 2) { in imx_pwm_set_cycles()
114 period_cycles -= 2U; in imx_pwm_set_cycles()
121 if (data->period_cycles != period_cycles) { in imx_pwm_set_cycles()
123 data->period_cycles, period_cycles, in imx_pwm_set_cycles()
126 data->period_cycles = period_cycles; in imx_pwm_set_cycles()
[all …]
Dpwm_rv32m1_tpm.c39 uint32_t period_cycles; member
44 uint32_t period_cycles, uint32_t pulse_cycles, in rv32m1_tpm_set_cycles() argument
51 if (period_cycles == 0U) { in rv32m1_tpm_set_cycles()
61 duty_cycle = pulse_cycles * 100U / period_cycles; in rv32m1_tpm_set_cycles()
71 pulse_cycles, period_cycles, duty_cycle, flags); in rv32m1_tpm_set_cycles()
73 if (period_cycles != data->period_cycles) { in rv32m1_tpm_set_cycles()
77 if (data->period_cycles != 0) { in rv32m1_tpm_set_cycles()
81 data->period_cycles, period_cycles, in rv32m1_tpm_set_cycles()
85 data->period_cycles = period_cycles; in rv32m1_tpm_set_cycles()
88 period_cycles; in rv32m1_tpm_set_cycles()
Dpwm_rcar.c90 uint32_t *period_cycles, uint32_t *pulse_cycles) in pwm_rcar_update_clk() argument
101 if (*period_cycles > RCAR_PWM_MAX_CYCLE) { in pwm_rcar_update_clk()
103 while (*period_cycles > RCAR_PWM_MAX_CYCLE) { in pwm_rcar_update_clk()
105 *period_cycles /= 2; in pwm_rcar_update_clk()
114 while (*period_cycles < (RCAR_PWM_MAX_CYCLE / 2)) { in pwm_rcar_update_clk()
119 *period_cycles *= 2; in pwm_rcar_update_clk()
135 static int pwm_rcar_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, in pwm_rcar_set_cycles() argument
151 if (period_cycles == 0U || pulse_cycles == 0U || pulse_cycles > period_cycles) { in pwm_rcar_set_cycles()
157 config->reg_addr, pulse_cycles, period_cycles, in pwm_rcar_set_cycles()
158 (pulse_cycles * 100U / period_cycles)); in pwm_rcar_set_cycles()
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Dpwm_mcux_tpm.c44 uint32_t period_cycles; member
49 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_tpm_set_cycles() argument
56 if (period_cycles == 0U) { in mcux_tpm_set_cycles()
66 duty_cycle = pulse_cycles * 100U / period_cycles; in mcux_tpm_set_cycles()
76 pulse_cycles, period_cycles, duty_cycle, flags); in mcux_tpm_set_cycles()
78 if (period_cycles != data->period_cycles) { in mcux_tpm_set_cycles()
82 if (data->period_cycles != 0) { in mcux_tpm_set_cycles()
86 data->period_cycles, period_cycles, in mcux_tpm_set_cycles()
90 data->period_cycles = period_cycles; in mcux_tpm_set_cycles()
93 period_cycles; in mcux_tpm_set_cycles()
Dpwm_mcux.c37 uint32_t period_cycles[CHANNEL_COUNT]; member
43 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_pwm_set_cycles_internal() argument
56 if (period_cycles != data->period_cycles[channel] in mcux_pwm_set_cycles_internal()
61 data->period_cycles[channel] = period_cycles; in mcux_pwm_set_cycles_internal()
95 (uint16_t)(period_cycles / 2U)); in mcux_pwm_set_cycles_internal()
98 (uint16_t)(period_cycles - 1U)); in mcux_pwm_set_cycles_internal()
108 (uint16_t)(period_cycles / 2U)); in mcux_pwm_set_cycles_internal()
111 (uint16_t)(period_cycles - 1U)); in mcux_pwm_set_cycles_internal()
146 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_pwm_set_cycles() argument
157 if (period_cycles == 0) { in mcux_pwm_set_cycles()
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Dpwm_mcux_sctimer.c43 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_new_channel() argument
51 data->match_period = period_cycles; in mcux_sctimer_new_channel()
58 pwm_freq = (clock_freq / config->prescale) / period_cycles; in mcux_sctimer_new_channel()
82 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_pwm_set_cycles() argument
95 if (period_cycles == 0) { in mcux_sctimer_pwm_set_cycles()
106 duty_cycle = 100 * pulse_cycles / period_cycles; in mcux_sctimer_pwm_set_cycles()
139 if (period_cycles != data->match_period && in mcux_sctimer_pwm_set_cycles()
145 ret = mcux_sctimer_new_channel(dev, channel, period_cycles, in mcux_sctimer_pwm_set_cycles()
155 if (period_cycles != data->match_period) { in mcux_sctimer_pwm_set_cycles()
161 ret = mcux_sctimer_new_channel(dev, channel, period_cycles, in mcux_sctimer_pwm_set_cycles()
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Dpwm_nrf_sw.c73 uint32_t period_cycles; member
98 uint32_t channel, uint32_t period_cycles, in pwm_period_check() argument
104 if ((pulse_cycles == 0U) || (pulse_cycles == period_cycles)) { in pwm_period_check()
112 (period_cycles != data->period_cycles)) { in pwm_period_check()
121 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nrf_sw_set_cycles() argument
144 ret = pwm_period_check(data, config->map_size, channel, period_cycles, in pwm_nrf_sw_set_cycles()
153 if (period_cycles > BIT_MASK(24) + 1) { in pwm_nrf_sw_set_cycles()
154 LOG_ERR("Too long period (%u)!", period_cycles); in pwm_nrf_sw_set_cycles()
159 period_cycles > BIT_MASK(GENERATOR_BITS)) { in pwm_nrf_sw_set_cycles()
161 period_cycles); in pwm_nrf_sw_set_cycles()
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Dpwm_xlnx_axi_timer.c66 uint32_t period_cycles, in xlnx_axi_timer_set_cycles() argument
79 LOG_DBG("period = 0x%08x, pulse = 0x%08x", period_cycles, pulse_cycles); in xlnx_axi_timer_set_cycles()
89 } else if (pulse_cycles == period_cycles) { in xlnx_axi_timer_set_cycles()
100 if (period_cycles < 2) { in xlnx_axi_timer_set_cycles()
106 tlr0 = period_cycles - 2; in xlnx_axi_timer_set_cycles()
122 if ((period_cycles - pulse_cycles) < 2) { in xlnx_axi_timer_set_cycles()
128 tlr1 = period_cycles - pulse_cycles - 2; in xlnx_axi_timer_set_cycles()
Dpwm_mcux_ctimer.c129 uint32_t period_cycles) in mcux_ctimer_pwm_update_state() argument
141 data->channel_states[period_channel].cycles = period_cycles; in mcux_ctimer_pwm_update_state()
145 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_ctimer_pwm_set_cycles() argument
159 if (period_cycles == 0) { in mcux_ctimer_pwm_set_cycles()
164 ret = mcux_ctimer_pwm_select_period_channel(data, pulse_channel, period_cycles, in mcux_ctimer_pwm_set_cycles()
174 pulse_cycles = period_cycles + 1; in mcux_ctimer_pwm_set_cycles()
176 pulse_cycles = period_cycles - pulse_cycles; in mcux_ctimer_pwm_set_cycles()
180 status = CTIMER_SetupPwmPeriod(config->base, period_channel, pulse_channel, period_cycles, in mcux_ctimer_pwm_set_cycles()
187 period_cycles); in mcux_ctimer_pwm_set_cycles()
Dpwm_nrfx.c55 uint32_t period_cycles; member
80 uint32_t channel, uint32_t period_cycles) in pwm_period_check_and_set() argument
90 if (period_cycles == data->period_cycles) { in pwm_period_check_and_set()
107 countertop = period_cycles; in pwm_period_check_and_set()
110 data->period_cycles = period_cycles; in pwm_period_check_and_set()
124 LOG_ERR("Prescaler for period_cycles %u not found.", period_cycles); in pwm_period_check_and_set()
138 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nrfx_set_cycles() argument
162 period_cycles /= 2; in pwm_nrfx_set_cycles()
169 } else if (pulse_cycles >= period_cycles) { in pwm_nrfx_set_cycles()
178 if (!pwm_period_check_and_set(dev, channel, period_cycles)) { in pwm_nrfx_set_cycles()
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Dpwm_xmc4xxx_ccu4.c52 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu4_set_cycles() argument
63 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu4_set_cycles()
68 slice->PRS = period_cycles - 1; in pwm_xmc4xxx_ccu4_set_cycles()
69 slice->CRS = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu4_set_cycles()
Dpwm_handlers.c52 uint32_t *period_cycles, in z_vrfy_pwm_capture_cycles() argument
66 if (period_cycles != NULL) { in z_vrfy_pwm_capture_cycles()
67 K_OOPS(k_usermode_to_copy(period_cycles, &period, in z_vrfy_pwm_capture_cycles()
68 sizeof(*period_cycles))); in z_vrfy_pwm_capture_cycles()
Dpwm_sifive.c110 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_sifive_set_cycles() argument
137 if (period_cycles > count_max) { in pwm_sifive_set_cycles()
139 period_cycles, count_max); in pwm_sifive_set_cycles()
150 while ((period_cycles >> pwmscale) > max_cmp_val) { in pwm_sifive_set_cycles()
157 period_cycles, max_cmp_val << pwmscale); in pwm_sifive_set_cycles()
167 sys_write32((period_cycles >> pwmscale), PWM_REG(config, REG_PWMCMP0)); in pwm_sifive_set_cycles()
176 (period_cycles >> pwmscale), in pwm_sifive_set_cycles()
Dpwm_sam.c47 uint32_t period_cycles, uint32_t pulse_cycles, in sam_pwm_set_cycles() argument
59 if (period_cycles == 0U) { in sam_pwm_set_cycles()
63 if (period_cycles > 0xffff) { in sam_pwm_set_cycles()
79 pwm->PWM_CH_NUM[channel].PWM_CPRD = period_cycles; in sam_pwm_set_cycles()
85 pwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period_cycles; in sam_pwm_set_cycles()
Dpwm_ifx_cat1.c93 uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags) in ifx_cat1_pwm_set_cycles() argument
99 ((period_cycles > UINT16_MAX) || (pulse_cycles > UINT16_MAX))) { in ifx_cat1_pwm_set_cycles()
101 if (period_cycles > UINT16_MAX) { in ifx_cat1_pwm_set_cycles()
102 LOG_ERR("Period cycles more than 16-bits (%u)", period_cycles); in ifx_cat1_pwm_set_cycles()
110 if ((period_cycles == 0) || (pulse_cycles == 0)) { in ifx_cat1_pwm_set_cycles()
113 Cy_TCPWM_PWM_SetPeriod0(PWM_REG_BASE, data->pwm_num, period_cycles); in ifx_cat1_pwm_set_cycles()
Dpwm_nxp_flexio.c89 uint32_t period_cycles[FLEXIO_MAX_PWM_CHANNELS]; member
94 uint32_t channel, uint32_t period_cycles, in pwm_nxp_flexio_set_cycles() argument
111 if (period_cycles == 0) { in pwm_nxp_flexio_set_cycles()
121 if (FLEXIO_PWM_TIMER_CMP_MAX_VALUE <= (uint16_t)(period_cycles - pulse_cycles)) { in pwm_nxp_flexio_set_cycles()
126 if (pulse_cycles > period_cycles) { in pwm_nxp_flexio_set_cycles()
148 data->period_cycles[channel] = period_cycles; in pwm_nxp_flexio_set_cycles()
151 ((uint8_t)(data->period_cycles[channel] - pulse_cycles - 1U) in pwm_nxp_flexio_set_cycles()
189 if (data->period_cycles[channel] == 0) { in pwm_nxp_flexio_get_cycles_per_sec()
196 ((data->period_cycles[channel]) * (pwm_info->prescaler_div))); in pwm_nxp_flexio_get_cycles_per_sec()
Dpwm_xmc4xxx_ccu8.c88 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu8_set_cycles() argument
101 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu8_set_cycles()
106 slice->PRS = period_cycles - 1; in pwm_xmc4xxx_ccu8_set_cycles()
109 slice->CR2S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
111 slice->CR1S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
Dpwm_mcux_ftm.c56 uint32_t period_cycles; member
65 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_ftm_set_cycles() argument
76 if (period_cycles == 0U) { in mcux_ftm_set_cycles()
81 if (period_cycles > UINT16_MAX) { in mcux_ftm_set_cycles()
108 pulse_cycles, period_cycles, flags); in mcux_ftm_set_cycles()
110 if (period_cycles != data->period_cycles) { in mcux_ftm_set_cycles()
118 if (data->period_cycles != 0) { in mcux_ftm_set_cycles()
122 data->period_cycles, period_cycles, in mcux_ftm_set_cycles()
126 data->period_cycles = period_cycles; in mcux_ftm_set_cycles()
129 FTM_SetTimerPeriod(config->base, period_cycles); in mcux_ftm_set_cycles()
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Dpwm_max32.c32 uint32_t period_cycles; member
35 static int api_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, in api_set_cycles() argument
52 pwm_cfg.cmp_cnt = period_cycles; in api_set_cycles()
57 pulse_cycles = period_cycles; in api_set_cycles()
Dpwm_ene_kb1200.c27 static int pwm_kb1200_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, in pwm_kb1200_set_cycles() argument
42 prescaler = DIV_ROUND_UP(period_cycles, PWM_MAX_CYCLES); in pwm_kb1200_set_cycles()
54 cycle_len = (period_cycles / prescaler); in pwm_kb1200_set_cycles()
Dpwm_rpi_pico.c102 static int pwm_rpi_set_cycles(const struct device *dev, uint32_t ch, uint32_t period_cycles, in pwm_rpi_set_cycles() argument
123 while ((period_cycles / div_int - 1) > PWM_RPI_PICO_COUNTER_TOP_MAX) { in pwm_rpi_set_cycles()
131 period_cycles /= div_int; in pwm_rpi_set_cycles()
135 if (period_cycles - 1 > PWM_RPI_PICO_COUNTER_TOP_MAX || in pwm_rpi_set_cycles()
142 pwm_set_wrap(slice, period_cycles - 1); in pwm_rpi_set_cycles()
Dpwm_b91.c59 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_b91_set_cycles() argument
70 if ((period_cycles > 0xFFFFu) || in pwm_b91_set_cycles()
84 pwm_set_tmax(channel, period_cycles); in pwm_b91_set_cycles()
Dpwm_intel_blinky.c37 uint32_t period_cycles, uint32_t pulse_cycles, in bk_intel_set_cycles() argument
54 out_freq = cfg->clock_freq / (float) period_cycles; in bk_intel_set_cycles()
57 duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles; in bk_intel_set_cycles()
/Zephyr-latest/include/zephyr/drivers/
Dpwm.h393 uint32_t period_cycles,
403 uint32_t period_cycles, uint32_t pulse_cycles,
542 uint64_t period_cycles; in pwm_set() local
550 period_cycles = (period * cycles_per_sec) / NSEC_PER_SEC; in pwm_set()
551 if (period_cycles > UINT32_MAX) { in pwm_set()
560 return pwm_set_cycles(dev, channel, (uint32_t)period_cycles, in pwm_set()
854 uint32_t period_cycles; in pwm_capture_usec() local
856 err = pwm_capture_cycles(dev, channel, flags, &period_cycles, in pwm_capture_usec()
862 err = pwm_cycles_to_usec(dev, channel, period_cycles, period); in pwm_capture_usec()
909 uint32_t period_cycles; in pwm_capture_nsec() local
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/Zephyr-latest/drivers/clock_control/
Dclock_control_pwm.c54 uint32_t period_cycles; in clock_control_pwm_on() local
65 period_cycles = cycles_per_sec / data->clock_frequency; in clock_control_pwm_on()
66 ret = pwm_set_cycles(spec->dev, spec->channel, period_cycles, period_cycles / 2, in clock_control_pwm_on()

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