1 /*
2 * Copyright (c) 2018, Cue Health Inc
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <nrfx_pwm.h>
7 #include <zephyr/drivers/pwm.h>
8 #include <zephyr/pm/device.h>
9 #include <zephyr/drivers/pinctrl.h>
10 #include <soc.h>
11 #include <hal/nrf_gpio.h>
12 #include <stdbool.h>
13 #include <zephyr/linker/devicetree_regions.h>
14 #include <zephyr/cache.h>
15 #include <zephyr/mem_mgmt/mem_attr.h>
16 #ifdef CONFIG_SOC_NRF54H20_GPD
17 #include <nrf/gpd.h>
18 #endif
19
20 #include <zephyr/logging/log.h>
21
22 LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
23
24 /* NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED can be undefined or defined
25 * to 0 or 1, hence the use of #if IS_ENABLED().
26 */
27 #if IS_ENABLED(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
28 #define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
29 #define _EGU_IRQ_CONNECT(idx) \
30 extern void nrfx_egu_##idx##_irq_handler(void); \
31 IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
32 DT_IRQ(DT_NODELABEL(egu##idx), priority), \
33 nrfx_isr, nrfx_egu_##idx##_irq_handler, 0)
34 #else
35 #define ANOMALY_109_EGU_IRQ_CONNECT(idx)
36 #endif
37
38 #define PWM_NRFX_CH_POLARITY_MASK BIT(15)
39 #define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
40 #define PWM_NRFX_CH_VALUE(compare_value, inverted) \
41 (compare_value | (inverted ? 0 : PWM_NRFX_CH_POLARITY_MASK))
42
43 struct pwm_nrfx_config {
44 nrfx_pwm_t pwm;
45 nrfx_pwm_config_t initial_config;
46 nrf_pwm_sequence_t seq;
47 const struct pinctrl_dev_config *pcfg;
48 uint32_t clock_freq;
49 #ifdef CONFIG_DCACHE
50 uint32_t mem_attr;
51 #endif
52 };
53
54 struct pwm_nrfx_data {
55 uint32_t period_cycles;
56 /* Bit mask indicating channels that need the PWM generation. */
57 uint8_t pwm_needed;
58 uint8_t prescaler;
59 bool stop_requested;
60 };
61 /* Ensure the pwm_needed bit mask can accommodate all available channels. */
62 #if (NRF_PWM_CHANNEL_COUNT > 8)
63 #error "Current implementation supports maximum 8 channels."
64 #endif
65
seq_values_ptr_get(const struct device * dev)66 static uint16_t *seq_values_ptr_get(const struct device *dev)
67 {
68 const struct pwm_nrfx_config *config = dev->config;
69
70 return (uint16_t *)config->seq.values.p_raw;
71 }
72
pwm_handler(nrfx_pwm_evt_type_t event_type,void * p_context)73 static void pwm_handler(nrfx_pwm_evt_type_t event_type, void *p_context)
74 {
75 ARG_UNUSED(event_type);
76 ARG_UNUSED(p_context);
77 }
78
pwm_period_check_and_set(const struct device * dev,uint32_t channel,uint32_t period_cycles)79 static bool pwm_period_check_and_set(const struct device *dev,
80 uint32_t channel, uint32_t period_cycles)
81 {
82 const struct pwm_nrfx_config *config = dev->config;
83 struct pwm_nrfx_data *data = dev->data;
84 uint8_t prescaler;
85 uint32_t countertop;
86
87 /* If the currently configured period matches the requested one,
88 * nothing more needs to be done.
89 */
90 if (period_cycles == data->period_cycles) {
91 return true;
92 }
93
94 /* If any other channel is driven by the PWM peripheral, the period
95 * that is currently set cannot be changed, as this would influence
96 * the output for that channel.
97 */
98 if ((data->pwm_needed & ~BIT(channel)) != 0) {
99 LOG_ERR("Incompatible period.");
100 return false;
101 }
102
103 /* Try to find a prescaler that will allow setting the requested period
104 * after prescaling as the countertop value for the PWM peripheral.
105 */
106 prescaler = 0;
107 countertop = period_cycles;
108 do {
109 if (countertop <= PWM_COUNTERTOP_COUNTERTOP_Msk) {
110 data->period_cycles = period_cycles;
111 data->prescaler = prescaler;
112
113 nrf_pwm_configure(config->pwm.p_reg,
114 data->prescaler,
115 config->initial_config.count_mode,
116 (uint16_t)countertop);
117 return true;
118 }
119
120 countertop >>= 1;
121 ++prescaler;
122 } while (prescaler <= PWM_PRESCALER_PRESCALER_Msk);
123
124 LOG_ERR("Prescaler for period_cycles %u not found.", period_cycles);
125 return false;
126 }
127
channel_psel_get(uint32_t channel,uint32_t * psel,const struct pwm_nrfx_config * config)128 static bool channel_psel_get(uint32_t channel, uint32_t *psel,
129 const struct pwm_nrfx_config *config)
130 {
131 *psel = nrf_pwm_pin_get(config->pwm.p_reg, (uint8_t)channel);
132
133 return (((*psel & PWM_PSEL_OUT_CONNECT_Msk) >> PWM_PSEL_OUT_CONNECT_Pos)
134 == PWM_PSEL_OUT_CONNECT_Connected);
135 }
136
pwm_nrfx_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)137 static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
138 uint32_t period_cycles, uint32_t pulse_cycles,
139 pwm_flags_t flags)
140 {
141 /* We assume here that period_cycles will always be 16MHz
142 * peripheral clock. Since pwm_nrfx_get_cycles_per_sec() function might
143 * be removed, see ISSUE #6958.
144 * TODO: Remove this comment when issue has been resolved.
145 */
146 const struct pwm_nrfx_config *config = dev->config;
147 struct pwm_nrfx_data *data = dev->data;
148 uint16_t compare_value;
149 bool inverted = (flags & PWM_POLARITY_INVERTED);
150 bool needs_pwm = false;
151
152 if (channel >= NRF_PWM_CHANNEL_COUNT) {
153 LOG_ERR("Invalid channel: %u.", channel);
154 return -EINVAL;
155 }
156
157 /* If this PWM is in center-aligned mode, pulse and period lengths
158 * are effectively doubled by the up-down count, so halve them here
159 * to compensate.
160 */
161 if (config->initial_config.count_mode == NRF_PWM_MODE_UP_AND_DOWN) {
162 period_cycles /= 2;
163 pulse_cycles /= 2;
164 }
165
166 if (pulse_cycles == 0) {
167 /* Constantly inactive (duty 0%). */
168 compare_value = 0;
169 } else if (pulse_cycles >= period_cycles) {
170 /* Constantly active (duty 100%). */
171 /* This value is always greater than or equal to COUNTERTOP. */
172 compare_value = PWM_NRFX_CH_COMPARE_MASK;
173 } else {
174 /* PWM generation needed. Check if the requested period matches
175 * the one that is currently set, or the PWM peripheral can be
176 * reconfigured accordingly.
177 */
178 if (!pwm_period_check_and_set(dev, channel, period_cycles)) {
179 return -EINVAL;
180 }
181
182 compare_value = (uint16_t)(pulse_cycles >> data->prescaler);
183 needs_pwm = true;
184 }
185
186 seq_values_ptr_get(dev)[channel] = PWM_NRFX_CH_VALUE(compare_value, inverted);
187
188 #ifdef CONFIG_DCACHE
189 if (config->mem_attr & DT_MEM_CACHEABLE) {
190 sys_cache_data_flush_range(seq_values_ptr_get(dev), config->seq.length);
191 }
192 #endif
193
194 LOG_DBG("channel %u, pulse %u, period %u, prescaler: %u.",
195 channel, pulse_cycles, period_cycles, data->prescaler);
196
197 /* If this channel does not need to be driven by the PWM peripheral
198 * because its state is to be constant (duty 0% or 100%), set properly
199 * the GPIO configuration for its output pin. This will provide
200 * the correct output state for this channel when the PWM peripheral
201 * is stopped.
202 */
203 if (!needs_pwm) {
204 uint32_t psel;
205
206 if (channel_psel_get(channel, &psel, config)) {
207 uint32_t out_level = (pulse_cycles == 0) ? 0 : 1;
208
209 if (inverted) {
210 out_level ^= 1;
211 }
212
213 nrf_gpio_pin_write(psel, out_level);
214 }
215
216 data->pwm_needed &= ~BIT(channel);
217 } else {
218 data->pwm_needed |= BIT(channel);
219 }
220
221 /* If the PWM generation is not needed for any channel (all are set
222 * to constant inactive or active state), stop the PWM peripheral.
223 * Otherwise, request a playback of the defined sequence so that
224 * the PWM peripheral loads `seq_values` into its internal compare
225 * registers and drives its outputs accordingly.
226 */
227 if (data->pwm_needed == 0) {
228 /* Don't wait here for the peripheral to actually stop. Instead,
229 * ensure it is stopped before starting the next playback.
230 */
231 nrfx_pwm_stop(&config->pwm, false);
232 data->stop_requested = true;
233 } else {
234 if (data->stop_requested) {
235 data->stop_requested = false;
236
237 /* After a stop is requested, the PWM peripheral stops
238 * pulse generation at the end of the current period,
239 * and till that moment, it ignores any start requests,
240 * so ensure here that it is stopped.
241 */
242 while (!nrfx_pwm_stopped_check(&config->pwm)) {
243 }
244 }
245
246 /* It is sufficient to play the sequence once without looping.
247 * The PWM generation will continue with the loaded values
248 * until another playback is requested (new values will be
249 * loaded then) or the PWM peripheral is stopped.
250 */
251 nrfx_pwm_simple_playback(&config->pwm, &config->seq, 1,
252 NRFX_PWM_FLAG_NO_EVT_FINISHED);
253 }
254
255 return 0;
256 }
257
pwm_nrfx_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)258 static int pwm_nrfx_get_cycles_per_sec(const struct device *dev, uint32_t channel,
259 uint64_t *cycles)
260 {
261 const struct pwm_nrfx_config *config = dev->config;
262
263 *cycles = config->clock_freq;
264
265 return 0;
266 }
267
268 static DEVICE_API(pwm, pwm_nrfx_drv_api_funcs) = {
269 .set_cycles = pwm_nrfx_set_cycles,
270 .get_cycles_per_sec = pwm_nrfx_get_cycles_per_sec,
271 };
272
pwm_resume(const struct device * dev)273 static void pwm_resume(const struct device *dev)
274 {
275 const struct pwm_nrfx_config *config = dev->config;
276 uint8_t initially_inverted = 0;
277
278 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
279
280 #ifdef CONFIG_SOC_NRF54H20_GPD
281 nrf_gpd_retain_pins_set(config->pcfg, false);
282 #endif
283
284 for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) {
285 uint32_t psel;
286
287 if (channel_psel_get(i, &psel, config)) {
288 /* Mark channels as inverted according to what initial
289 * state of their outputs has been set by pinctrl (high
290 * idle state means that the channel is inverted).
291 */
292 initially_inverted |= nrf_gpio_pin_out_read(psel) ?
293 BIT(i) : 0;
294 }
295 }
296
297 for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) {
298 bool inverted = initially_inverted & BIT(i);
299
300 seq_values_ptr_get(dev)[i] = PWM_NRFX_CH_VALUE(0, inverted);
301 }
302 }
303
pwm_suspend(const struct device * dev)304 static void pwm_suspend(const struct device *dev)
305 {
306 const struct pwm_nrfx_config *config = dev->config;
307
308 nrfx_pwm_stop(&config->pwm, false);
309 while (!nrfx_pwm_stopped_check(&config->pwm)) {
310 }
311
312 #ifdef CONFIG_SOC_NRF54H20_GPD
313 nrf_gpd_retain_pins_set(config->pcfg, true);
314 #endif
315
316 memset(dev->data, 0, sizeof(struct pwm_nrfx_data));
317 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
318 }
319
pwm_nrfx_pm_action(const struct device * dev,enum pm_device_action action)320 static int pwm_nrfx_pm_action(const struct device *dev,
321 enum pm_device_action action)
322 {
323 if (action == PM_DEVICE_ACTION_RESUME) {
324 pwm_resume(dev);
325 } else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) {
326 pwm_suspend(dev);
327 } else {
328 return -ENOTSUP;
329 }
330
331 return 0;
332 }
333
pwm_nrfx_init(const struct device * dev)334 static int pwm_nrfx_init(const struct device *dev)
335 {
336 const struct pwm_nrfx_config *config = dev->config;
337 nrfx_err_t err;
338
339 ANOMALY_109_EGU_IRQ_CONNECT(NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE);
340
341 if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)) {
342 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
343 }
344
345 err = nrfx_pwm_init(&config->pwm, &config->initial_config, pwm_handler, dev->data);
346 if (err != NRFX_SUCCESS) {
347 LOG_ERR("Failed to initialize device: %s", dev->name);
348 return -EBUSY;
349 }
350
351 return pm_device_driver_init(dev, pwm_nrfx_pm_action);
352 }
353
354 #define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
355 #define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
356 #define PWM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(PWM(idx), prop)
357 #define PWM_MEM_REGION(idx) DT_PHANDLE(PWM(idx), memory_regions)
358
359 #define PWM_MEMORY_SECTION(idx) \
360 COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
361 (__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
362 PWM_MEM_REGION(idx)))))), \
363 ())
364
365 #define PWM_GET_MEM_ATTR(idx) \
366 COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
367 (DT_PROP_OR(PWM_MEM_REGION(idx), zephyr_memory_attr, 0)), (0))
368
369 #define PWM_NRFX_DEVICE(idx) \
370 NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(PWM(idx)); \
371 static struct pwm_nrfx_data pwm_nrfx_##idx##_data; \
372 static uint16_t pwm_##idx##_seq_values[NRF_PWM_CHANNEL_COUNT] \
373 PWM_MEMORY_SECTION(idx); \
374 PINCTRL_DT_DEFINE(PWM(idx)); \
375 static const struct pwm_nrfx_config pwm_nrfx_##idx##_config = { \
376 .pwm = NRFX_PWM_INSTANCE(idx), \
377 .initial_config = { \
378 .skip_gpio_cfg = true, \
379 .skip_psel_cfg = true, \
380 .base_clock = NRF_PWM_CLK_1MHz, \
381 .count_mode = (PWM_PROP(idx, center_aligned) \
382 ? NRF_PWM_MODE_UP_AND_DOWN \
383 : NRF_PWM_MODE_UP), \
384 .top_value = 1000, \
385 .load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
386 .step_mode = NRF_PWM_STEP_TRIGGERED, \
387 }, \
388 .seq.values.p_raw = pwm_##idx##_seq_values, \
389 .seq.length = NRF_PWM_CHANNEL_COUNT, \
390 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(PWM(idx)), \
391 .clock_freq = COND_CODE_1(DT_CLOCKS_HAS_IDX(PWM(idx), 0), \
392 (DT_PROP(DT_CLOCKS_CTLR(PWM(idx)), clock_frequency)), \
393 (16ul * 1000ul * 1000ul)), \
394 IF_ENABLED(CONFIG_DCACHE, \
395 (.mem_attr = PWM_GET_MEM_ATTR(idx),)) \
396 }; \
397 static int pwm_nrfx_init##idx(const struct device *dev) \
398 { \
399 IRQ_CONNECT(DT_IRQN(PWM(idx)), DT_IRQ(PWM(idx), priority), \
400 nrfx_isr, nrfx_pwm_##idx##_irq_handler, 0); \
401 return pwm_nrfx_init(dev); \
402 }; \
403 PM_DEVICE_DT_DEFINE(PWM(idx), pwm_nrfx_pm_action); \
404 DEVICE_DT_DEFINE(PWM(idx), \
405 pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
406 &pwm_nrfx_##idx##_data, \
407 &pwm_nrfx_##idx##_config, \
408 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
409 &pwm_nrfx_drv_api_funcs)
410
411 #define COND_PWM_NRFX_DEVICE(unused, prefix, i, _) \
412 IF_ENABLED(CONFIG_HAS_HW_NRF_PWM##prefix##i, (PWM_NRFX_DEVICE(prefix##i);))
413
414 NRFX_FOREACH_PRESENT(PWM, COND_PWM_NRFX_DEVICE, (), (), _)
415
