Searched refs:instruction (Results 1 – 25 of 129) sorted by relevance
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30 Standard integer multiplication and division instruction extension,39 The standard atomic instruction extension is denoted by instruction49 Standard instruction-set extension for single-precision60 Standard double-precision floating-point instruction-set extension,86 quad-precision binary floatingpoint instruction subset is named "Q".93 RISC-V standard compressed instruction set extension, named "C",95 instruction encodings for common operations.110 The "Zifencei" extension includes the FENCE.I instruction that111 provides explicit synchronization between writes to instruction112 memory and instruction fetches on the same hart.
44 Faulting instruction address: 0x88c53 Faulting instruction address: 0xd6062 Faulting instruction address: 0x2000041c71 Faulting instruction address: 0x2000092880 Faulting instruction address: 0x20000454
168 uint8_t instruction)170 return z_cc2520_access(dev, false, instruction, 0, NULL, 0);174 uint8_t instruction) in cc2520_command_strobe_snop() argument178 return z_cc2520_access(dev, false, instruction, 0, snop, 1); in cc2520_command_strobe_snop()
64 E: Faulting instruction address (r15/pc): 0x00000f3478 E: Faulting instruction address (r15/pc): 0x000009a687 E: Faulting instruction address (r15/pc): 0x000009c499 E: Faulting instruction address (r15/pc): 0x0000cab0111 E: Faulting instruction address (r15/pc): 0x0000cab0122 E: Faulting instruction address (r15/pc): 0xf9cfef45131 E: Attempt to execute undefined instruction135 E: Faulting instruction address (r15/pc): 0x0000bec0
36 bool "8KB instruction cache size"39 bool "16KB instruction cache size"
58 <err> os: Faulting instruction address (r15/pc): 0x000003c874 <err> os: Faulting instruction address (r15/pc): 0x000003b288 <err> os: Faulting instruction address (r15/pc): 0x20000000116 <err> os: Faulting instruction address (r15/pc): 0x08000486129 <err> os: Faulting instruction address (r15/pc): 0x0800046a
76 From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php78 Thumb-2 technology is the instruction set underlying the ARM Cortex84 high code density instruction set for ARM microprocessor cores, to103 …From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets119 This helper symbol specifies the default target instruction set for123 assembler must use the Thumb-2 instruction set.126 and Cortex-R cores), the assembler must use the ARM instruction set131 bool "Compile C/C++ functions using Thumb-2 instruction set"136 using the Thumb-2 instruction set.144 instruction set for that language.
24 If you use 16KB instruction cache rather than 32KB instruction cache,74 bool "Define instruction cache wrap mode"76 If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
41 E: Faulting instruction address (r15/pc): 0x0000079e54 E: Faulting instruction address (r15/pc): 0x00005d1e
17 Faulting instruction address: 0x00000000
20 There is a ROTW instruction that can be used to manually rotate the33 There is an ENTRY instruction that does the rotation. It adds CALLINC38 There is a RETW instruction that undoes the rotation. It reads the53 will be set by the ENTRY instruction, and remain set after rotations70 so it's actually possible to trap again when the instruction restarts
20 Like the L1 cache, the TLB is split into separate instruction and data22 architecture technically supports separately-virtualized instruction80 one each for instruction/data TLBs, but in Zephyr they operate95 After the TLB refill exception, the original faulting instruction is124 requires doing a fetch via the instruction TLB. And that obviously130 provide 4k "pinnable" ways in the instruction TLB (frankly this seems137 the data TLB, such that instruction fetches always find their TLB188 6. Disable the initial/way6 instruction TLBs second. The very next189 instruction following the invalidation of the currently-executing
53 entering sleep by skipping the WFE/WFI instruction.
24 * It will generate instruction sequence of 'mov'/ 'movz' and one
35 instruction and data abort exception handlers.155 and Thumb (T32) instruction sets.177 Unit (MPU). It supports the A32 and T32 instruction sets.184 instruction and data abort exception handlers.
42 # instruction so we bump the kernel default values.
10 ESP32 features memory hardware which allows regions of flash memory to be mapped into instruction15 and the instruction address space. See the technical reference manual for more details and
104 Refer to the instruction in the :ref:`nordic_segger` page to install and116 Refer to the instruction in the :ref:`nordic_segger` page for information on
67 byte internal instruction memory (IMEM) for code execution. The size of the68 instruction memory can be overridden by changing the ``reg`` property of the127 If the bootloader is not enabled, the internal instruction memory (IMEM) is162 internal instruction memory of the NEORV32.
15 instruction cache. The cache controller can be in the core or can be an23 options must be selected when support for data or instruction cache is
107 bool "Use BREAK instruction on unrecoverable exceptions"109 Use BREAK instruction when unrecoverable exceptions are138 This option enables HiFi 3 instruction support.146 This option enables HiFi 4 instruction support.
57 * Useful when the mul instruction isn't available.
185 bool "X86 MFENCE instruction supported"189 Set n to disable the use of MFENCE instruction in arch_dcache_flush()190 for X86 CPUs have CLFLUSH instruction but no MFENCE
71 Enable QEMU virtual instruction counter. The virtual cpu will72 execute one instruction every 2^N ns of virtual time. This will79 The virtual CPU will execute one instruction every 2^N nanoseconds
27 /* tightly coupled instruction RAM */
