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Searched refs:enr (Results 1 – 25 of 38) sorted by relevance

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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_mp1.c26 LL_APB1_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
29 LL_APB2_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
32 LL_APB3_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
35 LL_APB4_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
38 LL_APB5_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
41 LL_AHB2_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
44 LL_AHB3_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
47 LL_AHB4_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
50 LL_AHB5_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
53 LL_AHB6_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
[all …]
Dclock_stm32_mco.c44 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_mco_init()
45 STM32_DT_CLKSEL_MASK_GET(pclken->enr) << in stm32_mco_init()
46 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_mco_init()
48 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_mco_init()
49 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_mco_init()
50 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_mco_init()
Dclock_stm32_ll_wb0.c222 sys_set_bits(reg, pclken->enr); in stm32_clock_control_on()
245 sys_clear_bits(reg, pclken->enr); in stm32_clock_control_off()
255 const uint32_t shift = STM32_DT_CLKSEL_SHIFT_GET(pclken->enr); in stm32_clock_control_configure()
256 mem_addr_t reg = RCC_REG(STM32_DT_CLKSEL_REG_GET(pclken->enr)); in stm32_clock_control_configure()
268 sys_clear_bits(reg, STM32_DT_CLKSEL_MASK_GET(pclken->enr) << shift); in stm32_clock_control_configure()
269 sys_set_bits(reg, STM32_DT_CLKSEL_VAL_GET(pclken->enr) << shift); in stm32_clock_control_configure()
277 switch (pclken->enr) { in get_apb0_periph_clkrate()
318 switch (pclken->enr) { in get_apb1_periph_clkrate()
520 if ((sys_read32(RCC_REG(pclken->bus)) & pclken->enr) == pclken->enr) { in stm32_clock_control_get_status()
Dclock_stm32_ll_wba.c79 pclken->enr); in stm32_clock_control_on()
100 pclken->enr); in stm32_clock_control_off()
123 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
124 STM32_DT_CLKSEL_MASK_GET(pclken->enr) << in stm32_clock_control_configure()
125 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
126 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
127 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_clock_control_configure()
128 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
292 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) in stm32_clock_control_get_status()
293 == pclken->enr) { in stm32_clock_control_get_status()
Dclock_stm32_ll_common.c264 pclken->enr); in stm32_clock_control_on()
287 pclken->enr); in stm32_clock_control_off()
309 if (pclken->enr == NO_SEL) { in stm32_clock_control_configure()
314 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
315 STM32_DT_CLKSEL_MASK_GET(pclken->enr) << in stm32_clock_control_configure()
316 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
317 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
318 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_clock_control_configure()
319 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
503 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) in stm32_clock_control_get_status()
[all …]
Dclock_stm32_ll_u5.c167 pclken->enr); in stm32_clock_control_on()
188 pclken->enr); in stm32_clock_control_off()
209 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
210 STM32_DT_CLKSEL_MASK_GET(pclken->enr) << in stm32_clock_control_configure()
211 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
212 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
213 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_clock_control_configure()
214 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
378 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) in stm32_clock_control_get_status()
379 == pclken->enr) { in stm32_clock_control_get_status()
Dclock_stm32_ll_n6.c208 pclken->enr); in stm32_clock_control_on()
212 pclken->enr); in stm32_clock_control_on()
231 pclken->enr); in stm32_clock_control_off()
235 pclken->enr); in stm32_clock_control_off()
256 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
257 STM32_DT_CLKSEL_MASK_GET(pclken->enr) << in stm32_clock_control_configure()
258 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
259 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
260 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_clock_control_configure()
261 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
Dclock_stm32_ll_h7.c400 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
426 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
451 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
452 STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
453 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
454 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
455 STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
456 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
Dclock_stm32_ll_h5.c161 pclken->enr); in stm32_clock_control_on()
182 pclken->enr); in stm32_clock_control_off()
203 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
204 STM32_DT_CLKSEL_VAL_GET(pclken->enr) << in stm32_clock_control_configure()
205 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_stm32h7x.c37 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
41 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits),
45 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits),
Deth_stm32_hal.c1528 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits)},
1530 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits)},
1532 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits)},
1535 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bits)},
/Zephyr-latest/soc/st/stm32/common/
Dstm32_backup_sram.c58 .enr = DT_INST_CLOCKS_CELL(0, bits) },
/Zephyr-latest/drivers/interrupt_controller/
Dintc_exti_stm32.c177 .enr = LL_APB4_GRP1_PERIPH_SYSCFG in stm32_exti_enable_registers()
180 .enr = LL_APB4_GRP1_PERIPH_SBS in stm32_exti_enable_registers()
183 .enr = LL_APB2_GRP1_PERIPH_SYSCFG in stm32_exti_enable_registers()
/Zephyr-latest/drivers/timer/
Dstm32_lptim_timer.c40 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
42 {.bus = STM32_SRC_LSE, .enr = LPTIM1_SEL(3)}
/Zephyr-latest/drivers/sensor/st/qdec_stm32/
Dqdec_stm32.c153 .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits)}, \
/Zephyr-latest/drivers/ipm/
Dipm_stm32_hsem.c199 .enr = DT_INST_CLOCKS_CELL(0, bits)
Dipm_stm32_ipcc.c294 .enr = DT_INST_CLOCKS_CELL(0, bits)
/Zephyr-latest/drivers/dac/
Ddac_stm32.c183 .enr = DT_INST_CLOCKS_CELL(index, bits), \
/Zephyr-latest/drivers/mbox/
Dmbox_stm32_hsem.c53 .enr = DT_INST_CLOCKS_CELL(0, bits)
/Zephyr-latest/drivers/mipi_dsi/
Ddsi_stm32.c457 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, dsiclk, bits), \
461 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, refclk, bits), \
465 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, pixelclk, bits), \
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdg_stm32.c308 .enr = DT_INST_CLOCKS_CELL(0, bits),
/Zephyr-latest/drivers/sensor/st/stm32_digi_temp/
Dstm32_digi_temp.c279 .enr = DT_INST_CLOCKS_CELL(index, bits), \
/Zephyr-latest/drivers/dma/
Ddmamux_stm32.c371 .enr = DT_INST_CLOCKS_CELL(index, bits)},), \
/Zephyr-latest/drivers/flash/
Dflash_stm32.c441 .enr = DT_INST_CLOCKS_CELL(0, bits),
/Zephyr-latest/drivers/video/
Dvideo_stm32_dcmi.c463 .enr = DT_INST_CLOCKS_CELL(0, bits),

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