| /Zephyr-latest/drivers/spi/ |
| D | spi_andes_atcspi200.c | 45 struct stream dma_tx; member
234 data->dma_tx.dma_blk_cfg.next_block = NULL; in spi_dma_move_buffers()
282 dma_stop(data->dma_tx.dma_dev, data->dma_tx.channel); in dma_tx_callback()
290 error = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in dma_tx_callback()
309 memset(&data->dma_tx.dma_blk_cfg, 0, sizeof(struct dma_block_config)); in spi_dma_tx_load()
312 data->dma_tx.dma_blk_cfg.block_size = data->chunk_len / in spi_dma_tx_load()
313 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
315 data->dma_tx.dma_blk_cfg.block_size = ctx->current_tx->len / in spi_dma_tx_load()
316 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
323 data->dma_tx.dma_blk_cfg.source_address = (uintptr_t)&dummy_rx_tx_buffer; in spi_dma_tx_load()
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| D | spi_xmc4xxx.c | 62 struct spi_xmc4xxx_dma_stream dma_tx; member
81 if (dev_dma == data->dma_tx.dev_dma && dma_channel == data->dma_tx.dma_channel) { in spi_xmc4xxx_dma_callback()
355 struct spi_xmc4xxx_dma_stream *dma_tx = &data->dma_tx; in spi_xmc4xxx_transceive_dma() local
430 dma_tx->blk_cfg.source_address = (uint32_t)ctx->tx_buf; in spi_xmc4xxx_transceive_dma()
431 dma_tx->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_xmc4xxx_transceive_dma()
433 dma_tx->blk_cfg.source_address = (uint32_t)&tx_dummy_data; in spi_xmc4xxx_transceive_dma()
434 dma_tx->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_xmc4xxx_transceive_dma()
437 dma_tx->blk_cfg.block_size = dma_len; in spi_xmc4xxx_transceive_dma()
439 ret = dma_config(dma_tx->dev_dma, dma_tx->dma_channel, &dma_tx->dma_cfg); in spi_xmc4xxx_transceive_dma()
450 ret = dma_start(dma_tx->dev_dma, dma_tx->dma_channel); in spi_xmc4xxx_transceive_dma()
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| D | spi_mcux_flexcomm.c | 69 struct stream dma_tx; member
314 if (channel == data->dma_tx.channel) { in spi_mcux_dma_callback()
315 if (status != data->dma_tx.wait_for_dma_status) { in spi_mcux_dma_callback()
398 struct stream *stream = &data->dma_tx; in spi_mcux_dma_tx_load()
431 data->dma_tx.wait_for_dma_status = DMA_STATUS_COMPLETE; in spi_mcux_dma_tx_load()
438 data->dma_tx.wait_for_dma_status = DMA_STATUS_BLOCK; in spi_mcux_dma_tx_load()
464 data->dma_tx.wait_for_dma_status = DMA_STATUS_COMPLETE; in spi_mcux_dma_tx_load()
469 data->dma_tx.wait_for_dma_status = DMA_STATUS_BLOCK; in spi_mcux_dma_tx_load()
481 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.channel, in spi_mcux_dma_tx_load()
508 return dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in spi_mcux_dma_tx_load()
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| D | spi_ll_stm32.c | 141 if (channel == spi_dma_data->dma_tx.channel) { in dma_callback()
165 struct stream *stream = &data->dma_tx; in spi_stm32_dma_tx_load()
184 if (data->dma_tx.src_addr_increment) { in spi_stm32_dma_tx_load()
193 if (data->dma_tx.dst_addr_increment) { in spi_stm32_dma_tx_load()
200 blk_cfg->fifo_mode_control = data->dma_tx.fifo_threshold; in spi_stm32_dma_tx_load()
207 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.channel, in spi_stm32_dma_tx_load()
215 return dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in spi_stm32_dma_tx_load()
290 dma_segment_len = len * data->dma_tx.dma_cfg.source_data_size; in spi_dma_move_buffers()
1100 err = dma_stop(data->dma_tx.dma_dev, data->dma_tx.channel); in transceive_dma()
1128 if ((data->dma_tx.dma_dev != NULL) in spi_stm32_transceive()
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| D | spi_mcux_lpspi.c | 87 struct spi_dma_stream dma_tx; member
230 return (data->dma_tx.dma_dev && data->dma_rx.dma_dev); in lpspi_inst_has_dma()
246 if (channel == data->dma_tx.channel) { in spi_mcux_dma_callback()
317 struct spi_dma_stream *stream = &data->dma_tx; in spi_mcux_dma_tx_load()
395 ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in spi_mcux_dma_rxtx_load()
752 return lpspi_dma_dev_ready(data->dma_tx.dma_dev) | in lpspi_dma_devs_ready()
809 (.dma_tx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
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| D | spi_ll_stm32.h | 69 struct stream dma_tx; member
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| /Zephyr-latest/drivers/serial/ |
| D | uart_xmc4xxx.c | 69 struct uart_dma_stream dma_tx; member
484 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_done()
485 .data.tx.len = data->dma_tx.counter}; in async_evt_tx_done()
487 data->dma_tx.buffer = NULL; in async_evt_tx_done()
488 data->dma_tx.buffer_len = 0; in async_evt_tx_done()
489 data->dma_tx.counter = 0; in async_evt_tx_done()
499 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_abort()
500 .data.tx.len = data->dma_tx.counter}; in async_evt_tx_abort()
502 data->dma_tx.buffer = NULL; in async_evt_tx_abort()
503 data->dma_tx.buffer_len = 0; in async_evt_tx_abort()
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| D | uart_stm32.c | 1146 LOG_DBG("tx done: %d", data->dma_tx.counter); in async_evt_tx_done()
1150 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_done()
1151 .data.tx.len = data->dma_tx.counter in async_evt_tx_done()
1155 data->dma_tx.buffer_length = 0; in async_evt_tx_done()
1156 data->dma_tx.counter = 0; in async_evt_tx_done()
1163 LOG_DBG("tx abort: %d", data->dma_tx.counter); in async_evt_tx_abort()
1167 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_abort()
1168 .data.tx.len = data->dma_tx.counter in async_evt_tx_abort()
1172 data->dma_tx.buffer_length = 0; in async_evt_tx_abort()
1173 data->dma_tx.counter = 0; in async_evt_tx_abort()
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| D | uart_stm32.h | 103 struct uart_dma_stream dma_tx; member
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 171 struct dma_stream *dma_tx; member
220 static struct dma_stream dma_tx = {SPI_DMA_CHANNEL_INIT(id, tx, TX, MEMORY, PERIPHERAL)}
227 .dma_tx = &dma_tx, \
311 if (channel == hc_spi->dma_tx->channel) { in dma_callback()
370 if ((hc_spi->dma_tx->dma_dev != NULL) && !device_is_ready(hc_spi->dma_tx->dma_dev)) { in spi_init()
371 LOG_ERR("%s device not ready", hc_spi->dma_tx->dma_dev->name); in spi_init()
424 ret = dma_reload(hc_spi->dma_tx->dma_dev, hc_spi->dma_tx->channel, (uint32_t)hc_spi->tx_buf, in reload_dma_tx()
431 ret = dma_start(hc_spi->dma_tx->dma_dev, hc_spi->dma_tx->channel); in reload_dma_tx()
447 struct dma_stream *stream = hc_spi->dma_tx; in spi_config_dma_tx()
463 blk_cfg->fifo_mode_control = hc_spi->dma_tx->fifo_threshold; in spi_config_dma_tx()
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| /Zephyr-latest/drivers/mipi_dbi/ |
| D | mipi_dbi_nxp_flexio_lcdif.c | 42 struct stream dma_tx; member
239 struct stream *stream = &lcdif_data->dma_tx; in mipi_dbi_flexio_ldcif_write_display()
277 dma_config(lcdif_data->dma_tx.dma_dev, lcdif_data->dma_tx.channel, &stream->dma_cfg); in mipi_dbi_flexio_ldcif_write_display()
283 EDMA_SetModulo(DMA0, lcdif_data->dma_tx.channel, kEDMA_ModuloDisable, in mipi_dbi_flexio_ldcif_write_display()
297 dma_start(lcdif_data->dma_tx.dma_dev, lcdif_data->dma_tx.channel); in mipi_dbi_flexio_ldcif_write_display()
379 if (!device_is_ready(lcdif_data->dma_tx.dma_dev)) { in flexio_lcdif_init()
380 LOG_ERR("%s device is not ready", lcdif_data->dma_tx.dma_dev->name); in flexio_lcdif_init()
464 .dma_tx = { \
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| /Zephyr-latest/drivers/disk/ |
| D | sdmmc_stm32.c | 91 struct sdmmc_dma_stream dma_tx; member
239 err = stm32_sdmmc_configure_dma(&priv->dma_tx_handle, &priv->dma_tx); in stm32_sdmmc_dma_init()
261 struct sdmmc_dma_stream *dma_tx = &priv->dma_tx; in stm32_sdmmc_dma_deinit() local
264 ret = dma_stop(dma_tx->dev, dma_tx->channel); in stm32_sdmmc_dma_deinit()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32_xspi.h | 108 struct stream dma_tx; member
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| D | flash_stm32_xspi.c | 2179 if (flash_stm32_xspi_dma_init(&hdma_tx, &dev_data->dma_tx) != 0) { in flash_stm32_xspi_init()
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_stm32.c | 141 struct i3c_stm32_dma_stream dma_tx; /* TX DMA channel config */ member
1143 dma_stream = &(data->dma_tx); in i3c_stm32_dma_msg_config()
1450 dev, &data->dma_tx, 0, in i3c_stm32_init_dma()
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