| /Zephyr-latest/drivers/timer/ |
| D | rv32m1_lptmr_timer.c | 76 uint32_t csr, psr, sircdiv; /* LPTMR registers */ in sys_clock_driver_init() local
91 csr = SYSTEM_TIMER_INSTANCE->CSR; in sys_clock_driver_init()
92 csr &= ~LPTMR_CSR_TEN(0); in sys_clock_driver_init()
93 csr |= LPTMR_CSR_TFC(1); in sys_clock_driver_init()
94 SYSTEM_TIMER_INSTANCE->CSR = csr; in sys_clock_driver_init()
113 csr &= ~(LPTMR_CSR_TMS(1) | LPTMR_CSR_TFC(1) | LPTMR_CSR_TDRE(1)); in sys_clock_driver_init()
117 csr |= LPTMR_CSR_TIE(1); in sys_clock_driver_init()
118 SYSTEM_TIMER_INSTANCE->CSR = csr; in sys_clock_driver_init()
145 csr = SYSTEM_TIMER_INSTANCE->CSR; in sys_clock_driver_init()
146 csr |= LPTMR_CSR_TEN(1); in sys_clock_driver_init()
[all …]
|
| /Zephyr-latest/drivers/regulator/ |
| D | regulator_nxp_vref.c | 37 volatile uint32_t *const csr = &base->CSR; in regulator_nxp_vref_enable() local
39 *csr |= VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK; in regulator_nxp_vref_enable()
44 *csr |= VREF_CSR_HCBGEN_MASK; in regulator_nxp_vref_enable()
47 while (!(*csr & VREF_CSR_VREFST_MASK)) { in regulator_nxp_vref_enable()
52 *csr |= VREF_CSR_BUF21EN_MASK; in regulator_nxp_vref_enable()
75 uint32_t csr = base->CSR; in regulator_nxp_vref_set_mode() local
78 csr &= ~VREF_CSR_REGEN_MASK & in regulator_nxp_vref_set_mode()
83 csr &= ~VREF_CSR_REGEN_MASK & in regulator_nxp_vref_set_mode()
86 csr |= VREF_CSR_BUF21EN_MASK; in regulator_nxp_vref_set_mode()
88 csr &= ~VREF_CSR_REGEN_MASK & in regulator_nxp_vref_set_mode()
[all …]
|
| /Zephyr-latest/include/zephyr/arch/riscv/ |
| D | csr.h | 185 #define csr_read(csr) \ argument
188 __asm__ volatile ("csrr %0, " STRINGIFY(csr) \
193 #define csr_write(csr, val) \ argument
196 __asm__ volatile ("csrw " STRINGIFY(csr) ", %0" \
202 #define csr_read_set(csr, val) \ argument
205 __asm__ volatile ("csrrs %0, " STRINGIFY(csr) ", %1" \
211 #define csr_set(csr, val) \ argument
214 __asm__ volatile ("csrs " STRINGIFY(csr) ", %0" \
219 #define csr_read_clear(csr, val) \ argument
222 __asm__ volatile ("csrrc %0, " STRINGIFY(csr) ", %1" \
[all …]
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_swerv_pic.c | 38 #define swerv_piccsr(csr) SWERV_PIC_##csr argument
40 #define swerv_pic_readcsr(csr, value) \ argument
41 volatile("csrr %0, "swerv_piccsr(csr) : "=r" (value))
42 #define swerv_pic_writecsr(csr, value) \ argument
43 volatile("csrw "swerv_piccsr(csr)", %0" :: "rK" (value))
|
| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/ |
| D | adsp_ipc_regs.h | 23 uint32_t csr; member
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_ipc_regs.h | 30 uint32_t csr; member
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_ipc_regs.h | 30 uint32_t csr; member
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/ |
| D | adsp_ipc_regs.h | 30 uint32_t csr; member
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_renesas_ra8_sci_b.c | 43 uint32_t csr; member
330 (data->csr & (BIT(R_SCI_B0_CSR_TDRE_Pos) | BIT(R_SCI_B0_CSR_TEND_Pos))); in uart_ra_sci_b_irq_tx_ready()
338 return (cfg->regs->CCR0_b.TEIE == 1U) && (data->csr & BIT(R_SCI_B0_CSR_TEND_Pos)); in uart_ra_sci_b_irq_tx_complete()
361 ((data->csr & BIT(R_SCI_B0_CSR_RDRF_Pos)) || in uart_ra_sci_b_irq_rx_ready()
384 const uint32_t csr = cfg->regs->CSR; in uart_ra_sci_b_irq_is_pending() local
387 (csr & (BIT(R_SCI_B0_CSR_TEND_Pos) | BIT(R_SCI_B0_CSR_TDRE_Pos)))); in uart_ra_sci_b_irq_is_pending()
390 ((csr & (BIT(R_SCI_B0_CSR_RDRF_Pos) | BIT(R_SCI_B0_CSR_PER_Pos) | in uart_ra_sci_b_irq_is_pending()
404 data->csr = cfg->regs->CSR; in uart_ra_sci_b_irq_update()
406 if (data->csr & BIT(R_SCI_B0_CSR_PER_Pos)) { in uart_ra_sci_b_irq_update()
409 if (data->csr & BIT(R_SCI_B0_CSR_FER_Pos)) { in uart_ra_sci_b_irq_update()
[all …]
|
| /Zephyr-latest/boards/intel/socfpga/agilex5_socdk/ |
| D | intel_socfpga_agilex5_socdk.dts | 55 csr-clock-indx = <4>;
|
| /Zephyr-latest/drivers/pwm/ |
| D | pwm_rpi_pico.c | 90 bool pwm_polarity_a = (cfg->pwm_controller->slice[slice].csr & PWM_CH0_CSR_A_INV_BITS) > 0; in pwm_rpi_set_channel_polarity()
91 bool pwm_polarity_b = (cfg->pwm_controller->slice[slice].csr & PWM_CH0_CSR_B_INV_BITS) > 0; in pwm_rpi_set_channel_polarity()
|
| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/ |
| D | index.rst | 142 … ./litex-boards/litex_boards/targets/digilent_arty.py --build --timer-uptime --csr-json csr.json
148 … ./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
|
| /Zephyr-latest/samples/subsys/mgmt/hawkbit/ |
| D | README.rst | 175 openssl req -new -key server.key -out server.csr
185 openssl x509 -req -days 365 -in server.csr -signkey server.key -out server.crt
|
