Home
last modified time | relevance | path

Searched refs:clk_src (Results 1 – 25 of 44) sorted by relevance

12

/Zephyr-latest/include/zephyr/drivers/clock_control/
Dadi_max32_clock_control.h36 uint32_t clk_src; member
99 #define ADI_MAX32_GET_PRPH_CLK_FREQ(clk_src) \ argument
100 ((clk_src) == ADI_MAX32_PRPH_CLK_SRC_PCLK ? ADI_MAX32_PCLK_FREQ \
101 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_IBRO ? ADI_MAX32_CLK_IBRO_FREQ \
102 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_ERFO ? ADI_MAX32_CLK_ERFO_FREQ \
103 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_ERTCO ? ADI_MAX32_CLK_ERTCO_FREQ \
104 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_INRO ? ADI_MAX32_CLK_INRO_FREQ \
105 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_ISO ? ADI_MAX32_CLK_ISO_FREQ \
106 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8 ? (ADI_MAX32_CLK_IBRO_FREQ / 8) \
107 : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_EXTCLK ? ADI_MAX32_CLK_EXTCLK_FREQ \
[all …]
Dclock_control_rts5912.h16 uint32_t clk_src; member
Dclock_control_numaker.h35 uint32_t clk_src; member
Desp32_clock_control.h29 int clk_src; member
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdt_numaker.c29 uint32_t clk_src; member
46 if (cfg->clk_src == CLK_CLKSEL1_WWDTSEL_LIRC) { in m_wwdt_numaker_clk_get_rate()
261 scc_subsys.pcc.clk_src = cfg->clk_src; in wwdt_numaker_init()
291 .clk_src = DT_INST_CLOCKS_CELL(0, clock_source),
Dwdt_max32.c127 wdt_max32_calculate_timeout(data->timeout.min, dev_cfg->perclk.clk_src); in wdt_max32_install_timeout()
152 wdt_max32_calculate_timeout(data->timeout.max, dev_cfg->perclk.clk_src); in wdt_max32_install_timeout()
227 ret = Wrap_MXC_WDT_SelectClockSource(regs, cfg->perclk.clk_src); in wdt_max32_init()
263 .perclk.clk_src = \
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.h24 void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
Dsoc.c312 void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, in imxrt_audio_codec_pll_init() argument
317 CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src); in imxrt_audio_codec_pll_init()
322 CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); in imxrt_audio_codec_pll_init()
327 CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); in imxrt_audio_codec_pll_init()
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.h24 void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
Dsoc.c597 void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, uint32_t clk_pre_div, in imxrt_audio_codec_pll_init() argument
604 CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, clk_src); in imxrt_audio_codec_pll_init()
608 CLOCK_SetRootClockMux(kCLOCK_Root_Sai2, clk_src); in imxrt_audio_codec_pll_init()
612 CLOCK_SetRootClockMux(kCLOCK_Root_Sai3, clk_src); in imxrt_audio_codec_pll_init()
616 CLOCK_SetRootClockMux(kCLOCK_Root_Sai4, clk_src); in imxrt_audio_codec_pll_init()
/Zephyr-latest/drivers/clock_control/
Dclock_control_renesas_ra_cgc.c74 clk_src_rate = R_BSP_SourceClockHzGet(config->clk_src); in clock_control_renesas_ra_get_rate()
107 {.clk_src = COND_CODE_1( \
Dclock_control_renesas_rz_cpg.c113 fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT; in clock_control_renesas_rz_get_rate() local
116 uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src); in clock_control_renesas_rz_get_rate()
Dclock_control_numaker_scc.c133 scc_subsys->pcc.clk_src, in numaker_scc_configure()
136 CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src, in numaker_scc_configure()
/Zephyr-latest/drivers/pwm/
Dpwm_numaker.c37 uint32_t clk_src; member
432 uint32_t clk_src; in pwm_numaker_clk_get_rate() local
436 clk_src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; in pwm_numaker_clk_get_rate()
438 clk_src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; in pwm_numaker_clk_get_rate()
444 if (clk_src == 0U) { in pwm_numaker_clk_get_rate()
482 scc_subsys.pcc.clk_src = cfg->clk_src; in pwm_numaker_init()
566 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
Dpwm_max32.c63 pwm_cfg.clock = Wrap_MXC_TMR_GetClockIndex(cfg->perclk.clk_src); in api_set_cycles()
135 .perclk.clk_src = DT_PROP(DT_INST_PARENT(_num), clock_source), \
/Zephyr-latest/drivers/can/
Dcan_numaker.c38 uint32_t clk_src; member
90 scc_subsys.pcc.clk_src = config->clk_src; in can_numaker_init_unlocked()
271 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
/Zephyr-latest/drivers/counter/
Dcounter_ambiq_timer.c24 uint32_t clk_src; member
69 (cfg->clk_src << CTIMER_CTRL0_TMRA0CLK_Pos)); in counter_ambiq_init()
82 tc.eInputClock = cfg->clk_src; in counter_ambiq_init()
299 .clk_src = DT_INST_PROP(idx, clk_source), \
/Zephyr-latest/drivers/rtc/
Drtc_ambiq.c29 uint8_t clk_src; member
364 am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_START + config->clk_src, NULL); in ambiq_rtc_init()
366 am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL + config->clk_src, NULL); in ambiq_rtc_init()
396 .clk_src = DT_INST_ENUM_IDX(inst, clock)}; \
/Zephyr-latest/drivers/spi/
Dspi_numaker.c31 uint32_t clk_src; member
305 scc_subsys.pcc.clk_src = dev_cfg->clk_src; in spi_numaker_init()
358 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
/Zephyr-latest/drivers/adc/
Dadc_numaker.c33 uint32_t clk_src; member
333 scc_subsys.pcc.clk_src = cfg->clk_src; in adc_numaker_init()
387 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
Dadc_esp32.c298 soc_module_clk_t clk_src = ADC_DIGI_CLK_SRC_DEFAULT; in adc_esp32_digi_start() local
301 esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, in adc_esp32_digi_start()
306 adc_hal_digi_ctrlr_cfg.clk_src = clk_src; in adc_esp32_digi_start()
677 .clk_src = ADC_DIGI_CLK_SRC_DEFAULT, in adc_esp32_init()
/Zephyr-latest/drivers/audio/
Ddmic_nrfx_pdm.c48 } clk_src; member
228 (NRF_PDM_HAS_MCLKCONFIG && drv_cfg->clk_src == ACLK) in check_pdm_frequencies()
465 nrfx_cfg.mclksrc = drv_cfg->clk_src == ACLK in dmic_nrfx_pdm_configure()
493 drv_data->request_clock = (drv_cfg->clk_src != PCLK32M); in dmic_nrfx_pdm_configure()
636 if (drv_cfg->clk_src == ACLK) { in init_clock_manager()
695 .clk_src = PDM_CLK_SRC(idx), \
/Zephyr-latest/drivers/serial/
Duart_numaker.c25 uint32_t clk_src; member
200 scc_subsys.pcc.clk_src = config->clk_src; in uart_numaker_init()
433 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
/Zephyr-latest/tests/boards/espressif/rtc_clk/src/
Drtc_clk_test.c55 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_XTAL; in ZTEST()
95 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_PLL; in ZTEST()
/Zephyr-latest/drivers/i2s/
Di2s_nrfx.c56 } clk_src; member
81 (NRF_I2S_HAS_CLKCONFIG && drv_cfg->clk_src == ACLK) in find_suitable_clock()
531 drv_data->request_clock = (drv_cfg->clk_src != PCLK32M); in i2s_nrfx_configure()
760 drv_cfg->clk_src == ACLK ? NRF_I2S_CLKSRC_ACLK in trigger_start()
905 if (drv_cfg->clk_src == ACLK) { in init_clock_manager()
949 .clk_src = I2S_CLK_SRC(idx), \

12