1 /*
2  * Copyright (c) 2023 Antmicro <www.antmicro.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT ambiq_counter
8 
9 #include <zephyr/drivers/counter.h>
10 #include <zephyr/spinlock.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <zephyr/logging/log.h>
14 /* ambiq-sdk includes */
15 #include <am_mcu_apollo.h>
16 
17 LOG_MODULE_REGISTER(ambiq_counter, CONFIG_COUNTER_LOG_LEVEL);
18 
19 static void counter_ambiq_isr(void *arg);
20 
21 struct counter_ambiq_config {
22 	struct counter_config_info counter_info;
23 	uint32_t instance;
24 	uint32_t clk_src;
25 	void (*irq_config_func)(void);
26 };
27 
28 struct counter_ambiq_data {
29 	counter_alarm_callback_t callback;
30 	void *user_data;
31 };
32 
33 static struct k_spinlock lock;
34 
35 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
counter_irq_config_func(void)36 static void counter_irq_config_func(void)
37 {
38 	/* Apollo3 counters share the same irq number, connect to counter0 once when init and handle
39 	 * different banks in counter_ambiq_isr
40 	 */
41 	static bool global_irq_init = true;
42 
43 	if (!global_irq_init) {
44 		return;
45 	}
46 
47 	global_irq_init = false;
48 
49 	/* Shared irq config default to ctimer0. */
50 	NVIC_ClearPendingIRQ(CTIMER_IRQn);
51 	IRQ_CONNECT(CTIMER_IRQn, DT_INST_IRQ(0, priority), counter_ambiq_isr, DEVICE_DT_INST_GET(0),
52 		    0);
53 	irq_enable(CTIMER_IRQn);
54 };
55 #endif
56 
counter_ambiq_init(const struct device * dev)57 static int counter_ambiq_init(const struct device *dev)
58 {
59 	k_spinlock_key_t key = k_spin_lock(&lock);
60 	const struct counter_ambiq_config *cfg = dev->config;
61 
62 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
63 	/* Timer configuration */
64 	am_hal_ctimer_config_t sContTimer;
65 	/* Create 32-bit timer */
66 	sContTimer.ui32Link = 1;
67 	/* Set up TimerA. */
68 	sContTimer.ui32TimerAConfig = (AM_HAL_CTIMER_FN_REPEAT | AM_HAL_CTIMER_INT_ENABLE |
69 				       (cfg->clk_src << CTIMER_CTRL0_TMRA0CLK_Pos));
70 	/* Set up TimerB. */
71 	sContTimer.ui32TimerBConfig = 0;
72 
73 	am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
74 
75 	am_hal_ctimer_clear(cfg->instance, AM_HAL_CTIMER_BOTH);
76 	am_hal_ctimer_config(cfg->instance, &sContTimer);
77 	counter_irq_config_func();
78 #else
79 	am_hal_timer_config_t tc;
80 
81 	am_hal_timer_default_config_set(&tc);
82 	tc.eInputClock = cfg->clk_src;
83 	tc.eFunction = AM_HAL_TIMER_FN_UPCOUNT;
84 	tc.ui32PatternLimit = 0;
85 
86 	am_hal_timer_config(cfg->instance, &tc);
87 	cfg->irq_config_func();
88 #endif
89 
90 	k_spin_unlock(&lock, key);
91 
92 	return 0;
93 }
94 
counter_ambiq_start(const struct device * dev)95 static int counter_ambiq_start(const struct device *dev)
96 {
97 	const struct counter_ambiq_config *cfg = dev->config;
98 	k_spinlock_key_t key = k_spin_lock(&lock);
99 
100 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
101 	am_hal_ctimer_start(cfg->instance, AM_HAL_CTIMER_TIMERA);
102 #else
103 	am_hal_timer_start(cfg->instance);
104 #endif
105 
106 	k_spin_unlock(&lock, key);
107 
108 	return 0;
109 }
110 
counter_ambiq_stop(const struct device * dev)111 static int counter_ambiq_stop(const struct device *dev)
112 {
113 	const struct counter_ambiq_config *cfg = dev->config;
114 
115 	k_spinlock_key_t key = k_spin_lock(&lock);
116 
117 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
118 	am_hal_ctimer_stop(cfg->instance, AM_HAL_CTIMER_BOTH);
119 #else
120 	am_hal_timer_stop(cfg->instance);
121 #endif
122 
123 	k_spin_unlock(&lock, key);
124 
125 	return 0;
126 }
127 
counter_ambiq_get_value(const struct device * dev,uint32_t * ticks)128 static int counter_ambiq_get_value(const struct device *dev, uint32_t *ticks)
129 {
130 	const struct counter_ambiq_config *cfg = dev->config;
131 
132 	k_spinlock_key_t key = k_spin_lock(&lock);
133 
134 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
135 	*ticks = (am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERA)) |
136 		 (am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERB) << 16);
137 #else
138 	*ticks = am_hal_timer_read(cfg->instance);
139 #endif
140 
141 	k_spin_unlock(&lock, key);
142 
143 	return 0;
144 }
145 
counter_ambiq_set_alarm(const struct device * dev,uint8_t chan_id,const struct counter_alarm_cfg * alarm_cfg)146 static int counter_ambiq_set_alarm(const struct device *dev, uint8_t chan_id,
147 				   const struct counter_alarm_cfg *alarm_cfg)
148 {
149 	ARG_UNUSED(chan_id);
150 	struct counter_ambiq_data *data = dev->data;
151 	const struct counter_ambiq_config *cfg = dev->config;
152 	uint32_t now;
153 
154 	counter_ambiq_get_value(dev, &now);
155 
156 	k_spinlock_key_t key = k_spin_lock(&lock);
157 
158 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
159 	am_hal_ctimer_int_clear(AM_HAL_CTIMER_INT_TIMERA0C0);
160 	am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA0C0);
161 
162 	if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
163 		am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0,
164 					  now + alarm_cfg->ticks);
165 	} else {
166 		am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, alarm_cfg->ticks);
167 	}
168 #else
169 	/* Enable interrupt, due to counter_ambiq_cancel_alarm() disables it*/
170 	am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
171 	am_hal_timer_interrupt_enable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
172 
173 	if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
174 		am_hal_timer_compare1_set(cfg->instance, now + alarm_cfg->ticks);
175 	} else {
176 		am_hal_timer_compare1_set(cfg->instance, alarm_cfg->ticks);
177 	}
178 #endif
179 
180 	data->user_data = alarm_cfg->user_data;
181 	data->callback = alarm_cfg->callback;
182 
183 	k_spin_unlock(&lock, key);
184 
185 	return 0;
186 }
187 
counter_ambiq_cancel_alarm(const struct device * dev,uint8_t chan_id)188 static int counter_ambiq_cancel_alarm(const struct device *dev, uint8_t chan_id)
189 {
190 	ARG_UNUSED(chan_id);
191 	const struct counter_ambiq_config *cfg = dev->config;
192 	k_spinlock_key_t key = k_spin_lock(&lock);
193 
194 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
195 	am_hal_ctimer_int_disable(AM_HAL_CTIMER_INT_TIMERA0C0);
196 	/* Reset the compare register */
197 	am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, 0);
198 #else
199 	am_hal_timer_interrupt_disable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
200 	/* Reset the compare register */
201 	am_hal_timer_compare1_set(cfg->instance, 0);
202 #endif
203 
204 	k_spin_unlock(&lock, key);
205 
206 	return 0;
207 }
208 
counter_ambiq_set_top_value(const struct device * dev,const struct counter_top_cfg * cfg)209 static int counter_ambiq_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
210 {
211 	const struct counter_ambiq_config *config = dev->config;
212 
213 	if (cfg->ticks != config->counter_info.max_top_value) {
214 		return -ENOTSUP;
215 	} else {
216 		return 0;
217 	}
218 }
219 
counter_ambiq_get_pending_int(const struct device * dev)220 static uint32_t counter_ambiq_get_pending_int(const struct device *dev)
221 {
222 	return 0;
223 }
224 
counter_ambiq_get_top_value(const struct device * dev)225 static uint32_t counter_ambiq_get_top_value(const struct device *dev)
226 {
227 	const struct counter_ambiq_config *config = dev->config;
228 
229 	return config->counter_info.max_top_value;
230 }
231 
232 static DEVICE_API(counter, counter_api) = {
233 	.start = counter_ambiq_start,
234 	.stop = counter_ambiq_stop,
235 	.get_value = counter_ambiq_get_value,
236 	.set_alarm = counter_ambiq_set_alarm,
237 	.cancel_alarm = counter_ambiq_cancel_alarm,
238 	.set_top_value = counter_ambiq_set_top_value,
239 	.get_pending_int = counter_ambiq_get_pending_int,
240 	.get_top_value = counter_ambiq_get_top_value,
241 };
242 
243 #define APOLLO3_HANDLE_SHARED_TIMER_IRQ(n)                                                         \
244 	static const struct device *const dev_##n = DEVICE_DT_INST_GET(n);                         \
245 	struct counter_ambiq_data *const data_##n = dev_##n->data;                                 \
246 	uint32_t status_##n = CTIMERn(n)->INTSTAT;                                                 \
247 	status_##n &= CTIMERn(n)->INTEN;                                                           \
248 	if (status_##n) {                                                                          \
249 		CTIMERn(n)->INTCLR = AM_HAL_CTIMER_INT_TIMERA0C0;                                  \
250 		counter_ambiq_get_value(dev_##n, &now);                                            \
251 		if (data_##n->callback) {                                                          \
252 			data_##n->callback(dev_##n, 0, now, data_##n->user_data);                  \
253 		}                                                                                  \
254 	}
255 
counter_ambiq_isr(void * arg)256 static void counter_ambiq_isr(void *arg)
257 {
258 	uint32_t now = 0;
259 
260 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
261 	ARG_UNUSED(arg);
262 
263 	DT_INST_FOREACH_STATUS_OKAY(APOLLO3_HANDLE_SHARED_TIMER_IRQ)
264 #else
265 	const struct device *dev = (const struct device *)arg;
266 	struct counter_ambiq_data *data = dev->data;
267 	const struct counter_ambiq_config *cfg = dev->config;
268 
269 	am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
270 	counter_ambiq_get_value(dev, &now);
271 
272 	if (data->callback) {
273 		data->callback(dev, 0, now, data->user_data);
274 	}
275 #endif
276 }
277 
278 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
279 /* Apollo3 counters share the same irq number, connect irq here will cause build error, so we
280  * leave this function blank here and do it in counter_irq_config_func
281  */
282 #define AMBIQ_COUNTER_CONFIG_FUNC(idx) static void counter_irq_config_func_##idx(void){};
283 #else
284 #define AMBIQ_COUNTER_CONFIG_FUNC(idx)                                                             \
285 	static void counter_irq_config_func_##idx(void)                                            \
286 	{                                                                                          \
287 		NVIC_ClearPendingIRQ(DT_INST_IRQN(idx));                                           \
288 		IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), counter_ambiq_isr,      \
289 			    DEVICE_DT_INST_GET(idx), 0);                                           \
290 		irq_enable(DT_INST_IRQN(idx));                                                     \
291 	};
292 #endif
293 
294 #define AMBIQ_COUNTER_INIT(idx)                                                                    \
295 	static void counter_irq_config_func_##idx(void);                                           \
296 	static struct counter_ambiq_data counter_data_##idx;                                       \
297 	static const struct counter_ambiq_config counter_config_##idx = {                          \
298 		.instance = (DT_INST_REG_ADDR(idx) - DT_INST_REG_ADDR(0)) / DT_INST_REG_SIZE(idx), \
299 		.clk_src = DT_INST_PROP(idx, clk_source),                                          \
300 		.counter_info = {.max_top_value = UINT32_MAX,                                      \
301 				 .freq = DT_INST_PROP(idx, clock_frequency),                       \
302 				 .flags = COUNTER_CONFIG_INFO_COUNT_UP,                            \
303 				 .channels = 1},                                                   \
304 		.irq_config_func = counter_irq_config_func_##idx,                                  \
305 	};                                                                                         \
306 	AMBIQ_COUNTER_CONFIG_FUNC(idx)                                                             \
307 	DEVICE_DT_INST_DEFINE(idx, counter_ambiq_init, NULL, &counter_data_##idx,                  \
308 			      &counter_config_##idx, PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY,   \
309 			      &counter_api);
310 DT_INST_FOREACH_STATUS_OKAY(AMBIQ_COUNTER_INIT);
311