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Searched refs:_num (Results 1 – 21 of 21) sorted by relevance

/Zephyr-latest/drivers/w1/
Dw1_max32.c189 #define MAX32_W1_INIT(_num) \ argument
190 PINCTRL_DT_INST_DEFINE(_num); \
191 static const struct max32_w1_config max32_w1_config_##_num = { \
192 .w1_config.slave_count = W1_INST_SLAVE_COUNT(_num), \
193 .regs = (mxc_owm_regs_t *)DT_INST_REG_ADDR(_num), \
194 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
195 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
196 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
197 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
198 .internal_pullup = DT_INST_PROP(_num, internal_pullup), \
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/Zephyr-latest/drivers/pwm/
Dpwm_max32.c126 #define PWM_MAX32_DEFINE(_num) \ argument
127 static struct max32_pwm_data max32_pwm_data_##_num; \
128 PINCTRL_DT_INST_DEFINE(_num); \
129 static const struct max32_pwm_config max32_pwm_config_##_num = { \
130 .regs = (mxc_tmr_regs_t *)DT_REG_ADDR(DT_INST_PARENT(_num)), \
131 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
132 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(_num))), \
133 .perclk.bus = DT_CLOCKS_CELL(DT_INST_PARENT(_num), offset), \
134 .perclk.bit = DT_CLOCKS_CELL(DT_INST_PARENT(_num), bit), \
135 .perclk.clk_src = DT_PROP(DT_INST_PARENT(_num), clock_source), \
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/Zephyr-latest/drivers/adc/
Dadc_max32.c308 #define MAX32_ADC_INIT(_num) \ argument
309 PINCTRL_DT_INST_DEFINE(_num); \
310 static void max32_adc_irq_init_##_num(void) \
312 IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), adc_max32_isr, \
313 DEVICE_DT_INST_GET(_num), 0); \
314 irq_enable(DT_INST_IRQN(_num)); \
316 static const struct max32_adc_config max32_adc_config_##_num = { \
317 .channel_count = DT_INST_PROP(_num, channel_count), \
318 .regs = (mxc_adc_regs_t *)DT_INST_REG_ADDR(_num), \
319 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
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Dadc_emul.c612 #define ADC_EMUL_INIT(_num) \ argument
613 static DEVICE_API(adc, adc_emul_api_##_num) = { \
616 .ref_internal = DT_INST_PROP(_num, ref_internal_mv), \
622 adc_emul_ch_cfg_##_num[DT_INST_PROP(_num, nchannels)]; \
624 static const struct adc_emul_config adc_emul_config_##_num = { \
625 .num_channels = DT_INST_PROP(_num, nchannels), \
628 static struct adc_emul_data adc_emul_data_##_num = { \
629 ADC_CONTEXT_INIT_TIMER(adc_emul_data_##_num, ctx), \
630 ADC_CONTEXT_INIT_LOCK(adc_emul_data_##_num, ctx), \
631 ADC_CONTEXT_INIT_SYNC(adc_emul_data_##_num, ctx), \
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/Zephyr-latest/drivers/counter/
Dcounter_max32_timer.c307 #define TIMER(_num) DT_INST_PARENT(_num) argument
310 #define COUNTER_MAX32_DEFINE(_num) \ argument
311 static struct max32_tmr_ch_data counter##_num##_ch_data[MAX32_TIMER_CH]; \
312 static void max32_tmr_irq_init_##_num(const struct device *dev) \
314 IRQ_CONNECT(DT_IRQN(TIMER(_num)), DT_IRQ(TIMER(_num), priority), \
315 counter_max32_isr, DEVICE_DT_INST_GET(_num), 0); \
316 irq_enable(DT_IRQN(TIMER(_num))); \
318 static const struct max32_tmr_config max32_tmr_config_##_num = { \
321 .max_top_value = WRAP_MXC_IS_32B_TIMER(MAX32_TIM(_num)) \
325 DT_PROP(TIMER(_num), clock_source)) / \
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Dcounter_max32_rtc.c239 #define COUNTER_RTC_MAX32_INIT(_num) \ argument
240 static struct max32_rtc_data rtc_max32_data_##_num; \
241 static void max32_rtc_irq_init_##_num(void) \
243 IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), rtc_max32_isr, \
244 DEVICE_DT_INST_GET(_num), 0); \
245 irq_enable(DT_INST_IRQN(_num)); \
246 if (DT_INST_PROP(_num, wakeup_source)) { \
250 static const struct max32_rtc_config rtc_max32_config_##_num = { \
258 .regs = (mxc_rtc_regs_t *)DT_INST_REG_ADDR(_num), \
259 .irq_func = max32_rtc_irq_init_##_num, \
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/Zephyr-latest/drivers/watchdog/
Dwdt_max32.c252 #define MAX32_WDT_INIT(_num) \ argument
253 static void wdt_max32_irq_init_##_num(void) \
255 IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), wdt_max32_isr, \
256 DEVICE_DT_INST_GET(_num), 0); \
257 irq_enable(DT_INST_IRQN(_num)); \
259 static struct max32_wdt_data max32_wdt_data##_num; \
260 static const struct max32_wdt_config max32_wdt_config##_num = { \
261 .regs = (mxc_wdt_regs_t *)DT_INST_REG_ADDR(_num), \
262 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
264 DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK), \
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/Zephyr-latest/drivers/gpio/
Dgpio_max32.c245 #define MAX32_GPIO_INIT(_num) \ argument
246 static void gpio_max32_irq_init_##_num(void) \
248 IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), gpio_max32_isr, \
249 DEVICE_DT_INST_GET(_num), 0); \
250 irq_enable(DT_INST_IRQN(_num)); \
252 static struct max32_gpio_data max32_gpio_data_##_num; \
253 static const struct max32_gpio_config max32_gpio_config_##_num = { \
256 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_num), \
258 .regs = (mxc_gpio_regs_t *)DT_INST_REG_ADDR(_num), \
259 .irq_func = &gpio_max32_irq_init_##_num, \
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Dgpio_emul.c849 #define GPIO_EMUL_INT_CAPS(_num) (0 \ argument
850 + DT_INST_PROP(_num, rising_edge) \
852 + DT_INST_PROP(_num, falling_edge) \
854 + DT_INST_PROP(_num, high_level) \
856 + DT_INST_PROP(_num, low_level) \
860 #define DEFINE_GPIO_EMUL(_num) \ argument
863 gpio_emul_flags_##_num[DT_INST_PROP(_num, ngpios)]; \
865 static const struct gpio_emul_config gpio_emul_config_##_num = {\
868 GPIO_PORT_PIN_MASK_FROM_DT_INST(_num), \
870 .num_pins = DT_INST_PROP(_num, ngpios), \
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/Zephyr-latest/drivers/serial/
Duart_max32.c424 #define MAX32_UART_INIT(_num) \ argument
425 PINCTRL_DT_INST_DEFINE(_num); \
427 (static void uart_max32_irq_init_##_num(const struct device *dev) \
429 IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), \
430 uart_max32_isr, DEVICE_DT_INST_GET(_num), 0); \
431 irq_enable(DT_INST_IRQN(_num)); \
433 static const struct max32_uart_config max32_uart_config_##_num = { \
434 .regs = (mxc_uart_regs_t *)DT_INST_REG_ADDR(_num), \
435 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
436 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
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/Zephyr-latest/drivers/flash/
Dflash_max32.c161 #define DEFINE_FLASH_MAX32(_num) \ argument
162 static const struct max32_flash_dev_config max32_flash_dev_cfg_##_num = { \
163 .flash_base = DT_INST_FOREACH_CHILD(_num, GET_FLASH_BASE), \
164 .flash_erase_blk_sz = DT_INST_FOREACH_CHILD(_num, GET_ERASE_BLOCK_SIZE), \
168 DT_INST_FOREACH_CHILD(_num, GET_WRITE_BLOCK_SIZE), \
171 FLASH_MAX32_CONFIG_PAGE_LAYOUT(_num)}; \
172 static struct max32_flash_dev_data max32_flash_dev_data_##_num; \
173 DEVICE_DT_INST_DEFINE(_num, flash_max32_init, NULL, &max32_flash_dev_data_##_num, \
174 &max32_flash_dev_cfg_##_num, POST_KERNEL, \
/Zephyr-latest/drivers/i2c/
Di2c_sbcon.c143 #define DEFINE_I2C_SBCON(_num) \ argument
145 static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \
147 static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \
148 .sbcon = (void *)DT_INST_REG_ADDR(_num), \
149 .bitrate = DT_INST_PROP(_num, clock_frequency), \
152 I2C_DEVICE_DT_INST_DEFINE(_num, \
155 &i2c_sbcon_dev_data_##_num, \
156 &i2c_sbcon_dev_cfg_##_num, \
Di2c_gpio.c206 #define DEFINE_I2C_GPIO(_num) \ argument
208 static struct i2c_gpio_context i2c_gpio_dev_data_##_num; \
210 static const struct i2c_gpio_config i2c_gpio_dev_cfg_##_num = { \
211 .scl_gpio = GPIO_DT_SPEC_INST_GET(_num, scl_gpios), \
212 .sda_gpio = GPIO_DT_SPEC_INST_GET(_num, sda_gpios), \
213 .bitrate = DT_INST_PROP(_num, clock_frequency), \
216 I2C_DEVICE_DT_INST_DEFINE(_num, \
219 &i2c_gpio_dev_data_##_num, \
220 &i2c_gpio_dev_cfg_##_num, \
Di2c_max32_rtio.c418 #define DEFINE_I2C_MAX32(_num) \ argument
419 PINCTRL_DT_INST_DEFINE(_num); \
420 I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
421 static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
422 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
423 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
424 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
425 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
426 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
427 .bitrate = DT_INST_PROP(_num, clock_frequency), \
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Di2c_max32.c936 #define DEFINE_I2C_MAX32(_num) \ argument
937 PINCTRL_DT_INST_DEFINE(_num); \
938 I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
939 static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
940 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
941 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
942 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
943 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
944 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
945 .bitrate = DT_INST_PROP(_num, clock_frequency), \
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/Zephyr-latest/drivers/eeprom/
Deeprom_tmp116.c62 #define DEFINE_TMP116(_num) \ argument
63 static const struct eeprom_tmp116_config eeprom_tmp116_config##_num = { \
64 .parent = DEVICE_DT_GET(DT_INST_BUS(_num)) \
66 DEVICE_DT_INST_DEFINE(_num, eeprom_tmp116_init, NULL, \
67 NULL, &eeprom_tmp116_config##_num, POST_KERNEL, \
/Zephyr-latest/drivers/sensor/rohm/bh1750/
Dbh1750.c211 #define DEFINE_BH1750(_num) \ argument
212 static struct bh1750_data bh1750_data_##_num; \
213 static const struct bh1750_dev_config bh1750_config_##_num = { \
214 .bus = I2C_DT_SPEC_INST_GET(_num), \
215 .mtreg = DT_INST_PROP(_num, mtreg), \
216 .resolution = DT_INST_PROP(_num, resolution) \
218 SENSOR_DEVICE_DT_INST_DEFINE(_num, bh1750_init, NULL, \
219 &bh1750_data_##_num, &bh1750_config_##_num, POST_KERNEL, \
/Zephyr-latest/drivers/sensor/ti/tmag5170/
Dtmag5170.c552 #define DEFINE_TMAG5170(_num) \ argument
553 static struct tmag5170_data tmag5170_data_##_num; \
554 static const struct tmag5170_dev_config tmag5170_config_##_num = { \
555 .bus = SPI_DT_SPEC_INST_GET(_num, \
560 .magnetic_channels = DT_INST_ENUM_IDX(_num, magnetic_channels), \
561 .x_range = DT_INST_ENUM_IDX(_num, x_range), \
562 .y_range = DT_INST_ENUM_IDX(_num, y_range), \
563 .z_range = DT_INST_ENUM_IDX(_num, z_range), \
564 .operating_mode = DT_INST_PROP(_num, operating_mode), \
565 .oversampling = DT_INST_ENUM_IDX(_num, oversampling), \
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/Zephyr-latest/drivers/sensor/ti/tmp114/
Dtmp114.c230 #define DEFINE_TMP114(_num) \ argument
231 static struct tmp114_data tmp114_data_##_num; \
232 static const struct tmp114_dev_config tmp114_config_##_num = { \
233 .bus = I2C_DT_SPEC_INST_GET(_num) \
235 SENSOR_DEVICE_DT_INST_DEFINE(_num, tmp114_init, NULL, \
236 &tmp114_data_##_num, &tmp114_config_##_num, POST_KERNEL, \
/Zephyr-latest/drivers/sensor/ti/tmp116/
Dtmp116.c405 #define DEFINE_TMP116(_num) \ argument
406 static struct tmp116_data tmp116_data_##_num; \
407 static const struct tmp116_dev_config tmp116_config_##_num = { \
408 .bus = I2C_DT_SPEC_INST_GET(_num), \
409 .odr = DT_INST_PROP(_num, odr), \
411 SENSOR_DEVICE_DT_INST_DEFINE(_num, tmp116_init, NULL, \
412 &tmp116_data_##_num, &tmp116_config_##_num, POST_KERNEL, \
/Zephyr-latest/drivers/spi/
Dspi_max32.c948 #define DEFINE_SPI_MAX32_RTIO(_num) SPI_RTIO_DEFINE(max32_spi_rtio_##_num, \ argument
952 #define DEFINE_SPI_MAX32(_num) \ argument
953 PINCTRL_DT_INST_DEFINE(_num); \
954 SPI_MAX32_IRQ_CONFIG_FUNC(_num) \
955 COND_CODE_1(CONFIG_SPI_RTIO, (DEFINE_SPI_MAX32_RTIO(_num)), ()); \
956 static const struct max32_spi_config max32_spi_config_##_num = { \
957 .regs = (mxc_spi_regs_t *)DT_INST_REG_ADDR(_num), \
958 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
959 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
960 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
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