Searched refs:STS (Results 1 – 12 of 12) sorted by relevance
268 regs->STS = 0xfffffffful; in qmspi_tx_dummy_clocks()272 qstatus = regs->STS; in qmspi_tx_dummy_clocks()417 regs->STS = 0xfffffffful; in qmspi_tx()425 if (regs->STS & MCHP_QMSPI_STS_TXBF_RO) { in qmspi_tx()432 if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) { in qmspi_tx()438 while (regs->STS & MCHP_QMSPI_STS_TXBF_RO) { in qmspi_tx()448 if (regs->STS & MCHP_QMSPI_STS_DONE) { in qmspi_tx()487 regs->STS = 0xfffffffful; in qmspi_rx()498 if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) { in qmspi_rx()503 if (!(regs->STS & MCHP_QMSPI_STS_RXBE_RO)) { in qmspi_rx()[all …]
453 regs->STS = 0xffffffffu; in qmspi_xfr_cm_init()630 regs->STS = 0xffffffffu; in qmspi_xfr_sync()634 uint32_t temp = regs->STS; in qmspi_xfr_sync()637 temp = regs->STS; in qmspi_xfr_sync()646 qdata->qstatus = regs->STS; in qmspi_xfr_sync()653 qdata->qstatus = regs->STS; in qmspi_xfr_sync()692 regs->STS = 0xffffffffu; in qmspi_xfr_start_async()809 if (regs->STS & MCHP_QMSPI_STS_ACTIVE_RO) { in qmspi_release()812 while (regs->STS & MCHP_QMSPI_STS_ACTIVE_RO) { in qmspi_release()836 uint32_t qstatus = regs->STS; in qmspi_xec_isr()[all …]
24 B32TMR1_REGS->STS = 1; /* Clear interrupt */ in soc_timing_init()
601 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_read()626 if (ESPI_FC_REGS->STS & err_mask) { in espi_xec_flash_read()628 ESPI_FC_REGS->STS = err_mask; in espi_xec_flash_read()655 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_write()682 if (ESPI_FC_REGS->STS & err_mask) { in espi_xec_flash_write()684 ESPI_FC_REGS->STS = err_mask; in espi_xec_flash_write()705 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_erase()716 status = ESPI_FC_REGS->STS; in espi_xec_flash_erase()717 ESPI_FC_REGS->STS = status; in espi_xec_flash_erase()732 if (ESPI_FC_REGS->STS & err_mask) { in espi_xec_flash_erase()[all …]
222 regs->STS = MCHP_QMSPI_STS_RW1C_MASK; in saf_qmspi_init()
240 qregs->STS = MCHP_QMSPI_STS_RW1C_MASK; in saf_qmspi_init()
34 regs->STS = 1; /* Clear interrupt */ in soc_timing_init()
79 volatile uint16_t STS; member
78 volatile uint8_t STS; member
180 return counter->STS; in counter_xec_get_pending_int()253 counter->STS = MCHP_BTMR_STS_ACTIVE; in counter_xec_isr()
73 self.regs.STS = 0x03165 …(self.regs.STS >> 5) & 1, (self.regs.STS >> 4) & 1, (self.regs.STS >> 3) & 1, (self.regs.STS >> 2)…
415 volatile uint32_t STS; member
