1 /*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_xec_espi
8
9 #include <zephyr/kernel.h>
10 #include <soc.h>
11 #include <errno.h>
12 #include <zephyr/drivers/espi.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16 #include "espi_utils.h"
17
18 /* Minimum delay before acknowledging a virtual wire */
19 #define ESPI_XEC_VWIRE_ACK_DELAY 10ul
20
21 /* Maximum timeout to transmit a virtual wire packet.
22 * 10 ms expressed in multiples of 100us
23 */
24 #define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
25
26 #define VW_MAX_GIRQS 2ul
27
28 /* 200ms */
29 #define MAX_OOB_TIMEOUT 200ul
30 /* 1s */
31 #define MAX_FLASH_TIMEOUT 1000ul
32
33 /* While issuing flash erase command, it should be ensured that the transfer
34 * length specified is non-zero.
35 */
36 #define ESPI_FLASH_ERASE_DUMMY 0x01ul
37
38 /* OOB maximum address configuration */
39 #define ESPI_XEC_OOB_ADDR_MSW 0x1FFFul
40 #define ESPI_XEC_OOB_ADDR_LSW 0xFFFFul
41
42 /* OOB Rx length */
43 #define ESPI_XEC_OOB_RX_LEN 0x7F00ul
44
45 /* BARs as defined in LPC spec chapter 11 */
46 #define ESPI_XEC_KBC_BAR_ADDRESS 0x00600000
47 #define ESPI_XEC_UART0_BAR_ADDRESS 0x03F80000
48 #define ESPI_XEC_MBOX_BAR_ADDRESS 0x03600000
49 #define ESPI_XEC_PORT80_BAR_ADDRESS 0x00800000
50 #define ESPI_XEC_PORT81_BAR_ADDRESS 0x00810000
51
52 /* Espi peripheral has 3 uart ports */
53 #define ESPI_PERIPHERAL_UART_PORT0 0
54 #define ESPI_PERIPHERAL_UART_PORT1 1
55 #define ESPI_PERIPHERAL_UART_PORT2 2
56
57 #define UART_DEFAULT_IRQ_POS 2u
58 #define UART_DEFAULT_IRQ BIT(UART_DEFAULT_IRQ_POS)
59
60 /* VM index 0x50 for OCB */
61 #define ESPI_OCB_VW_INDEX 0x50u
62
63 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
64
65 struct espi_isr {
66 uint32_t girq_bit;
67 void (*the_isr)(const struct device *dev);
68 };
69
70 struct espi_xec_config {
71 uint32_t base_addr;
72 uint8_t bus_girq_id;
73 uint8_t vw_girq_ids[VW_MAX_GIRQS];
74 uint8_t pc_girq_id;
75 const struct pinctrl_dev_config *pcfg;
76 };
77
78 struct espi_xec_data {
79 sys_slist_t callbacks;
80 struct k_sem tx_lock;
81 struct k_sem rx_lock;
82 struct k_sem flash_lock;
83 };
84
85 struct xec_signal {
86 uint8_t xec_reg_idx;
87 uint8_t bit;
88 uint8_t dir;
89 };
90
91 enum mchp_msvw_regs {
92 MCHP_MSVW00,
93 MCHP_MSVW01,
94 MCHP_MSVW02,
95 MCHP_MSVW03,
96 MCHP_MSVW04,
97 MCHP_MSVW05,
98 MCHP_MSVW06,
99 MCHP_MSVW07,
100 MCHP_MSVW08,
101 };
102
103 enum mchp_smvw_regs {
104 MCHP_SMVW00,
105 MCHP_SMVW01,
106 MCHP_SMVW02,
107 MCHP_SMVW03,
108 MCHP_SMVW04,
109 MCHP_SMVW05,
110 MCHP_SMVW06,
111 MCHP_SMVW07,
112 MCHP_SMVW08,
113 };
114
115 /* Microchip canonical virtual wire mapping
116 * --------------------------------------------------------------------------------|
117 * VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
118 * --------------------------------------------------------------------------------|
119 * System Event Virtual Wires
120 * --------------------------------------------------------------------------------|
121 * 2h | MSVW00 | res | SLP_S5# | SLP_S4# | SLP_S3# |
122 * 3h | MSVW01 | res | OOB_RST_WARN | PLTRST# | SUS_STAT# |
123 * 4h | SMVW00 | PME# | WAKE# | res | OOB_RST_ACK |
124 * 5h | SMVW01 | TARGET_BOOT_STS | ERR_NONFATAL | ERR_FATAL | TARGET_BOOT_DONE |
125 * 6h | SMVW02 | HOST_RST_ACK | RCIN# | SMI# | SCI# |
126 * 7h | MSVW02 | res | res | res | HOS_RST_WARN |
127 * --------------------------------------------------------------------------------|
128 * Platform specific virtual wires
129 * --------------------------------------------------------------------------------|
130 * 40h | SMVW03 | res | res | DNX_ACK | SUS_ACK# |
131 * 41h | MSVW03 | SLP_A# | res | SUS_PDNACK| SUS_WARN# |
132 * 42h | MSVW04 | res | res | SLP_WLAN# | SLP_LAN# |
133 * 43h | MSVW05 | generic | generic | generic | generic |
134 * 44h | MSVW06 | generic | generic | generic | generic |
135 * 45h | SMVW04 | generic | generic | generic | generic |
136 * 46h | SMVW05 | generic | generic | generic | generic |
137 * 47h | MSVW07 | res | res | res | HOST_C10 |
138 * 4Ah | MSVW08 | res | res | DNX_WARN | res |
139 * 50h | SMVW06 | ESPI_OCB_3 | ESPI_OCB_2 | ESPI_OCB_1| ESPI_OCB_0 |
140 */
141
142 static const struct xec_signal vw_tbl[] = {
143 /* MSVW00 */
144 [ESPI_VWIRE_SIGNAL_SLP_S3] = {MCHP_MSVW00, ESPI_VWIRE_SRC_ID0,
145 ESPI_CONTROLLER_TO_TARGET},
146 [ESPI_VWIRE_SIGNAL_SLP_S4] = {MCHP_MSVW00, ESPI_VWIRE_SRC_ID1,
147 ESPI_CONTROLLER_TO_TARGET},
148 [ESPI_VWIRE_SIGNAL_SLP_S5] = {MCHP_MSVW00, ESPI_VWIRE_SRC_ID2,
149 ESPI_CONTROLLER_TO_TARGET},
150 /* MSVW01 */
151 [ESPI_VWIRE_SIGNAL_SUS_STAT] = {MCHP_MSVW01, ESPI_VWIRE_SRC_ID0,
152 ESPI_CONTROLLER_TO_TARGET},
153 [ESPI_VWIRE_SIGNAL_PLTRST] = {MCHP_MSVW01, ESPI_VWIRE_SRC_ID1,
154 ESPI_CONTROLLER_TO_TARGET},
155 [ESPI_VWIRE_SIGNAL_OOB_RST_WARN] = {MCHP_MSVW01, ESPI_VWIRE_SRC_ID2,
156 ESPI_CONTROLLER_TO_TARGET},
157 /* SMVW00 */
158 [ESPI_VWIRE_SIGNAL_OOB_RST_ACK] = {MCHP_SMVW00, ESPI_VWIRE_SRC_ID0,
159 ESPI_TARGET_TO_CONTROLLER},
160 [ESPI_VWIRE_SIGNAL_WAKE] = {MCHP_SMVW00, ESPI_VWIRE_SRC_ID2,
161 ESPI_TARGET_TO_CONTROLLER},
162 [ESPI_VWIRE_SIGNAL_PME] = {MCHP_SMVW00, ESPI_VWIRE_SRC_ID3,
163 ESPI_TARGET_TO_CONTROLLER},
164 /* SMVW01 */
165 [ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE] = {MCHP_SMVW01, ESPI_VWIRE_SRC_ID0,
166 ESPI_TARGET_TO_CONTROLLER},
167 [ESPI_VWIRE_SIGNAL_ERR_FATAL] = {MCHP_SMVW01, ESPI_VWIRE_SRC_ID1,
168 ESPI_TARGET_TO_CONTROLLER},
169 [ESPI_VWIRE_SIGNAL_ERR_NON_FATAL] = {MCHP_SMVW01, ESPI_VWIRE_SRC_ID2,
170 ESPI_TARGET_TO_CONTROLLER},
171 [ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS] = {MCHP_SMVW01, ESPI_VWIRE_SRC_ID3,
172 ESPI_TARGET_TO_CONTROLLER},
173 /* SMVW02 */
174 [ESPI_VWIRE_SIGNAL_SCI] = {MCHP_SMVW02, ESPI_VWIRE_SRC_ID0,
175 ESPI_TARGET_TO_CONTROLLER},
176 [ESPI_VWIRE_SIGNAL_SMI] = {MCHP_SMVW02, ESPI_VWIRE_SRC_ID1,
177 ESPI_TARGET_TO_CONTROLLER},
178 [ESPI_VWIRE_SIGNAL_RST_CPU_INIT] = {MCHP_SMVW02, ESPI_VWIRE_SRC_ID2,
179 ESPI_TARGET_TO_CONTROLLER},
180 [ESPI_VWIRE_SIGNAL_HOST_RST_ACK] = {MCHP_SMVW02, ESPI_VWIRE_SRC_ID3,
181 ESPI_TARGET_TO_CONTROLLER},
182 /* MSVW02 */
183 [ESPI_VWIRE_SIGNAL_HOST_RST_WARN] = {MCHP_MSVW02, ESPI_VWIRE_SRC_ID0,
184 ESPI_CONTROLLER_TO_TARGET},
185 /* SMVW03 */
186 [ESPI_VWIRE_SIGNAL_SUS_ACK] = {MCHP_SMVW03, ESPI_VWIRE_SRC_ID0,
187 ESPI_TARGET_TO_CONTROLLER},
188 [ESPI_VWIRE_SIGNAL_DNX_ACK] = {MCHP_SMVW03, ESPI_VWIRE_SRC_ID1,
189 ESPI_TARGET_TO_CONTROLLER},
190 /* MSVW03 */
191 [ESPI_VWIRE_SIGNAL_SUS_WARN] = {MCHP_MSVW03, ESPI_VWIRE_SRC_ID0,
192 ESPI_CONTROLLER_TO_TARGET},
193 [ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK] = {MCHP_MSVW03, ESPI_VWIRE_SRC_ID1,
194 ESPI_CONTROLLER_TO_TARGET},
195 [ESPI_VWIRE_SIGNAL_SLP_A] = {MCHP_MSVW03, ESPI_VWIRE_SRC_ID3,
196 ESPI_CONTROLLER_TO_TARGET},
197 /* MSVW04 */
198 [ESPI_VWIRE_SIGNAL_SLP_LAN] = {MCHP_MSVW04, ESPI_VWIRE_SRC_ID0,
199 ESPI_CONTROLLER_TO_TARGET},
200 [ESPI_VWIRE_SIGNAL_SLP_WLAN] = {MCHP_MSVW04, ESPI_VWIRE_SRC_ID1,
201 ESPI_CONTROLLER_TO_TARGET},
202 /* MSVW07 */
203 [ESPI_VWIRE_SIGNAL_HOST_C10] = {MCHP_MSVW07, ESPI_VWIRE_SRC_ID0,
204 ESPI_CONTROLLER_TO_TARGET},
205 /* MSVW08 */
206 [ESPI_VWIRE_SIGNAL_DNX_WARN] = {MCHP_MSVW08, ESPI_VWIRE_SRC_ID1,
207 ESPI_CONTROLLER_TO_TARGET},
208 /* SMVW06 */
209 [ESPI_VWIRE_SIGNAL_OCB_0] = {MCHP_SMVW06, ESPI_VWIRE_SRC_ID0,
210 ESPI_TARGET_TO_CONTROLLER},
211 [ESPI_VWIRE_SIGNAL_OCB_1] = {MCHP_SMVW06, ESPI_VWIRE_SRC_ID1,
212 ESPI_TARGET_TO_CONTROLLER},
213 [ESPI_VWIRE_SIGNAL_OCB_2] = {MCHP_SMVW06, ESPI_VWIRE_SRC_ID2,
214 ESPI_TARGET_TO_CONTROLLER},
215 [ESPI_VWIRE_SIGNAL_OCB_3] = {MCHP_SMVW06, ESPI_VWIRE_SRC_ID3,
216 ESPI_TARGET_TO_CONTROLLER},
217 };
218
219 /* Buffer size are expressed in bytes */
220 #ifdef CONFIG_ESPI_OOB_CHANNEL
221 static uint32_t target_rx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
222 static uint32_t target_tx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
223 #endif
224 #ifdef CONFIG_ESPI_FLASH_CHANNEL
225 static uint32_t target_mem[CONFIG_ESPI_FLASH_BUFFER_SIZE >> 2];
226 #endif
227
espi_xec_configure(const struct device * dev,struct espi_cfg * cfg)228 static int espi_xec_configure(const struct device *dev, struct espi_cfg *cfg)
229 {
230 uint8_t iomode = 0;
231 uint8_t cap0 = ESPI_CAP_REGS->GLB_CAP0;
232 uint8_t cap1 = ESPI_CAP_REGS->GLB_CAP1;
233 uint8_t cur_iomode = (cap1 & MCHP_ESPI_GBL_CAP1_IO_MODE_MASK) >>
234 MCHP_ESPI_GBL_CAP1_IO_MODE_POS;
235
236 /* Set frequency */
237 cap1 &= ~MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK;
238
239 switch (cfg->max_freq) {
240 case 20:
241 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M;
242 break;
243 case 25:
244 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M;
245 break;
246 case 33:
247 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M;
248 break;
249 case 50:
250 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M;
251 break;
252 case 66:
253 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 /* Set IO mode */
260 iomode = (cfg->io_caps >> 1);
261 if (iomode > 3) {
262 return -EINVAL;
263 }
264
265 if (iomode != cur_iomode) {
266 cap1 &= ~(MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 <<
267 MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
268 cap1 |= (iomode << MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
269 }
270
271 /* Validate and translate eSPI API channels to MEC capabilities */
272 cap0 &= ~MCHP_ESPI_GBL_CAP0_MASK;
273 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
274 if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_CHANNEL)) {
275 cap0 |= MCHP_ESPI_GBL_CAP0_PC_SUPP;
276 } else {
277 return -EINVAL;
278 }
279 }
280
281 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
282 if (IS_ENABLED(CONFIG_ESPI_VWIRE_CHANNEL)) {
283 cap0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP;
284 } else {
285 return -EINVAL;
286 }
287 }
288
289 if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
290 if (IS_ENABLED(CONFIG_ESPI_OOB_CHANNEL)) {
291 cap0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
292 } else {
293 return -EINVAL;
294 }
295 }
296
297 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
298 if (IS_ENABLED(CONFIG_ESPI_FLASH_CHANNEL)) {
299 cap0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
300 } else {
301 LOG_ERR("Flash channel not supported");
302 return -EINVAL;
303 }
304 }
305
306 ESPI_CAP_REGS->GLB_CAP0 = cap0;
307 ESPI_CAP_REGS->GLB_CAP1 = cap1;
308
309 /* Activate the eSPI block *.
310 * Need to guarantee that this register is configured before RSMRST#
311 * de-assertion and after pinmux
312 */
313 ESPI_EIO_BAR_REGS->IO_ACTV = 1;
314 LOG_DBG("eSPI block activated successfully");
315
316 return 0;
317 }
318
espi_xec_channel_ready(const struct device * dev,enum espi_channel ch)319 static bool espi_xec_channel_ready(const struct device *dev,
320 enum espi_channel ch)
321 {
322 bool sts;
323
324 switch (ch) {
325 case ESPI_CHANNEL_PERIPHERAL:
326 sts = ESPI_CAP_REGS->PC_RDY & MCHP_ESPI_PC_READY;
327 break;
328 case ESPI_CHANNEL_VWIRE:
329 sts = ESPI_CAP_REGS->VW_RDY & MCHP_ESPI_VW_READY;
330 break;
331 case ESPI_CHANNEL_OOB:
332 sts = ESPI_CAP_REGS->OOB_RDY & MCHP_ESPI_OOB_READY;
333 break;
334 case ESPI_CHANNEL_FLASH:
335 sts = ESPI_CAP_REGS->FC_RDY & MCHP_ESPI_FC_READY;
336 break;
337 default:
338 sts = false;
339 break;
340 }
341
342 return sts;
343 }
344
espi_xec_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)345 static int espi_xec_read_lpc_request(const struct device *dev,
346 enum lpc_peripheral_opcode op,
347 uint32_t *data)
348 {
349 ARG_UNUSED(dev);
350
351 if (op >= E8042_START_OPCODE && op <= E8042_MAX_OPCODE) {
352 /* Make sure kbc 8042 is on */
353 if (!(KBC_REGS->KBC_CTRL & MCHP_KBC_CTRL_OBFEN)) {
354 return -ENOTSUP;
355 }
356
357 switch (op) {
358 case E8042_OBF_HAS_CHAR:
359 /* EC has written data back to host. OBF is
360 * automatically cleared after host reads
361 * the data
362 */
363 *data = KBC_REGS->EC_KBC_STS & MCHP_KBC_STS_OBF ? 1 : 0;
364 break;
365 case E8042_IBF_HAS_CHAR:
366 *data = KBC_REGS->EC_KBC_STS & MCHP_KBC_STS_IBF ? 1 : 0;
367 break;
368 case E8042_READ_KB_STS:
369 *data = KBC_REGS->EC_KBC_STS;
370 break;
371 default:
372 return -EINVAL;
373 }
374 } else {
375 return -ENOTSUP;
376 }
377
378 return 0;
379 }
380
espi_xec_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)381 static int espi_xec_write_lpc_request(const struct device *dev,
382 enum lpc_peripheral_opcode op,
383 uint32_t *data)
384 {
385 struct espi_xec_config *config =
386 (struct espi_xec_config *) (dev->config);
387
388 volatile uint32_t __attribute__((unused)) dummy;
389
390 if (op >= E8042_START_OPCODE && op <= E8042_MAX_OPCODE) {
391 /* Make sure kbc 8042 is on */
392 if (!(KBC_REGS->KBC_CTRL & MCHP_KBC_CTRL_OBFEN)) {
393 return -ENOTSUP;
394 }
395
396 switch (op) {
397 case E8042_WRITE_KB_CHAR:
398 KBC_REGS->EC_DATA = *data & 0xff;
399 break;
400 case E8042_WRITE_MB_CHAR:
401 KBC_REGS->EC_AUX_DATA = *data & 0xff;
402 break;
403 case E8042_RESUME_IRQ:
404 MCHP_GIRQ_SRC(config->pc_girq_id) = MCHP_KBC_IBF_GIRQ;
405 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_KBC_IBF_GIRQ;
406 break;
407 case E8042_PAUSE_IRQ:
408 MCHP_GIRQ_ENCLR(config->pc_girq_id) = MCHP_KBC_IBF_GIRQ;
409 break;
410 case E8042_CLEAR_OBF:
411 dummy = KBC_REGS->HOST_AUX_DATA;
412 break;
413 case E8042_SET_FLAG:
414 /* FW shouldn't modify these flags directly */
415 *data &= ~(MCHP_KBC_STS_OBF | MCHP_KBC_STS_IBF |
416 MCHP_KBC_STS_AUXOBF);
417 KBC_REGS->EC_KBC_STS |= *data;
418 break;
419 case E8042_CLEAR_FLAG:
420 /* FW shouldn't modify these flags directly */
421 *data |= (MCHP_KBC_STS_OBF | MCHP_KBC_STS_IBF |
422 MCHP_KBC_STS_AUXOBF);
423 KBC_REGS->EC_KBC_STS &= ~(*data);
424 break;
425 default:
426 return -EINVAL;
427 }
428 } else {
429 return -ENOTSUP;
430
431 }
432
433 return 0;
434 }
435
espi_xec_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)436 static int espi_xec_send_vwire(const struct device *dev,
437 enum espi_vwire_signal signal, uint8_t level)
438 {
439 struct xec_signal signal_info = vw_tbl[signal];
440 uint8_t xec_id = signal_info.xec_reg_idx;
441 uint8_t src_id = signal_info.bit;
442
443 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
444 (xec_id >= ESPI_MSVW_IDX_MAX)) {
445 return -EINVAL;
446 }
447
448 if (signal_info.dir == ESPI_CONTROLLER_TO_TARGET) {
449 ESPI_MSVW_REG *reg = &(ESPI_M2S_VW_REGS->MSVW00) + xec_id;
450 uint8_t *p8 = (uint8_t *)®->SRC;
451
452 *(p8 + (uintptr_t) src_id) = level;
453 }
454
455 if (signal_info.dir == ESPI_TARGET_TO_CONTROLLER) {
456 ESPI_SMVW_REG *reg = &(ESPI_S2M_VW_REGS->SMVW00) + xec_id;
457 uint8_t *p8 = (uint8_t *)®->SRC;
458
459 *(p8 + (uintptr_t) src_id) = level;
460
461 /* Ensure eSPI virtual wire packet is transmitted
462 * There is no interrupt, so need to poll register
463 */
464 uint8_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
465
466 while (reg->SRC_CHG && rd_cnt--) {
467 k_busy_wait(100);
468 }
469 }
470
471 return 0;
472 }
473
espi_xec_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)474 static int espi_xec_receive_vwire(const struct device *dev,
475 enum espi_vwire_signal signal, uint8_t *level)
476 {
477 struct xec_signal signal_info = vw_tbl[signal];
478 uint8_t xec_id = signal_info.xec_reg_idx;
479 uint8_t src_id = signal_info.bit;
480
481 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
482 (xec_id >= ESPI_SMVW_IDX_MAX) || (level == NULL)) {
483 return -EINVAL;
484 }
485
486 if (signal_info.dir == ESPI_CONTROLLER_TO_TARGET) {
487 ESPI_MSVW_REG *reg = &(ESPI_M2S_VW_REGS->MSVW00) + xec_id;
488 *level = ((reg->SRC >> (src_id << 3)) & 0x01ul);
489 }
490
491 if (signal_info.dir == ESPI_TARGET_TO_CONTROLLER) {
492 ESPI_SMVW_REG *reg = &(ESPI_S2M_VW_REGS->SMVW00) + xec_id;
493 *level = ((reg->SRC >> (src_id << 3)) & 0x01ul);
494 }
495
496 return 0;
497 }
498
499 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_xec_send_oob(const struct device * dev,struct espi_oob_packet * pckt)500 static int espi_xec_send_oob(const struct device *dev,
501 struct espi_oob_packet *pckt)
502 {
503 int ret;
504 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
505 uint8_t err_mask = MCHP_ESPI_OOB_TX_STS_IBERR |
506 MCHP_ESPI_OOB_TX_STS_OVRUN |
507 MCHP_ESPI_OOB_TX_STS_BADREQ;
508
509 LOG_DBG("%s", __func__);
510
511 if (!(ESPI_OOB_REGS->TX_STS & MCHP_ESPI_OOB_TX_STS_CHEN)) {
512 LOG_ERR("OOB channel is disabled");
513 return -EIO;
514 }
515
516 if (ESPI_OOB_REGS->TX_STS & MCHP_ESPI_OOB_TX_STS_BUSY) {
517 LOG_ERR("OOB channel is busy");
518 return -EBUSY;
519 }
520
521 if (pckt->len > CONFIG_ESPI_OOB_BUFFER_SIZE) {
522 LOG_ERR("insufficient space");
523 return -EINVAL;
524 }
525
526 memcpy(target_tx_mem, pckt->buf, pckt->len);
527
528 ESPI_OOB_REGS->TX_LEN = pckt->len;
529 ESPI_OOB_REGS->TX_CTRL = MCHP_ESPI_OOB_TX_CTRL_START;
530 LOG_DBG("%s %d", __func__, ESPI_OOB_REGS->TX_LEN);
531
532 /* Wait until ISR or timeout */
533 ret = k_sem_take(&data->tx_lock, K_MSEC(MAX_OOB_TIMEOUT));
534 if (ret == -EAGAIN) {
535 return -ETIMEDOUT;
536 }
537
538 if (ESPI_OOB_REGS->TX_STS & err_mask) {
539 LOG_ERR("Tx failed %x", ESPI_OOB_REGS->TX_STS);
540 ESPI_OOB_REGS->TX_STS = err_mask;
541 return -EIO;
542 }
543
544 return 0;
545 }
546
espi_xec_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)547 static int espi_xec_receive_oob(const struct device *dev,
548 struct espi_oob_packet *pckt)
549 {
550 uint8_t err_mask = MCHP_ESPI_OOB_RX_STS_IBERR |
551 MCHP_ESPI_OOB_RX_STS_OVRUN;
552
553 if (ESPI_OOB_REGS->TX_STS & err_mask) {
554 return -EIO;
555 }
556
557 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
558 int ret;
559 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
560
561 /* Wait until ISR or timeout */
562 ret = k_sem_take(&data->rx_lock, K_MSEC(MAX_OOB_TIMEOUT));
563 if (ret == -EAGAIN) {
564 return -ETIMEDOUT;
565 }
566 #endif
567 /* Check if buffer passed to driver can fit the received buffer */
568 uint32_t rcvd_len = ESPI_OOB_REGS->RX_LEN & MCHP_ESPI_OOB_RX_LEN_MASK;
569
570 if (rcvd_len > pckt->len) {
571 LOG_ERR("space rcvd %d vs %d", rcvd_len, pckt->len);
572 return -EIO;
573 }
574
575 pckt->len = rcvd_len;
576 memcpy(pckt->buf, target_rx_mem, pckt->len);
577 memset(target_rx_mem, 0, pckt->len);
578
579 /* Only after data has been copied from SRAM, indicate channel
580 * is available for next packet
581 */
582 ESPI_OOB_REGS->RX_CTRL |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
583
584 return 0;
585 }
586 #endif /* CONFIG_ESPI_OOB_CHANNEL */
587
588 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_xec_flash_read(const struct device * dev,struct espi_flash_packet * pckt)589 static int espi_xec_flash_read(const struct device *dev,
590 struct espi_flash_packet *pckt)
591 {
592 int ret;
593 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
594 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
595 MCHP_ESPI_FC_STS_FAIL |
596 MCHP_ESPI_FC_STS_OVFL |
597 MCHP_ESPI_FC_STS_BADREQ;
598
599 LOG_DBG("%s", __func__);
600
601 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) {
602 LOG_ERR("Flash channel is disabled");
603 return -EIO;
604 }
605
606 if (pckt->len > CONFIG_ESPI_FLASH_BUFFER_SIZE) {
607 LOG_ERR("Invalid size request");
608 return -EINVAL;
609 }
610
611 ESPI_FC_REGS->FL_ADDR_MSW = 0;
612 ESPI_FC_REGS->FL_ADDR_LSW = pckt->flash_addr;
613 ESPI_FC_REGS->MEM_ADDR_MSW = 0;
614 ESPI_FC_REGS->MEM_ADDR_LSW = (uint32_t)&target_mem[0];
615 ESPI_FC_REGS->XFR_LEN = pckt->len;
616 ESPI_FC_REGS->CTRL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_RD0);
617 ESPI_FC_REGS->CTRL |= MCHP_ESPI_FC_CTRL_START;
618
619 /* Wait until ISR or timeout */
620 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
621 if (ret == -EAGAIN) {
622 LOG_ERR("%s timeout", __func__);
623 return -ETIMEDOUT;
624 }
625
626 if (ESPI_FC_REGS->STS & err_mask) {
627 LOG_ERR("%s error %x", __func__, err_mask);
628 ESPI_FC_REGS->STS = err_mask;
629 return -EIO;
630 }
631
632 memcpy(pckt->buf, target_mem, pckt->len);
633
634 return 0;
635 }
636
espi_xec_flash_write(const struct device * dev,struct espi_flash_packet * pckt)637 static int espi_xec_flash_write(const struct device *dev,
638 struct espi_flash_packet *pckt)
639 {
640 int ret;
641 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
642 MCHP_ESPI_FC_STS_OVRUN |
643 MCHP_ESPI_FC_STS_FAIL |
644 MCHP_ESPI_FC_STS_BADREQ;
645
646 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
647
648 LOG_DBG("%s", __func__);
649
650 if (sizeof(target_mem) < pckt->len) {
651 LOG_ERR("Packet length is too big");
652 return -ENOMEM;
653 }
654
655 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) {
656 LOG_ERR("Flash channel is disabled");
657 return -EIO;
658 }
659
660 if ((ESPI_FC_REGS->CFG & MCHP_ESPI_FC_CFG_BUSY)) {
661 LOG_ERR("Flash channel is busy");
662 return -EBUSY;
663 }
664
665 memcpy(target_mem, pckt->buf, pckt->len);
666
667 ESPI_FC_REGS->FL_ADDR_MSW = 0;
668 ESPI_FC_REGS->FL_ADDR_LSW = pckt->flash_addr;
669 ESPI_FC_REGS->MEM_ADDR_MSW = 0;
670 ESPI_FC_REGS->MEM_ADDR_LSW = (uint32_t)&target_mem[0];
671 ESPI_FC_REGS->XFR_LEN = pckt->len;
672 ESPI_FC_REGS->CTRL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_WR0);
673 ESPI_FC_REGS->CTRL |= MCHP_ESPI_FC_CTRL_START;
674
675 /* Wait until ISR or timeout */
676 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
677 if (ret == -EAGAIN) {
678 LOG_ERR("%s timeout", __func__);
679 return -ETIMEDOUT;
680 }
681
682 if (ESPI_FC_REGS->STS & err_mask) {
683 LOG_ERR("%s err: %x", __func__, err_mask);
684 ESPI_FC_REGS->STS = err_mask;
685 return -EIO;
686 }
687
688 return 0;
689 }
690
espi_xec_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)691 static int espi_xec_flash_erase(const struct device *dev,
692 struct espi_flash_packet *pckt)
693 {
694 int ret;
695 uint32_t status;
696 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
697 MCHP_ESPI_FC_STS_OVRUN |
698 MCHP_ESPI_FC_STS_FAIL |
699 MCHP_ESPI_FC_STS_BADREQ;
700
701 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
702
703 LOG_DBG("%s", __func__);
704
705 if (!(ESPI_FC_REGS->STS & MCHP_ESPI_FC_STS_CHAN_EN)) {
706 LOG_ERR("Flash channel is disabled");
707 return -EIO;
708 }
709
710 if ((ESPI_FC_REGS->CFG & MCHP_ESPI_FC_CFG_BUSY)) {
711 LOG_ERR("Flash channel is busy");
712 return -EBUSY;
713 }
714
715 /* Clear status register */
716 status = ESPI_FC_REGS->STS;
717 ESPI_FC_REGS->STS = status;
718
719 ESPI_FC_REGS->FL_ADDR_MSW = 0;
720 ESPI_FC_REGS->FL_ADDR_LSW = pckt->flash_addr;
721 ESPI_FC_REGS->XFR_LEN = ESPI_FLASH_ERASE_DUMMY;
722 ESPI_FC_REGS->CTRL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_ERS0);
723 ESPI_FC_REGS->CTRL |= MCHP_ESPI_FC_CTRL_START;
724
725 /* Wait until ISR or timeout */
726 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
727 if (ret == -EAGAIN) {
728 LOG_ERR("%s timeout", __func__);
729 return -ETIMEDOUT;
730 }
731
732 if (ESPI_FC_REGS->STS & err_mask) {
733 LOG_ERR("%s err: %x", __func__, err_mask);
734 ESPI_FC_REGS->STS = err_mask;
735 return -EIO;
736 }
737
738 return 0;
739 }
740 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
741
espi_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)742 static int espi_xec_manage_callback(const struct device *dev,
743 struct espi_callback *callback, bool set)
744 {
745 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
746
747 return espi_manage_callback(&data->callbacks, callback, set);
748 }
749
750 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
send_target_bootdone(const struct device * dev)751 static void send_target_bootdone(const struct device *dev)
752 {
753 int ret;
754 uint8_t boot_done;
755
756 ret = espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE,
757 &boot_done);
758 if (!ret && !boot_done) {
759 /* TARGET_BOOT_DONE & TARGET_LOAD_STS have to be sent together */
760 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
761 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, 1);
762 }
763 }
764 #endif
765
766 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_init_oob(const struct device * dev)767 static void espi_init_oob(const struct device *dev)
768 {
769 struct espi_xec_config *config =
770 (struct espi_xec_config *) (dev->config);
771
772 /* Enable OOB Tx/Rx interrupts */
773 MCHP_GIRQ_ENSET(config->bus_girq_id) = (MCHP_ESPI_OOB_UP_GIRQ_VAL |
774 MCHP_ESPI_OOB_DN_GIRQ_VAL);
775
776 ESPI_OOB_REGS->TX_ADDR_MSW = 0;
777 ESPI_OOB_REGS->RX_ADDR_MSW = 0;
778 ESPI_OOB_REGS->TX_ADDR_LSW = (uint32_t)&target_tx_mem[0];
779 ESPI_OOB_REGS->RX_ADDR_LSW = (uint32_t)&target_rx_mem[0];
780 ESPI_OOB_REGS->RX_LEN = 0x00FF0000;
781
782 /* Enable OOB Tx channel enable change status interrupt */
783 ESPI_OOB_REGS->TX_IEN |= MCHP_ESPI_OOB_TX_IEN_CHG_EN |
784 MCHP_ESPI_OOB_TX_IEN_DONE;
785
786 /* Enable Rx channel to receive data any time
787 * there are case where OOB is not initiated by a previous OOB Tx
788 */
789 ESPI_OOB_REGS->RX_IEN |= MCHP_ESPI_OOB_RX_IEN;
790 ESPI_OOB_REGS->RX_CTRL |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
791 }
792 #endif
793
794 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_init_flash(const struct device * dev)795 static void espi_init_flash(const struct device *dev)
796 {
797 struct espi_xec_config *config =
798 (struct espi_xec_config *)(dev->config);
799
800 LOG_DBG("%s", __func__);
801
802 /* Need to clear status done when ROM boots in MAF */
803 LOG_DBG("%s ESPI_FC_REGS->CFG %X", __func__, ESPI_FC_REGS->CFG);
804 ESPI_FC_REGS->STS = MCHP_ESPI_FC_STS_DONE;
805
806 /* Enable interrupts */
807 MCHP_GIRQ_ENSET(config->bus_girq_id) = BIT(MCHP_ESPI_FC_GIRQ_POS);
808 ESPI_FC_REGS->IEN |= MCHP_ESPI_FC_IEN_CHG_EN;
809 ESPI_FC_REGS->IEN |= MCHP_ESPI_FC_IEN_DONE;
810 }
811 #endif
812
espi_bus_init(const struct device * dev)813 static void espi_bus_init(const struct device *dev)
814 {
815 const struct espi_xec_config *config = dev->config;
816
817 /* Enable bus interrupts */
818 MCHP_GIRQ_ENSET(config->bus_girq_id) = MCHP_ESPI_ESPI_RST_GIRQ_VAL |
819 MCHP_ESPI_VW_EN_GIRQ_VAL | MCHP_ESPI_PC_GIRQ_VAL;
820 }
821
espi_config_vw_ocb(void)822 void espi_config_vw_ocb(void)
823 {
824 ESPI_SMVW_REG *reg = &(ESPI_S2M_VW_REGS->SMVW06);
825
826 /* Keep index bits [7:0] in initial 0h value (disabled state) */
827 mec_espi_smvw_index_set(reg, 0);
828 /* Set 01b (eSPI_RESET# domain) into bits [9:8] which frees the
829 * register from all except chip level resets and set initial state
830 * of VW wires as 1111b in bits [15:12].
831 */
832 mec_espi_msvw_stom_set(reg, VW_RST_SRC_ESPI_RESET, 0x1);
833 /* Set 4 SMVW SRC bits in bit positions [0], [8], [16] and [24] to
834 * initial value '1'.
835 */
836 mec_espi_smvw_set_all_bitmap(reg, 0xF);
837 /* Set 00b (eSPI_RESET# domain) into bits [9:8] while preserving
838 * the values in bits [15:12].
839 */
840 mec_espi_msvw_stom_set(reg, VW_RST_SRC_ESPI_RESET, 0x0);
841 /* Set INDEX field with OCB VW index */
842 mec_espi_smvw_index_set(reg, ESPI_OCB_VW_INDEX);
843 }
844
espi_rst_isr(const struct device * dev)845 static void espi_rst_isr(const struct device *dev)
846 {
847 uint8_t rst_sts;
848 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
849 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
850
851 rst_sts = ESPI_CAP_REGS->ERST_STS;
852
853 /* eSPI reset status register is clear on write register */
854 ESPI_CAP_REGS->ERST_STS = MCHP_ESPI_RST_ISTS;
855
856 if (rst_sts & MCHP_ESPI_RST_ISTS) {
857 if (rst_sts & MCHP_ESPI_RST_ISTS_PIN_RO_HI) {
858 evt.evt_data = 1;
859 } else {
860 evt.evt_data = 0;
861 }
862
863 espi_send_callbacks(&data->callbacks, dev, evt);
864 #ifdef CONFIG_ESPI_OOB_CHANNEL
865 espi_init_oob(dev);
866 #endif
867 #ifdef CONFIG_ESPI_FLASH_CHANNEL
868 espi_init_flash(dev);
869 #endif
870 espi_bus_init(dev);
871 }
872 }
873
874 /* Configure sub devices BAR address if not using default I/O based address
875 * then make its BAR valid.
876 * Refer to microchip eSPI I/O base addresses for default values
877 */
config_sub_devices(const struct device * dev)878 static void config_sub_devices(const struct device *dev)
879 {
880 #ifdef CONFIG_ESPI_PERIPHERAL_UART
881 /* eSPI logical UART is tied to corresponding physical UART
882 * Not all boards use same UART port for debug, hence needs to set
883 * eSPI host logical UART0 bar address based on configuration.
884 */
885 switch (CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING) {
886 case 0:
887 ESPI_EIO_BAR_REGS->EC_BAR_UART_0 = ESPI_XEC_UART0_BAR_ADDRESS |
888 MCHP_ESPI_IO_BAR_HOST_VALID;
889 break;
890 case 1:
891 ESPI_EIO_BAR_REGS->EC_BAR_UART_1 = ESPI_XEC_UART0_BAR_ADDRESS |
892 MCHP_ESPI_IO_BAR_HOST_VALID;
893 break;
894 case 2:
895 ESPI_EIO_BAR_REGS->EC_BAR_UART_2 = ESPI_XEC_UART0_BAR_ADDRESS |
896 MCHP_ESPI_IO_BAR_HOST_VALID;
897 break;
898 }
899 #endif
900 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
901 KBC_REGS->KBC_CTRL |= MCHP_KBC_CTRL_AUXH;
902 KBC_REGS->KBC_CTRL |= MCHP_KBC_CTRL_OBFEN;
903 /* This is the activate register, but the HAL has a funny name */
904 KBC_REGS->KBC_PORT92_EN = MCHP_KBC_PORT92_EN;
905 ESPI_EIO_BAR_REGS->EC_BAR_KBC = ESPI_XEC_KBC_BAR_ADDRESS |
906 MCHP_ESPI_IO_BAR_HOST_VALID;
907 #endif
908 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
909 ESPI_EIO_BAR_REGS->EC_BAR_ACPI_EC_0 |= MCHP_ESPI_IO_BAR_HOST_VALID;
910 ESPI_EIO_BAR_REGS->EC_BAR_MBOX = ESPI_XEC_MBOX_BAR_ADDRESS |
911 MCHP_ESPI_IO_BAR_HOST_VALID;
912 #endif
913 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
914 ESPI_EIO_BAR_REGS->EC_BAR_ACPI_EC_1 =
915 CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM |
916 MCHP_ESPI_IO_BAR_HOST_VALID;
917 ESPI_EIO_BAR_REGS->EC_BAR_MBOX = ESPI_XEC_MBOX_BAR_ADDRESS |
918 MCHP_ESPI_IO_BAR_HOST_VALID;
919 #endif
920
921 #ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
922 ESPI_EIO_BAR_REGS->EC_BAR_P80CAP_0 = ESPI_XEC_PORT80_BAR_ADDRESS |
923 MCHP_ESPI_IO_BAR_HOST_VALID;
924 PORT80_CAP0_REGS->ACTV = 1;
925 ESPI_EIO_BAR_REGS->EC_BAR_P80CAP_1 = ESPI_XEC_PORT81_BAR_ADDRESS |
926 MCHP_ESPI_IO_BAR_HOST_VALID;
927 PORT80_CAP1_REGS->ACTV = 1;
928 #endif
929 }
930
configure_sirq(void)931 static void configure_sirq(void)
932 {
933 #ifdef CONFIG_ESPI_PERIPHERAL_UART
934 switch (CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING) {
935 case ESPI_PERIPHERAL_UART_PORT0:
936 ESPI_SIRQ_REGS->UART_0_SIRQ = UART_DEFAULT_IRQ;
937 break;
938 case ESPI_PERIPHERAL_UART_PORT1:
939 ESPI_SIRQ_REGS->UART_1_SIRQ = UART_DEFAULT_IRQ;
940 break;
941 case ESPI_PERIPHERAL_UART_PORT2:
942 ESPI_SIRQ_REGS->UART_2_SIRQ = UART_DEFAULT_IRQ;
943 break;
944 }
945 #endif
946 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
947 ESPI_SIRQ_REGS->KBC_SIRQ_0 = 0x01;
948 ESPI_SIRQ_REGS->KBC_SIRQ_1 = 0x0C;
949 #endif
950 }
951
setup_espi_io_config(const struct device * dev,uint16_t host_address)952 static void setup_espi_io_config(const struct device *dev,
953 uint16_t host_address)
954 {
955 ESPI_EIO_BAR_REGS->EC_BAR_IOC = (host_address << 16) |
956 MCHP_ESPI_IO_BAR_HOST_VALID;
957
958 config_sub_devices(dev);
959 configure_sirq();
960
961 ESPI_PC_REGS->PC_STATUS = (MCHP_ESPI_PC_STS_EN_CHG |
962 MCHP_ESPI_PC_STS_BM_EN_CHG_POS);
963 ESPI_PC_REGS->PC_IEN |= MCHP_ESPI_PC_IEN_EN_CHG;
964 ESPI_CAP_REGS->PC_RDY = 1;
965 }
966
espi_pc_isr(const struct device * dev)967 static void espi_pc_isr(const struct device *dev)
968 {
969 uint32_t status = ESPI_PC_REGS->PC_STATUS;
970
971 if (status & MCHP_ESPI_PC_STS_EN_CHG) {
972 if (status & MCHP_ESPI_PC_STS_EN) {
973 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
974 }
975
976 ESPI_PC_REGS->PC_STATUS = MCHP_ESPI_PC_STS_EN_CHG;
977 }
978 }
979
espi_vwire_chanel_isr(const struct device * dev)980 static void espi_vwire_chanel_isr(const struct device *dev)
981 {
982 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
983 const struct espi_xec_config *config = dev->config;
984 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
985 .evt_details = ESPI_CHANNEL_VWIRE,
986 .evt_data = 0 };
987 uint32_t status;
988
989 status = ESPI_IO_VW_REGS->VW_EN_STS;
990
991 if (status & MCHP_ESPI_VW_EN_STS_RO) {
992 ESPI_IO_VW_REGS->VW_RDY = 1;
993 evt.evt_data = 1;
994 /* VW channel interrupt can disabled at this point */
995 MCHP_GIRQ_ENCLR(config->bus_girq_id) = MCHP_ESPI_VW_EN_GIRQ_VAL;
996 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
997 send_target_bootdone(dev);
998 #endif
999 }
1000
1001 espi_send_callbacks(&data->callbacks, dev, evt);
1002 }
1003
1004 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_oob_down_isr(const struct device * dev)1005 static void espi_oob_down_isr(const struct device *dev)
1006 {
1007 uint32_t status;
1008 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1009 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1010 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
1011 .evt_details = 0,
1012 .evt_data = 0 };
1013 #endif
1014
1015 status = ESPI_OOB_REGS->RX_STS;
1016
1017 LOG_DBG("%s %x", __func__, status);
1018 if (status & MCHP_ESPI_OOB_RX_STS_DONE) {
1019 /* Register is write-on-clear, ensure only 1 bit is affected */
1020 ESPI_OOB_REGS->RX_STS = MCHP_ESPI_OOB_RX_STS_DONE;
1021
1022 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1023 k_sem_give(&data->rx_lock);
1024 #else
1025 evt.evt_details = ESPI_OOB_REGS->RX_LEN & MCHP_ESPI_OOB_RX_LEN_MASK;
1026 espi_send_callbacks(&data->callbacks, dev, evt);
1027 #endif
1028 }
1029 }
1030
espi_oob_up_isr(const struct device * dev)1031 static void espi_oob_up_isr(const struct device *dev)
1032 {
1033 uint32_t status;
1034 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1035 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
1036 .evt_details = ESPI_CHANNEL_OOB,
1037 .evt_data = 0
1038 };
1039
1040 status = ESPI_OOB_REGS->TX_STS;
1041 LOG_DBG("%s sts:%x", __func__, status);
1042
1043 if (status & MCHP_ESPI_OOB_TX_STS_DONE) {
1044 /* Register is write-on-clear, ensure only 1 bit is affected */
1045 ESPI_OOB_REGS->TX_STS = MCHP_ESPI_OOB_TX_STS_DONE;
1046 k_sem_give(&data->tx_lock);
1047 }
1048
1049 if (status & MCHP_ESPI_OOB_TX_STS_CHG_EN) {
1050 if (status & MCHP_ESPI_OOB_TX_STS_CHEN) {
1051 espi_init_oob(dev);
1052 /* Indicate OOB channel is ready to eSPI host */
1053 ESPI_CAP_REGS->OOB_RDY = 1;
1054 evt.evt_data = 1;
1055 }
1056
1057 ESPI_OOB_REGS->TX_STS = MCHP_ESPI_OOB_TX_STS_CHG_EN;
1058 espi_send_callbacks(&data->callbacks, dev, evt);
1059 }
1060 }
1061 #endif
1062
1063 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_flash_isr(const struct device * dev)1064 static void espi_flash_isr(const struct device *dev)
1065 {
1066 uint32_t status;
1067 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1068 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
1069 .evt_details = ESPI_CHANNEL_FLASH,
1070 .evt_data = 0,
1071 };
1072
1073 status = ESPI_FC_REGS->STS;
1074 LOG_DBG("%s %x", __func__, status);
1075
1076 if (status & MCHP_ESPI_FC_STS_DONE) {
1077 /* Ensure to clear only relevant bit */
1078 ESPI_FC_REGS->STS = MCHP_ESPI_FC_STS_DONE;
1079
1080 k_sem_give(&data->flash_lock);
1081 }
1082
1083 if (status & MCHP_ESPI_FC_STS_CHAN_EN_CHG) {
1084 /* Ensure to clear only relevant bit */
1085 ESPI_FC_REGS->STS = MCHP_ESPI_FC_STS_CHAN_EN_CHG;
1086
1087 if (status & MCHP_ESPI_FC_STS_CHAN_EN) {
1088 espi_init_flash(dev);
1089 /* Indicate flash channel is ready to eSPI controller */
1090 ESPI_CAP_REGS->FC_RDY = MCHP_ESPI_FC_READY;
1091 evt.evt_data = 1;
1092 }
1093
1094 espi_send_callbacks(&data->callbacks, dev, evt);
1095 }
1096 }
1097 #endif
1098
vw_pltrst_isr(const struct device * dev)1099 static void vw_pltrst_isr(const struct device *dev)
1100 {
1101 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1102 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
1103 ESPI_VWIRE_SIGNAL_PLTRST, 0
1104 };
1105 uint8_t status = 0;
1106
1107 espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &status);
1108 if (status) {
1109 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
1110 }
1111
1112 evt.evt_data = status;
1113 espi_send_callbacks(&data->callbacks, dev, evt);
1114 }
1115
1116 /* Send callbacks if enabled and track eSPI host system state */
notify_system_state(const struct device * dev,enum espi_vwire_signal signal)1117 static void notify_system_state(const struct device *dev,
1118 enum espi_vwire_signal signal)
1119 {
1120 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1121 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1122 uint8_t status = 0;
1123
1124 espi_xec_receive_vwire(dev, signal, &status);
1125 evt.evt_details = signal;
1126 evt.evt_data = status;
1127 espi_send_callbacks(&data->callbacks, dev, evt);
1128 }
1129
notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)1130 static void notify_host_warning(const struct device *dev,
1131 enum espi_vwire_signal signal)
1132 {
1133 uint8_t status;
1134
1135 espi_xec_receive_vwire(dev, signal, &status);
1136
1137 if (!IS_ENABLED(CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE)) {
1138 struct espi_xec_data *data =
1139 (struct espi_xec_data *)(dev->data);
1140 struct espi_event evt = {ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1141
1142 evt.evt_details = signal;
1143 evt.evt_data = status;
1144 espi_send_callbacks(&data->callbacks, dev, evt);
1145 } else {
1146 k_busy_wait(ESPI_XEC_VWIRE_ACK_DELAY);
1147 /* Some flows are dependent on awareness of client's driver
1148 * about these warnings in such cases these automatic response
1149 * should not be enabled.
1150 */
1151 switch (signal) {
1152 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
1153 espi_xec_send_vwire(dev,
1154 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
1155 status);
1156 break;
1157 case ESPI_VWIRE_SIGNAL_SUS_WARN:
1158 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
1159 status);
1160 break;
1161 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
1162 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
1163 status);
1164 break;
1165 case ESPI_VWIRE_SIGNAL_DNX_WARN:
1166 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_DNX_ACK,
1167 status);
1168 break;
1169 default:
1170 break;
1171 }
1172 }
1173 }
1174
vw_slp3_isr(const struct device * dev)1175 static void vw_slp3_isr(const struct device *dev)
1176 {
1177 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S3);
1178 }
1179
vw_slp4_isr(const struct device * dev)1180 static void vw_slp4_isr(const struct device *dev)
1181 {
1182 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S4);
1183 }
1184
vw_slp5_isr(const struct device * dev)1185 static void vw_slp5_isr(const struct device *dev)
1186 {
1187 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S5);
1188 }
1189
vw_host_rst_warn_isr(const struct device * dev)1190 static void vw_host_rst_warn_isr(const struct device *dev)
1191 {
1192 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_HOST_RST_WARN);
1193 }
1194
vw_sus_warn_isr(const struct device * dev)1195 static void vw_sus_warn_isr(const struct device *dev)
1196 {
1197 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_SUS_WARN);
1198 /* Configure spare VW register SMVW06 to VW index 50h. As per
1199 * per microchip recommendation, spare VW register should be
1200 * configured between TARGET_BOOT_LOAD_DONE = 1 VW event and
1201 * point where SUS_ACK=1 VW is sent to SOC.
1202 */
1203 espi_config_vw_ocb();
1204 }
1205
vw_oob_rst_isr(const struct device * dev)1206 static void vw_oob_rst_isr(const struct device *dev)
1207 {
1208 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_OOB_RST_WARN);
1209 }
1210
vw_sus_pwrdn_ack_isr(const struct device * dev)1211 static void vw_sus_pwrdn_ack_isr(const struct device *dev)
1212 {
1213 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK);
1214 }
1215
vw_sus_slp_a_isr(const struct device * dev)1216 static void vw_sus_slp_a_isr(const struct device *dev)
1217 {
1218 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_A);
1219 }
1220
ibf_isr(const struct device * dev)1221 static void ibf_isr(const struct device *dev)
1222 {
1223 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1224 struct espi_event evt = { ESPI_BUS_PERIPHERAL_NOTIFICATION,
1225 ESPI_PERIPHERAL_HOST_IO, ESPI_PERIPHERAL_NODATA
1226 };
1227
1228 espi_send_callbacks(&data->callbacks, dev, evt);
1229 }
1230
1231 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
ibf_pvt_isr(const struct device * dev)1232 static void ibf_pvt_isr(const struct device *dev)
1233 {
1234 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1235 struct espi_event evt = {
1236 .evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1237 .evt_details = ESPI_PERIPHERAL_HOST_IO_PVT,
1238 .evt_data = ESPI_PERIPHERAL_NODATA
1239 };
1240
1241 espi_send_callbacks(&data->callbacks, dev, evt);
1242 }
1243 #endif
1244
ibf_kbc_isr(const struct device * dev)1245 static void ibf_kbc_isr(const struct device *dev)
1246 {
1247 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1248
1249 /* The high byte contains information from the host,
1250 * and the lower byte specifies if the host sent
1251 * a command or data. 1 = Command.
1252 */
1253 uint32_t isr_data = ((KBC_REGS->EC_DATA & 0xFF) << E8042_ISR_DATA_POS) |
1254 ((KBC_REGS->EC_KBC_STS & MCHP_KBC_STS_CD) <<
1255 E8042_ISR_CMD_DATA_POS);
1256
1257 struct espi_event evt = {
1258 .evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1259 .evt_details = ESPI_PERIPHERAL_8042_KBC,
1260 .evt_data = isr_data
1261 };
1262
1263 espi_send_callbacks(&data->callbacks, dev, evt);
1264 }
1265
port80_isr(const struct device * dev)1266 static void port80_isr(const struct device *dev)
1267 {
1268 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1269 struct espi_event evt = { ESPI_BUS_PERIPHERAL_NOTIFICATION,
1270 (ESPI_PERIPHERAL_INDEX_0 << 16) | ESPI_PERIPHERAL_DEBUG_PORT80,
1271 ESPI_PERIPHERAL_NODATA
1272 };
1273
1274 evt.evt_data = PORT80_CAP0_REGS->EC_DATA;
1275 espi_send_callbacks(&data->callbacks, dev, evt);
1276 }
1277
port81_isr(const struct device * dev)1278 static void port81_isr(const struct device *dev)
1279 {
1280 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1281 struct espi_event evt = { ESPI_BUS_PERIPHERAL_NOTIFICATION,
1282 (ESPI_PERIPHERAL_INDEX_1 << 16) | ESPI_PERIPHERAL_DEBUG_PORT80,
1283 ESPI_PERIPHERAL_NODATA
1284 };
1285
1286 evt.evt_data = PORT80_CAP1_REGS->EC_DATA;
1287 espi_send_callbacks(&data->callbacks, dev, evt);
1288 }
1289
1290 const struct espi_isr espi_bus_isr[] = {
1291 {MCHP_ESPI_PC_GIRQ_VAL, espi_pc_isr},
1292 #ifdef CONFIG_ESPI_OOB_CHANNEL
1293 {MCHP_ESPI_OOB_UP_GIRQ_VAL, espi_oob_up_isr},
1294 {MCHP_ESPI_OOB_DN_GIRQ_VAL, espi_oob_down_isr},
1295 #endif
1296 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1297 {MCHP_ESPI_FC_GIRQ_VAL, espi_flash_isr},
1298 #endif
1299 {MCHP_ESPI_ESPI_RST_GIRQ_VAL, espi_rst_isr},
1300 {MCHP_ESPI_VW_EN_GIRQ_VAL, espi_vwire_chanel_isr},
1301 };
1302
1303 uint8_t vw_wires_int_en[] = {
1304 ESPI_VWIRE_SIGNAL_SLP_S3,
1305 ESPI_VWIRE_SIGNAL_SLP_S4,
1306 ESPI_VWIRE_SIGNAL_SLP_S5,
1307 ESPI_VWIRE_SIGNAL_PLTRST,
1308 ESPI_VWIRE_SIGNAL_OOB_RST_WARN,
1309 ESPI_VWIRE_SIGNAL_HOST_RST_WARN,
1310 ESPI_VWIRE_SIGNAL_SUS_WARN,
1311 ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK,
1312 ESPI_VWIRE_SIGNAL_DNX_WARN,
1313 };
1314
1315 const struct espi_isr m2s_vwires_isr[] = {
1316 {MEC_ESPI_MSVW00_SRC0_VAL, vw_slp3_isr},
1317 {MEC_ESPI_MSVW00_SRC1_VAL, vw_slp4_isr},
1318 {MEC_ESPI_MSVW00_SRC2_VAL, vw_slp5_isr},
1319 {MEC_ESPI_MSVW01_SRC1_VAL, vw_pltrst_isr},
1320 {MEC_ESPI_MSVW01_SRC2_VAL, vw_oob_rst_isr},
1321 {MEC_ESPI_MSVW02_SRC0_VAL, vw_host_rst_warn_isr},
1322 {MEC_ESPI_MSVW03_SRC0_VAL, vw_sus_warn_isr},
1323 {MEC_ESPI_MSVW03_SRC1_VAL, vw_sus_pwrdn_ack_isr},
1324 {MEC_ESPI_MSVW03_SRC3_VAL, vw_sus_slp_a_isr},
1325 };
1326
1327 const struct espi_isr peripherals_isr[] = {
1328 {MCHP_ACPI_EC_0_IBF_GIRQ, ibf_isr},
1329 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
1330 {MCHP_ACPI_EC_1_IBF_GIRQ, ibf_pvt_isr},
1331 #endif
1332 {MCHP_KBC_IBF_GIRQ, ibf_kbc_isr},
1333 {MCHP_PORT80_DEBUG0_GIRQ_VAL, port80_isr},
1334 {MCHP_PORT80_DEBUG1_GIRQ_VAL, port81_isr},
1335 };
1336
1337 static uint8_t bus_isr_cnt = sizeof(espi_bus_isr) / sizeof(struct espi_isr);
1338 static uint8_t m2s_vwires_isr_cnt =
1339 sizeof(m2s_vwires_isr) / sizeof(struct espi_isr);
1340 static uint8_t periph_isr_cnt = sizeof(peripherals_isr) / sizeof(struct espi_isr);
1341
espi_xec_bus_isr(const struct device * dev)1342 static void espi_xec_bus_isr(const struct device *dev)
1343 {
1344 const struct espi_xec_config *config = dev->config;
1345 uint32_t girq_result;
1346
1347 girq_result = MCHP_GIRQ_RESULT(config->bus_girq_id);
1348
1349 for (int i = 0; i < bus_isr_cnt; i++) {
1350 struct espi_isr entry = espi_bus_isr[i];
1351
1352 if (girq_result & entry.girq_bit) {
1353 if (entry.the_isr != NULL) {
1354 entry.the_isr(dev);
1355 }
1356 }
1357 }
1358
1359 REG32(MCHP_GIRQ_SRC_ADDR(config->bus_girq_id)) = girq_result;
1360 }
1361
espi_xec_vw_isr(const struct device * dev)1362 static void espi_xec_vw_isr(const struct device *dev)
1363 {
1364 const struct espi_xec_config *config = dev->config;
1365 uint32_t girq_result;
1366
1367 girq_result = MCHP_GIRQ_RESULT(config->vw_girq_ids[0]);
1368 MCHP_GIRQ_SRC(config->vw_girq_ids[0]) = girq_result;
1369
1370 for (int i = 0; i < m2s_vwires_isr_cnt; i++) {
1371 struct espi_isr entry = m2s_vwires_isr[i];
1372
1373 if (girq_result & entry.girq_bit) {
1374 if (entry.the_isr != NULL) {
1375 entry.the_isr(dev);
1376 }
1377 }
1378 }
1379 }
1380
1381 #if DT_INST_PROP_HAS_IDX(0, vw_girqs, 1)
vw_sus_dnx_warn_isr(const struct device * dev)1382 static void vw_sus_dnx_warn_isr(const struct device *dev)
1383 {
1384 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_DNX_WARN);
1385 }
1386
1387 const struct espi_isr m2s_vwires_ext_isr[] = {
1388 {MEC_ESPI_MSVW08_SRC1_VAL, vw_sus_dnx_warn_isr}
1389 };
1390
espi_xec_vw_ext_isr(const struct device * dev)1391 static void espi_xec_vw_ext_isr(const struct device *dev)
1392 {
1393 const struct espi_xec_config *config = dev->config;
1394 uint32_t girq_result;
1395
1396 girq_result = MCHP_GIRQ_RESULT(config->vw_girq_ids[1]);
1397 MCHP_GIRQ_SRC(config->vw_girq_ids[1]) = girq_result;
1398
1399 for (int i = 0; i < ARRAY_SIZE(m2s_vwires_ext_isr); i++) {
1400 struct espi_isr entry = m2s_vwires_ext_isr[i];
1401
1402 if (girq_result & entry.girq_bit) {
1403 if (entry.the_isr != NULL) {
1404 entry.the_isr(dev);
1405 }
1406 }
1407 }
1408 }
1409 #endif
1410
espi_xec_periph_isr(const struct device * dev)1411 static void espi_xec_periph_isr(const struct device *dev)
1412 {
1413 const struct espi_xec_config *config = dev->config;
1414 uint32_t girq_result;
1415
1416 girq_result = MCHP_GIRQ_RESULT(config->pc_girq_id);
1417
1418 for (int i = 0; i < periph_isr_cnt; i++) {
1419 struct espi_isr entry = peripherals_isr[i];
1420
1421 if (girq_result & entry.girq_bit) {
1422 if (entry.the_isr != NULL) {
1423 entry.the_isr(dev);
1424 }
1425 }
1426 }
1427
1428 REG32(MCHP_GIRQ_SRC_ADDR(config->pc_girq_id)) = girq_result;
1429 }
1430
1431 static int espi_xec_init(const struct device *dev);
1432
1433 static DEVICE_API(espi, espi_xec_driver_api) = {
1434 .config = espi_xec_configure,
1435 .get_channel_status = espi_xec_channel_ready,
1436 .send_vwire = espi_xec_send_vwire,
1437 .receive_vwire = espi_xec_receive_vwire,
1438 #ifdef CONFIG_ESPI_OOB_CHANNEL
1439 .send_oob = espi_xec_send_oob,
1440 .receive_oob = espi_xec_receive_oob,
1441 #endif
1442 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1443 .flash_read = espi_xec_flash_read,
1444 .flash_write = espi_xec_flash_write,
1445 .flash_erase = espi_xec_flash_erase,
1446 #endif
1447 .manage_callback = espi_xec_manage_callback,
1448 .read_lpc_request = espi_xec_read_lpc_request,
1449 .write_lpc_request = espi_xec_write_lpc_request,
1450 };
1451
1452 static struct espi_xec_data espi_xec_data;
1453
1454 /* pin control structure(s) */
1455 PINCTRL_DT_INST_DEFINE(0);
1456
1457 static const struct espi_xec_config espi_xec_config = {
1458 .base_addr = DT_INST_REG_ADDR(0),
1459 .bus_girq_id = DT_INST_PROP(0, io_girq),
1460 .vw_girq_ids[0] = DT_INST_PROP_BY_IDX(0, vw_girqs, 0),
1461 .vw_girq_ids[1] = DT_INST_PROP_BY_IDX(0, vw_girqs, 1),
1462 .pc_girq_id = DT_INST_PROP(0, pc_girq),
1463 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1464 };
1465
1466 DEVICE_DT_INST_DEFINE(0, &espi_xec_init, NULL,
1467 &espi_xec_data, &espi_xec_config,
1468 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1469 &espi_xec_driver_api);
1470
espi_xec_init(const struct device * dev)1471 static int espi_xec_init(const struct device *dev)
1472 {
1473 const struct espi_xec_config *config = dev->config;
1474 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
1475 int ret;
1476
1477 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1478 if (ret != 0) {
1479 LOG_ERR("XEC eSPI pinctrl setup failed (%d)", ret);
1480 return ret;
1481 }
1482
1483 /* Configure eSPI_PLTRST# to cause nSIO_RESET reset */
1484 PCR_REGS->PWR_RST_CTRL = MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST;
1485 ESPI_CAP_REGS->PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_IS_VW;
1486
1487 /* Configure the channels and its capabilities based on build config */
1488 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP;
1489 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_PC_SUPP;
1490
1491 /* Max VW count is 12 pairs */
1492 ESPI_CAP_REGS->VW_CAP = ESPI_NUM_SMVW;
1493 ESPI_CAP_REGS->PC_CAP |= MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64;
1494
1495 #ifdef CONFIG_ESPI_OOB_CHANNEL
1496 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1497 ESPI_CAP_REGS->OOB_CAP |= MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73;
1498
1499 k_sem_init(&data->tx_lock, 0, 1);
1500 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1501 k_sem_init(&data->rx_lock, 0, 1);
1502 #endif /* CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC */
1503 #else
1504 ESPI_CAP_REGS->GLB_CAP0 &= ~MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1505 #endif
1506
1507 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1508 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
1509 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64;
1510 ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF;
1511 ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_MAX_RD_SZ_64;
1512
1513 k_sem_init(&data->flash_lock, 0, 1);
1514 #else
1515 ESPI_CAP_REGS->GLB_CAP0 &= ~MCHP_ESPI_GBL_CAP0_FC_SUPP;
1516 #endif
1517
1518 /* Clear reset interrupt status and enable interrupts */
1519 ESPI_CAP_REGS->ERST_STS = MCHP_ESPI_RST_ISTS;
1520 ESPI_CAP_REGS->ERST_IEN |= MCHP_ESPI_RST_IEN;
1521 ESPI_PC_REGS->PC_STATUS = MCHP_ESPI_PC_STS_EN_CHG;
1522 ESPI_PC_REGS->PC_IEN |= MCHP_ESPI_PC_IEN_EN_CHG;
1523
1524 /* Enable VWires interrupts */
1525 for (int i = 0; i < sizeof(vw_wires_int_en); i++) {
1526 uint8_t signal = vw_wires_int_en[i];
1527 struct xec_signal signal_info = vw_tbl[signal];
1528 uint8_t xec_id = signal_info.xec_reg_idx;
1529 ESPI_MSVW_REG *reg = &(ESPI_M2S_VW_REGS->MSVW00) + xec_id;
1530
1531 mec_espi_msvw_irq_sel_set(reg, signal_info.bit,
1532 MSVW_IRQ_SEL_EDGE_BOTH);
1533 }
1534
1535 /* Enable interrupts for each logical channel enable assertion */
1536 MCHP_GIRQ_ENSET(config->bus_girq_id) = MCHP_ESPI_ESPI_RST_GIRQ_VAL |
1537 MCHP_ESPI_VW_EN_GIRQ_VAL | MCHP_ESPI_PC_GIRQ_VAL;
1538
1539 #ifdef CONFIG_ESPI_OOB_CHANNEL
1540 espi_init_oob(dev);
1541 #endif
1542 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1543 espi_init_flash(dev);
1544 #endif
1545 /* Enable aggregated block interrupts for VWires */
1546 MCHP_GIRQ_ENSET(config->vw_girq_ids[0]) = MEC_ESPI_MSVW00_SRC0_VAL |
1547 MEC_ESPI_MSVW00_SRC1_VAL | MEC_ESPI_MSVW00_SRC2_VAL |
1548 MEC_ESPI_MSVW01_SRC1_VAL | MEC_ESPI_MSVW01_SRC2_VAL |
1549 MEC_ESPI_MSVW02_SRC0_VAL | MEC_ESPI_MSVW03_SRC0_VAL;
1550
1551 /* Enable aggregated block interrupts for peripherals supported */
1552 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
1553 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_KBC_IBF_GIRQ;
1554 #endif
1555 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
1556 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_ACPI_EC_0_IBF_GIRQ;
1557 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_ACPI_EC_2_IBF_GIRQ;
1558 #endif
1559 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
1560 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_ACPI_EC_1_IBF_GIRQ;
1561 #endif
1562 #ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
1563 MCHP_GIRQ_ENSET(config->pc_girq_id) = MCHP_PORT80_DEBUG0_GIRQ_VAL |
1564 MCHP_PORT80_DEBUG1_GIRQ_VAL;
1565 #endif
1566 /* Enable aggregated interrupt block for eSPI bus events */
1567 MCHP_GIRQ_BLK_SETEN(config->bus_girq_id);
1568 IRQ_CONNECT(DT_INST_IRQN(0),
1569 DT_INST_IRQ(0, priority),
1570 espi_xec_bus_isr,
1571 DEVICE_DT_INST_GET(0), 0);
1572 irq_enable(DT_INST_IRQN(0));
1573
1574 /* Enable aggregated interrupt block for eSPI VWire events */
1575 MCHP_GIRQ_BLK_SETEN(config->vw_girq_ids[0]);
1576 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 1, irq),
1577 DT_INST_IRQ_BY_IDX(0, 1, priority),
1578 espi_xec_vw_isr,
1579 DEVICE_DT_INST_GET(0), 0);
1580 irq_enable(DT_INST_IRQ_BY_IDX(0, 1, irq));
1581
1582 /* Enable aggregated interrupt block for eSPI peripheral channel */
1583 MCHP_GIRQ_BLK_SETEN(config->pc_girq_id);
1584 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 2, irq),
1585 DT_INST_IRQ_BY_IDX(0, 2, priority),
1586 espi_xec_periph_isr,
1587 DEVICE_DT_INST_GET(0), 0);
1588 irq_enable(DT_INST_IRQ_BY_IDX(0, 2, irq));
1589
1590 #if DT_INST_PROP_HAS_IDX(0, vw_girqs, 1)
1591 MCHP_GIRQ_ENSET(config->vw_girq_ids[1]) = MEC_ESPI_MSVW08_SRC1_VAL;
1592 MCHP_GIRQ_BLK_SETEN(config->vw_girq_ids[1]);
1593 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 3, irq),
1594 DT_INST_IRQ_BY_IDX(0, 3, priority),
1595 espi_xec_vw_ext_isr,
1596 DEVICE_DT_INST_GET(0), 0);
1597 irq_enable(DT_INST_IRQ_BY_IDX(0, 3, irq));
1598 #endif
1599
1600 return 0;
1601 }
1602
