1 /*
2  * Copyright (c) 2020 Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/arch/arm/arch.h>
8 #include <zephyr/kernel.h>
9 #include <zephyr/sys_clock.h>
10 #include <zephyr/timing/timing.h>
11 #include <soc.h>
12 
soc_timing_init(void)13 void soc_timing_init(void)
14 {
15 	/* Setup counter */
16 	B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE |
17 			     MCHP_BTMR_CTRL_AUTO_RESTART |
18 			     MCHP_BTMR_CTRL_COUNT_UP;
19 
20 	B32TMR1_REGS->PRLD = 0; /* Preload */
21 	B32TMR1_REGS->CNT = 0; /* Counter value */
22 
23 	B32TMR1_REGS->IEN = 0; /* Disable interrupt */
24 	B32TMR1_REGS->STS = 1; /* Clear interrupt */
25 }
26 
soc_timing_start(void)27 void soc_timing_start(void)
28 {
29 	B32TMR1_REGS->CTRL |= MCHP_BTMR_CTRL_START;
30 }
31 
soc_timing_stop(void)32 void soc_timing_stop(void)
33 {
34 	B32TMR1_REGS->CTRL &= ~MCHP_BTMR_CTRL_START;
35 }
36 
soc_timing_counter_get(void)37 timing_t soc_timing_counter_get(void)
38 {
39 	return B32TMR1_REGS->CNT;
40 }
41 
soc_timing_cycles_get(volatile timing_t * const start,volatile timing_t * const end)42 uint64_t soc_timing_cycles_get(volatile timing_t *const start,
43 			       volatile timing_t *const end)
44 {
45 	return (*end - *start);
46 }
47 
soc_timing_freq_get(void)48 uint64_t soc_timing_freq_get(void)
49 {
50 	return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
51 }
52 
soc_timing_cycles_to_ns(uint64_t cycles)53 uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
54 {
55 	return (cycles) * (NSEC_PER_SEC) / (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
56 }
57 
soc_timing_cycles_to_ns_avg(uint64_t cycles,uint32_t count)58 uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
59 {
60 	return (uint32_t)soc_timing_cycles_to_ns(cycles) / count;
61 }
62 
soc_timing_freq_get_mhz(void)63 uint32_t soc_timing_freq_get_mhz(void)
64 {
65 	return (uint32_t)(soc_timing_freq_get() / 1000000);
66 }
67