Home
last modified time | relevance | path

Searched refs:STM32_SRC_PLLCLK (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f10x_clock.h17 #define STM32_SRC_PLL2CLK (STM32_SRC_PLLCLK + 1)
Dstm32f1_clock.h29 #define STM32_SRC_PLLCLK (STM32_SRC_EXT_HSE + 1) macro
Dstm32f0_clock.h31 #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) macro
Dstm32f3_clock.h32 #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) macro
/Zephyr-latest/dts/arm/st/f0/
Dstm32f072.dtsi30 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
Dstm32f070.dtsi48 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
Dstm32f042.dtsi77 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.c189 #if defined(STM32_SRC_PLLCLK) in enabled_clock()
190 case STM32_SRC_PLLCLK: in enabled_clock()
403 #if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL) in stm32_clock_control_get_subsys_rate()
404 case STM32_SRC_PLLCLK: in stm32_clock_control_get_subsys_rate()