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Searched refs:STM32_SRC_PLL2_Q (Results 1 – 13 of 13) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h30 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
31 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
Dstm32h7_clock.h29 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
30 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
Dstm32u5_clock.h34 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
35 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
Dstm32h5_clock.h33 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
34 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
/Zephyr-latest/boards/st/stm32h735g_disco/
Dstm32h735g_disco.dts214 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
226 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
238 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-latest/boards/st/stm32h745i_disco/
Dstm32h745i_disco_stm32h745xx_m7.dts227 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
239 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-latest/boards/witte/linum/
Dlinum.dts217 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
225 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-latest/boards/st/nucleo_h723zg/
Dnucleo_h723zg.dts210 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c136 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || in enabled_clock()
309 case STM32_SRC_PLL2_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c142 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || in enabled_clock()
325 case STM32_SRC_PLL2_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c374 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
592 case STM32_SRC_PLL2_Q:
/Zephyr-latest/boards/st/nucleo_h753zi/
Dnucleo_h753zi.dts161 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-latest/boards/st/nucleo_h743zi/
Dnucleo_h743zi.dts184 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;