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Searched refs:STM32_SRC_HSE (Results 1 – 25 of 33) sorted by relevance

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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32l1_clock.h26 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
27 #define STM32_SRC_HSI (STM32_SRC_HSE + 1)
Dstm32f1_clock.h27 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) macro
28 #define STM32_SRC_EXT_HSE (STM32_SRC_HSE + 1)
Dstm32l0_clock.h28 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
29 #define STM32_SRC_HSI (STM32_SRC_HSE + 1)
Dstm32f4_clock.h32 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) macro
34 #define STM32_SRC_PLL_P (STM32_SRC_HSE + 1)
Dstm32c0_clock.h28 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) macro
30 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
Dstm32wb_clock.h32 #define STM32_SRC_HSE (STM32_SRC_MSI + 1) macro
34 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
Dstm32u0_clock.h31 #define STM32_SRC_HSE (STM32_SRC_MSI + 1) macro
33 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
Dstm32g4_clock.h32 #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1) macro
33 #define STM32_SRC_MSI (STM32_SRC_HSE + 1)
Dstm32g0_clock.h30 #define STM32_SRC_HSE (STM32_SRC_MSI + 1) macro
32 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
Dstm32wba_clock.h19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
20 #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
Dstm32f7_clock.h33 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) macro
35 #define STM32_SRC_PLL_P (STM32_SRC_HSE + 1)
Dstm32h7rs_clock.h20 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
21 #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
Dstm32h7_clock.h20 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
21 #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
Dstm32u5_clock.h19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
20 #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
Dstm32h5_clock.h19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
20 #define STM32_SRC_CSI (STM32_SRC_HSE + 1)
Dstm32n6_clock.h18 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) macro
19 #define STM32_SRC_HSI (STM32_SRC_HSE + 1)
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f429zi.overlay18 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(MCO_SEL_HSE)>;
27 clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO_SEL_HSE)>;
Dstm32f746g_disco.overlay30 clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO2_SEL_HSE)>;
Dnucleo_f446ze.overlay16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
Dnucleo_f411re.overlay21 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_per_ck_hse.overlay19 clocks = <&rcc STM32_SRC_HSE CKPER_SEL(2)>;
/Zephyr-latest/dts/arm/st/h7/
Dstm32h747.dtsi21 <&rcc STM32_SRC_HSE NO_SEL>,
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.c131 #if defined(STM32_SRC_HSE) in enabled_clock()
132 case STM32_SRC_HSE: in enabled_clock()
467 #if defined(STM32_SRC_HSE) in stm32_clock_control_get_subsys_rate()
468 case STM32_SRC_HSE: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_wba.c52 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || in enabled_clock()
263 case STM32_SRC_HSE: in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c98 } else if (perclk_dt_domain_clk == STM32_SRC_HSE) { in ZTEST()

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