Home
last modified time | relevance | path

Searched refs:STM32_PLL_SRC_HSI (Results 1 – 17 of 17) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f0_f3.c59 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock()
70 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock()
119 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllout_frequency()
130 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllout_frequency()
Dclock_stm32g4.c28 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source()
44 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
Dclock_stm32g0_u0.c29 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source()
45 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
Dclock_stm32l4_l5_wb_wl.c36 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source()
54 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
Dclock_stm32l0_l1.c35 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source()
51 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
Dclock_stm32f1.c65 if (!IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock()
98 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock()
Dclock_stm32f2_f4_f7.c27 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source()
43 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
Dclock_stm32_ll_wba.c139 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()
153 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc()
394 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()
Dclock_stm32_ll_h5.c52 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
457 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()
635 if (IS_ENABLED(STM32_PLL_SRC_HSI) || in set_up_fixed_clock_sources()
Dclock_stm32_ll_h7.c57 #if defined(STM32_PLL_SRC_HSI)
686 if (IS_ENABLED(STM32_PLL_SRC_HSI) || IS_ENABLED(STM32_PLL2_SRC_HSI) ||
823 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
Dclock_stm32_ll_u5.c57 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
538 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/
Dtest_stm32_clock_configuration.c59 #elif STM32_PLL_SRC_HSI in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/
Dtest_stm32_clock_configuration.c64 #elif STM32_PLL_SRC_HSI in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/
Dtest_stm32_clock_configuration.c64 #elif STM32_PLL_SRC_HSI in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
Dtest_stm32_clock_configuration.c64 #elif STM32_PLL_SRC_HSI in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c73 #elif STM32_PLL_SRC_HSI in ZTEST()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h266 #define STM32_PLL_SRC_HSI 1 macro