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Searched refs:READ_BIT (Results 1 – 18 of 18) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c94 if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { in ZTEST()
114 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled"); in ZTEST()
116 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled"); in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
Dtest_stm32_clock_configuration.c85 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS is not enabled"); in ZTEST()
87 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS unexpectedly enabled"); in ZTEST()
/Zephyr-latest/soc/st/stm32/stm32h7x/
Dsoc_m7.c33 if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { in stm32h7_m4_wakeup()
/Zephyr-latest/drivers/sensor/st/stm32_digi_temp/
Dstm32_digi_temp.c76 while (READ_BIT(dts->SR, DTS_SR_TS1_RDY) == 0) { in stm32_digi_temp_sample_fetch()
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac.c375 READ_BIT(tcq_config->rx_q_ddma_en, q_idx)) | in dwxgmac_dma_mtl_init()
388 READ_BIT(tcq_config->tsf_en, q_idx)); in dwxgmac_dma_mtl_init()
400 READ_BIT(tcq_config->hfc_en, q_idx)) | in dwxgmac_dma_mtl_init()
402 READ_BIT(tcq_config->cs_err_pkt_drop_dis, q_idx)) | in dwxgmac_dma_mtl_init()
404 READ_BIT(tcq_config->rsf_en, q_idx)) | in dwxgmac_dma_mtl_init()
406 READ_BIT(tcq_config->fep_en, q_idx)) | in dwxgmac_dma_mtl_init()
408 READ_BIT(tcq_config->fup_en, q_idx)) | in dwxgmac_dma_mtl_init()
Deth_dwc_xgmac_priv.h21 #define READ_BIT(var, bit) ((var >> bit) & 1u) macro
/Zephyr-latest/drivers/flash/
Dflash_stm32g4x.c369 if (READ_BIT(FLASH->OPTR, FLASH_STM32_DBANK) == 0U) { in flash_stm32_check_configuration()
Dflash_stm32wb0x.c76 READ_BIT(FLASH->SIZE, FLASH_FLASH_SIZE_FLASH_SIZE) + 1; in get_flash_size_in_bytes()
Dflash_stm32h7x.c292 bank_swap = (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == FLASH_OPTCR_SWAP_BANK);
Dflash_stm32_qspi.c470 return READ_BIT(dev_data->hqspi.Instance->CCR, QUADSPI_CCR_FMODE) == QUADSPI_CCR_FMODE; in stm32_qspi_is_memory_mapped()
Dflash_stm32_xspi.c953 return ((READ_BIT(dev_data->hxspi.Instance->CR, in stm32_xspi_is_memorymap()
Dflash_stm32_ospi.c1121 return ((READ_BIT(dev_data->hospi.Instance->CR, in stm32_ospi_is_memorymap()
/Zephyr-latest/drivers/counter/
Dcounter_ll_stm32_timer.c395 apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV)); in counter_stm32_get_tim_clk()
403 apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV)); in counter_stm32_get_tim_clk()
/Zephyr-latest/drivers/pwm/
Dpwm_stm32.c243 apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV)); in get_tim_clk()
252 apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV)); in get_tim_clk()
/Zephyr-latest/drivers/rtc/
Drtc_ll_stm32.c1026 bool calp_enabled = READ_BIT(calr, RTC_CALR_CALP); in rtc_stm32_get_calibration()
1027 uint32_t calm = READ_BIT(calr, RTC_CALR_CALM); in rtc_stm32_get_calibration()
/Zephyr-latest/drivers/entropy/
Dentropy_stm32.c183 cur_nist_cfg = READ_BIT(rng->CR, in configure_rng()
/Zephyr-latest/drivers/i3c/
Di3c_stm32.c1275 msgs[i].num_xfer = READ_BIT(data->status_fifo[i], I3C_SR_XDCNT); in i3c_stm32_i3c_transfer()
/Zephyr-latest/doc/releases/
Drelease-notes-2.5.rst1183 * :github:`31028` - Cannot READ_BIT(RCC->CR, RCC_CR_PLL1RDY) on STM32H743 based board