Searched refs:P9 (Results 1 – 18 of 18) sorted by relevance
112 * LED1 (green) = P9.0113 * LED2 (green) = P9.1114 * LED3 (green) = P9.2115 * LED4 (green) = P9.3
83 #define P9 CYHAL_PORT_9 macro
35 programmer is attached to the P9 programming header.
91 <9 0 &gpio0 9 0>, /* P9 */
78 <9 0 &gpio0 4 0>, /* P9, P0.04/AIN0 */
72 <9 0 &gpio0 4 0>, /* P9, P0.04/AIN0 */
92 <9 0 &gpio0 10 0>, /* P9, LED Col 7 */
189 SWD port. SWD debug can be accessed through the Cortex 10-pin connector, P9.200 be connected to the standard 2*5 pin debug connector (P9) using an
104 * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
105 | P9 | GPIO_AD_B1_03 | D9 | GPIO1_IO19 | | |
102 * configuration to pass PWM signal on pis 0 and 1. First valid config is P9.2.
85 | P9 | GPIO_B0_00 | D9 | GPIO2_IO00 | | |
9 RISC-V architecture and FPGA technology. It has the same P8 & P9 cape header pins as BeagleBone
117 Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector.
355 programmer is attached to the P9 programming header.
281 P3/P9 Digital I/O
275 The P9 pins are available at J2. Those signals should be routed to J6.
272 The 100Base-T1 signals are available in connector ``P9`` and can be converted to
