Searched refs:MT_P_RW_U_NA (Results 1 – 17 of 17) sorted by relevance
| /Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
19 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
22 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
26 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
30 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
33 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
36 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
41 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
44 DT_REG_SIZE(DT_NODELABEL(outbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
47 DT_REG_SIZE(DT_NODELABEL(inbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/a53/ |
| D | mmu_regions.c | 16 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
21 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
26 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
31 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
36 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
41 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
44 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
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| /Zephyr-latest/soc/intel/intel_socfpga/agilex/ |
| D | mmu_regions.c | 17 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
22 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
27 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
32 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
37 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/nxp/imx/imx9/imx95/a55/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
19 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
22 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
25 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
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| /Zephyr-latest/soc/brcm/bcmvk/viper/a72/ |
| D | mmu_regions.c | 20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_SECURE),
24 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_SECURE),
28 MT_NORMAL | MT_P_RW_U_NA | MT_SECURE),
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| /Zephyr-latest/soc/arm/fvp_aemv8a/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/xen/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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| /Zephyr-latest/soc/arm/qemu_cortex_a53/ |
| D | mmu_regions.c | 16 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
21 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/arm/qemu_virt_arm64/ |
| D | mmu_regions.c | 16 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
21 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/brcm/bcm2711/ |
| D | mmu_regions.c | 14 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
19 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/brcm/bcm2712/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/nxp/layerscape/ls1046a/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/rockchip/rk3399/ |
| D | mmu_regions.c | 15 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
20 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/soc/ti/k3/am6x/a53/ |
| D | mmu_regions.c | 16 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
21 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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| /Zephyr-latest/soc/intel/intel_socfpga/agilex5/ |
| D | mmu_regions.c | 14 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
25 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | arm_mmu.h | 83 #define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) macro
207 {MT_P_RW_U_NA})
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| /Zephyr-latest/arch/arm64/core/ |
| D | mmu.c | 810 .attrs = MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE },
1566 #define MT_SCRATCH (MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE)
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