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/Zephyr-latest/kernel/include/
Dgen_offset.h84 #define GEN_OFFSET_SYM(S, M) \ argument
85 GEN_ABSOLUTE_SYM(__##S##_##M##_##OFFSET, offsetof(S, M))
87 #define GEN_OFFSET_STRUCT(S, M) \ argument
88 GEN_ABSOLUTE_SYM(__struct_##S##_##M##_##OFFSET, offsetof(struct S, M))
90 #define GEN_NAMED_OFFSET_SYM(S, M, N) \ argument
91 GEN_ABSOLUTE_SYM(__##S##_##N##_##OFFSET, offsetof(S, M))
93 #define GEN_NAMED_OFFSET_STRUCT(S, M, N) \ argument
94 GEN_ABSOLUTE_SYM(__struct_##S##_##N##_##OFFSET, offsetof(struct S, M))
/Zephyr-latest/samples/subsys/rtio/sensor_batch_processing/src/
Dmain.c14 #define M (N/2) macro
21 #define PROCESS_TIME ((M - 1) * SAMPLE_PERIOD)
39 uint8_t *userdata[M] = {0}; in main()
40 uint32_t data_len[M] = {0}; in main()
42 LOG_INF("Submitting %d read requests", M); in main()
43 rtio_submit(&ez_io, M); in main()
49 while (m < M) { in main()
76 LOG_INF("Start processing %d samples", M); in main()
77 for (m = 0; m < M; m++) { in main()
81 LOG_INF("Finished processing %d samples", M); in main()
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/Zephyr-latest/samples/tfm_integration/
Dtfm_integration.rst2 :name: TF-M Integration
5 These TF-M integration examples can be used with a supported Armv8-M board, and demonstrate how
6 the TF-M APIs can be used with Zephyr.
16 built, in addition to the TF-M S and Zephyr NS binary images. The S and NS
23 What is Trusted Firmware-M (TF-M)?
26 Trusted Firmware-M (TF-M) is the reference implementation of `Platform Security
29 TF-M provides a highly configurable set of software components to create a
32 Additionally, secure boot in TF-M ensures integrity of run time software and
35 The current TF-M implementation specifically targets TrustZone for ARMv8-M.
37 Trusted Firmware-M source code is available at
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/Zephyr-latest/cmake/toolchain/llvm/
Dtarget.cmake11 # ARMv8-M mainline is ARMv7-M with additional features from ARMv8-M.
14 # ARMv8-M baseline is ARMv6-M with additional features from ARMv8-M.
17 # ARMV7_M_ARMV8_M_MAINLINE means that ARMv7-M or backward compatible ARMv8-M
21 # ARMV6_M_ARMV8_M_BASELINE means that ARMv6-M or ARMv8-M supporting the
/Zephyr-latest/samples/tfm_integration/psa_crypto/boards/
Dnrf9160dk_nrf9160_ns.overlay8 * for the Secure (TF-M) firmware for the configuration that is
12 /* Increase the size of the Secure Firmware (TF-M).
14 * since TF-M region definitions are configured
15 * statically in the TF-M project.
23 * TF-M.
34 /* Disable UART1, because it is used by default in TF-M */
/Zephyr-latest/samples/tfm_integration/tfm_ipc/boards/
Dnrf9160dk_nrf9160_ns.overlay8 * for the Secure (TF-M) firmware for the configuration that is
12 /* Increase the size of the Secure Firmware (TF-M).
14 * since TF-M region definitions are configured
15 * statically in the TF-M project.
23 * TF-M.
34 /* Disable UART1, because it is used by default in TF-M */
/Zephyr-latest/doc/services/tfm/
Dintegration.rst1 Trusted Firmware-M Integration
4 The Trusted Firmware-M (TF-M) section contains information about the
5 integration between TF-M and Zephyr RTOS. Use this information to help
6 understand how to integrate TF-M with Zephyr for Cortex-M platforms and make
12 TF-M will be built for the secure processing environment along with Zephyr if
16 and all config flags required for TF-M should be set in a board variant with
23 to the board name that TF-M expects for this target, so that it knows which
34 non-secure image, linked with TF-M as an external project, and optionally the
43 the required space for TF-M and the secure bootloader:
52 /* The memory regions defined below must match what the TF-M
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Dtestsuites.rst4 TF-M includes two sets of test suites:
6 * tf-m-tests - Standard TF-M specific regression tests
12 TF-M Regression Tests
20 application (TF-M).
27 being followed by the secure application, TF-M being an implementation of
37 your specific board, RTOS (Zephyr here), and PSA implementation (TF-M in this
41 changes to TF-M, such as enabling a new TF-M board target, or making changes
42 to the core TF-M module(s). They should generally be run as a coherence check
Dbuild.rst3 TF-M Build System
6 When building a valid ``_ns`` board target, TF-M will be built in the
8 of TF-M's build system is required in most cases, and the following will
9 build a TF-M and Zephyr image pair, and run it in qemu with no additional
20 Images Created by the TF-M Build
23 The TF-M build system creates the following executable files:
25 * tfm_s - TF-M secure firmware
26 * tfm_ns - TF-M non-secure app (only used by regression tests).
27 * bl2 - TF-M MCUboot, if enabled
31 The TF-M build system also creates signed variants of tfm_s and tfm_ns, and a
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Dindex.rst3 Trusted Firmware-M (TF-M)
Doverview.rst1 Trusted Firmware-M Overview
4 `Trusted Firmware-M (TF-M) <https://tf-m-user-guide.trustedfirmware.org/>`__
10 Zephyr RTOS has been PSA Certified since Zephyr 2.0.0 with TF-M 1.0, and
11 is currently integrated with TF-M 2.1.0.
13 What Does TF-M Offer?
16 Through a set of secure services and by design, TF-M provides:
29 When using TF-M with a supported platform, TF-M will be automatically built and
31 build process makes a number of assumptions about how TF-M is being used, and
35 * The secure processing environment (secure boot and TF-M) starts first
41 A TF-M application will, generally, have the following three parts, from most
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/Zephyr-latest/modules/trusted-firmware-m/
DKconfig.tfm1 # Configuration for the TF-M Module
33 bool "Build with TF-M as the Secure Execution Environment"
44 additionally generate a TF-M image for the Secure Execution
49 TF-M and Zephyr images, as well as the veneer object file that links
73 prompt "TF-M build profile"
76 The TF-M build profile selection. Can be empty (not set),
78 TF-M configuration options, namely, the IPC model and the
82 bool "TF-M build profile: not set (base)"
85 bool "TF-M build profile: small"
88 bool "TF-M build profile: medium"
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/Zephyr-latest/samples/boards/nxp/adsp/number_crunching/src/
Dcmsis_dsp_wrapper.c47 void real_block_iir_32(int M, const int32_t *coef_sos, const int16_t *coef_g, in real_block_iir_32() argument
57 q31_t biquadStateBandQ31[4 * M]; in real_block_iir_32()
65 arm_biquad_cascade_df1_init_q31(&handle, M, coef_sos, &biquadStateBandQ31[0], 2); in real_block_iir_32()
71 int32_t mu, int block_size, int M) in lms_iir_32() argument
76 arm_lms_init_q31(&handle, M, coef, ref, mu, block_size, 0); in lms_iir_32()
Dnature_dsp_wrapper.c49 void real_block_iir_32(int M, const int32_t *coef_sos, const int16_t *coef_g, in real_block_iir_32() argument
62 handle = bqriir32x32_df1_init(objmem, M, coef_sos, coef_g, 0); in real_block_iir_32()
74 int32_t mu, int block_size, int M) in lms_iir_32() argument
93 fir_blms32x32(err, coef, input, ref, norm64, mu, block_size, M); in lms_iir_32()
/Zephyr-latest/drivers/sensor/explorir_m/
DKconfig1 # ExplorIR-M CO2 sensor configuration options
7 bool "ExplorIR-M CO2 Sensor"
13 Enable driver for ExplorIR-M CO2 Sensor.
/Zephyr-latest/arch/arm/core/cortex_m/
DKconfig1 # ARM Cortex-M platform configuration options
113 Trace (DWT) unit specified by the ARMv7-M and above.
115 While ARMv6-M does define a "DWT" unit, this is significantly different
116 from the DWT specified by the ARMv7-M and above in terms of both feature
129 Always present in CPUs that implement the ARMv7-M or
130 ARM8-M Mainline architectures.
139 in CPUs implementing the ARMv7-M or ARMv8-M architectures.
140 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline
152 can descend. MSPLIM, PSPLIM are always present in ARMv8-M
153 MCUs that implement the ARMv8-M Main Extension (Mainline).
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/Zephyr-latest/tests/arch/arm/arm_irq_advanced_features/
DREADME.txt1 Title: Test to verify advanced features of ARM Cortex-M interrupt handling.
10 Only for ARMv7-M and ARMv8-M Mainline targets.
16 Only for ARMv7-M and ARMv8-M Mainline targets.
19 TrustZone-M enabled Cortex-M Mainline CPUs.
/Zephyr-latest/doc/connectivity/bluetooth/img/
Datt_timeout.svg1 …M 38.93352592923047 55.049635120999994 L 38.93352592923047 300.077684621" stroke-miterlimit="10" s…
/Zephyr-latest/soc/gaisler/gr716a/
Dlinker.ld23 extprom (rx) : ORIGIN = 0x01000000, LENGTH = 16M
24 spi0 (rx) : ORIGIN = 0x02000000, LENGTH = 32M
25 spi1 (rx) : ORIGIN = 0x04000000, LENGTH = 32M
28 extram (rwx) : ORIGIN = 0x40000000, LENGTH = 256M
/Zephyr-latest/doc/services/portability/
Dcmsis_rtos_v1.rst6 Cortex-M Software Interface Standard (CMSIS) RTOS is a vendor-independent
7 hardware abstraction layer for the ARM Cortex-M processor series and defines
8 generic tool interfaces. Though it was originally defined for ARM Cortex-M
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst3 Arm Cortex-M Developer Guide
9 This page contains detailed information about the status of the Arm Cortex-M
11 developing Zephyr applications for Arm Cortex-M-based platforms.
17 Arm Cortex-M implementation variants.
23 … | Arm v6-M | Arm v7-M | Arm v8-M …
73 | | Native TrustZone-M support | N | N |…
75 | | TF-M integration | N | N |…
99 Each Zephyr thread is defined with its own stack memory. By default, Cortex-M enforces a double wor…
102 In Arm v6-M and Arm v7-M architecture variants, thread stacks are additionally required to align wi…
104 …nfig:option:`CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT`, that is enforced in Arm v6-M and Arm v7-M
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/Zephyr-latest/arch/arm/core/mpu/
DKconfig23 The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
26 The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
29 The ARMv8-M MPU requires the active MPU regions be non-overlapping.
30 As a result of this, the ARMv8-M MPU needs to fully partition the
34 of the ARMv8-M background memory map. The application developer may
38 SRAM area covered only by the default ARMv8-M memory map. This
46 of full partitioning the default behavior for the ARMv8-M MPU
77 128, to accommodate the length of a Cortex-M exception stack
96 MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
100 and sub-regions(ARMv7-M) to cover this feature.
/Zephyr-latest/samples/tfm_integration/tfm_ipc/
DREADME.rst2 :name: TF-M IPC
9 This is a simple TF-M integration example that can be used with an ARMv8-M
12 It uses **IPC Mode** for communication, where TF-M API calls are made to the
16 Zephyr uses Trusted Firmware (TF-M) Platform Security Architecture (PSA) APIs
23 The sample reboots after 5 seconds to demonstrate rebooting with TF-M.
24 The sys_reboot call is routed to TF-M, since the nonsecure app is not allowed
67 IMAGE1FILE: \SOFTWARE\tfm_sign.bin ; TF-M with application binary blob
86 dual core ARM Cortex-M33 setup, also allows you to run TF-M tests using QEMU if
87 you don't have access to a supported ARMv8-M development board.
94 qemu-system-arm -M mps2-an521 -device loader,file=build/zephyr/tfm_merged.hex -serial stdio
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/Zephyr-latest/samples/tfm_integration/tfm_secure_partition/
DREADME.rst2 :name: TF-M Secure Partition
9 A Secure Partition is an isolated module that resides in TF-M. It exposes a number of functions or
10 "secure services" to other partitions and/or to the non-secure firmware. TF-M already contains
14 This sample creates a dummy secure partition and secure service for TF-M and instructs the TF-M
22 build files and build configuration files. The partition is built by the TF-M build system, refer to
25 For more information on how to add custom secure partitions refer to TF-M's guide:
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig145 bool "SPI flash size 0.5M or 1M Bytes"
147 The SPI flash size is 0.5M or 1M Bytes.
150 bool "SPI flash size 2M Bytes"
152 The SPI flash size is 2M Bytes.
155 bool "SPI flash size 4M Bytes"
157 The SPI flash size is 4M Bytes.
160 bool "SPI flash size 8M Bytes"
162 The SPI flash size is 8M Bytes.
165 bool "SPI flash size 16M Bytes"
167 The SPI flash size is 16M Bytes.

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