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Searched refs:GD32_RESET_TIMER4 (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32vf103.h46 #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) macro
Dgd32e10x.h50 #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) macro
Dgd32e50x.h56 #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 2U) macro
Dgd32f4xx.h66 #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) macro
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi374 resets = <&rctl GD32_RESET_TIMER4>;
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi372 resets = <&rctl GD32_RESET_TIMER4>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi315 resets = <&rctl GD32_RESET_TIMER4>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi466 resets = <&rctl GD32_RESET_TIMER4>;