Searched refs:GD32_RESET_TIMER12 (Results 1 – 8 of 8) sorted by relevance
54 #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) macro
55 #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) macro
60 #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) macro
70 #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) macro
104 resets = <&rctl GD32_RESET_TIMER12>;
440 resets = <&rctl GD32_RESET_TIMER12>;
464 resets = <&rctl GD32_RESET_TIMER12>;
592 resets = <&rctl GD32_RESET_TIMER12>;