Searched refs:GD32_RESET_SPI0 (Results 1 – 12 of 12) sorted by relevance
33 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
67 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
38 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
64 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
39 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
41 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
99 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) macro
142 resets = <&rctl GD32_RESET_SPI0>;
188 resets = <&rctl GD32_RESET_SPI0>;
123 resets = <&rctl GD32_RESET_SPI0>;
197 resets = <&rctl GD32_RESET_SPI0>;
