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Searched refs:DT_REG_SIZE_BY_IDX (Results 1 – 25 of 30) sorted by relevance

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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dlinker.ld17 #if (DT_REG_SIZE_BY_IDX(DT_NODELABEL(flexspi1), 1) > 0)
18 …: ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi1), 1), LENGTH = DT_REG_SIZE_BY_IDX(DT_NODELABEL…
20 #if (DT_REG_SIZE_BY_IDX(DT_NODELABEL(flexspi2), 1) > 0)
21 …: ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi2), 1), LENGTH = DT_REG_SIZE_BY_IDX(DT_NODELABEL…
/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
Dmmu_regions.c24 DT_REG_SIZE_BY_IDX(DT_NODELABEL(pinmux), 0),
29 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
34 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/arm/fvp_aemv8a/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/xen/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/arm/qemu_cortex_a53/
Dmmu_regions.c15 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
20 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/arm/qemu_virt_arm64/
Dmmu_regions.c15 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
20 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/brcm/bcm2711/
Dmmu_regions.c13 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/brcm/bcm2712/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/nxp/layerscape/ls1046a/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/renesas/rcar/rcar_gen3/
Dmmu_regions.c13 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/renesas/rcar/rcar_gen4/a55/
Dmmu_regions.c13 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/rockchip/rk3399/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/rockchip/rk3568/
Dmmu_regions.c16 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
21 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/ti/k3/am6x/a53/
Dmmu_regions.c15 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
20 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/nxp/imx/imx9/imx95/a55/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
18 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
Dmmu_regions.c31 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
36 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c15 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
20 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory_regions.h20 #define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0)
/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c14 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
18 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.c93 #define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))
Dintc_gicv3_priv.h33 #define GIC_RDIST_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1)
/Zephyr-latest/drivers/xen/
Dgnttab.c38 #define GNTTAB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, xen_xen), 0)
/Zephyr-latest/tests/drivers/gpio/gpio_ite_it8xxx2_v2/src/
Dmain.c23 uint8_t gpcr[DT_REG_SIZE_BY_IDX(MY_GPIO, 4)];
60 r < DT_REG_ADDR_BY_IDX(MY_GPIO, 4) + DT_REG_SIZE_BY_IDX(MY_GPIO, 4)) { in fake_ecreg()
/Zephyr-latest/include/zephyr/
Ddevicetree.h2441 #define DT_REG_SIZE_BY_IDX(node_id, idx) \ macro
2472 #define DT_REG_SIZE(node_id) DT_REG_SIZE_BY_IDX(node_id, 0)
4440 DT_REG_SIZE_BY_IDX(DT_DRV_INST(inst), idx)
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi.c404 DT_REG_SIZE_BY_IDX(node_id, 1)))

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